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From: Jianjun Wang <jianjun.wang@mediatek.com>
To: Bjorn Helgaas <bhelgaas@google.com>,
	Rob Herring <robh+dt@kernel.org>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Ryder Lee <ryder.lee@mediatek.com>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	<linux-pci@vger.kernel.org>, <linux-mediatek@lists.infradead.org>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>, <youlin.pei@mediatek.com>,
	<chuanjia.liu@mediatek.com>, <qizhong.cheng@mediatek.com>,
	<sin_jieyang@mediatek.com>, <drinkcat@chromium.org>,
	<Rex-BC.Chen@mediatek.com>, Krzysztof Wilczyski <kw@linux.com>,
	<Ryan-JH.Yu@mediatek.com>
Subject: Re: [PATCH 2/2] PCI: mediatek-gen3: Add support for disable dvfsrc voltage request
Date: Wed, 26 May 2021 15:44:34 +0800	[thread overview]
Message-ID: <1622015074.22554.7.camel@mhfsdcap03> (raw)
In-Reply-To: <20210514065927.20774-3-jianjun.wang@mediatek.com>

Hi Bjorn, Rob, Lorenzo,

Could you please help to take a look at this patch, I'm not sure if this
is a good solution, and I really need your suggestions.

Thanks.

On Fri, 2021-05-14 at 14:59 +0800, Jianjun Wang wrote:
> PCIe Gen3 PHY layer cannot work properly when the requested voltage
> is lower than a specific level(e.g. 0.55V, it's depends on
> the chip manufacturing process).
> 
> When the dvfsrc feature is implemented, the requested voltage
> may be reduced to a lower level in suspend mode, hence that
> the MAC layer will assert a HW signal to request the dvfsrc
> to raise voltage to normal mode, and it will wait the voltage
> ready signal which is derived from dvfsrc to determine whether
> the LTSSM can start normally.
> 
> When the dvfsrc feature is not implemented, the MAC layer still
> assert the voltage request to dvfsrc when exit suspend mode,
> but will not receive the voltage ready signal, in this case,
> the LTSSM cannot start normally, and the PCIe link will be failed.
> 
> Add support for disable dvfsrc voltage request. If the property of
> "disable-dvfsrc-vlt-req" is presented in device node, we assume that
> the requested voltage is always higher enough to keep the PCIe Gen3
> PHY active, and the voltage request to dvfsrc should be disabled.
> 
> Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
> ---
>  drivers/pci/controller/pcie-mediatek-gen3.c | 32 +++++++++++++++++++++
>  1 file changed, 32 insertions(+)
> 
> diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
> index 20165e4a75b2..d1864303217e 100644
> --- a/drivers/pci/controller/pcie-mediatek-gen3.c
> +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> @@ -68,6 +68,9 @@
>  #define PCIE_MSI_SET_ENABLE_REG		0x190
>  #define PCIE_MSI_SET_ENABLE		GENMASK(PCIE_MSI_SET_NUM - 1, 0)
>  
> +#define PCIE_MISC_CTRL_REG		0x348
> +#define PCIE_DISABLE_DVFSRC_VLT_REQ	BIT(1)
> +
>  #define PCIE_MSI_SET_BASE_REG		0xc00
>  #define PCIE_MSI_SET_OFFSET		0x10
>  #define PCIE_MSI_SET_STATUS_OFFSET	0x04
> @@ -297,6 +300,35 @@ static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
>  	val &= ~PCIE_INTX_ENABLE;
>  	writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG);
>  
> +	/*
> +	 * PCIe Gen3 PHY layer can not work properly when the requested voltage
> +	 * is lower than a specific level(e.g. 0.55V, it's depends on
> +	 * the chip manufacturing process).
> +	 *
> +	 * When the dvfsrc feature is implemented, the requested voltage
> +	 * may be reduced to a lower level in suspend mode, hence that
> +	 * the MAC layer will assert a HW signal to request the dvfsrc
> +	 * to raise voltage to normal mode, and it will wait the voltage
> +	 * ready signal which is derived from dvfsrc to determine whether
> +	 * the LTSSM can start normally.
> +	 *
> +	 * When the dvfsrc feature is not implemented, the MAC layer still
> +	 * assert the voltage request to dvfsrc when exit suspend mode,
> +	 * but will not receive the voltage ready signal, in this case,
> +	 * the LTSSM cannot start normally, and the PCIe link will be failed.
> +	 *
> +	 * If the property of "disable-dvfsrc-vlt-req" is presented
> +	 * in device node, we assume that the requested voltage is always
> +	 * higher enough to keep the PCIe Gen3 PHY active, and the voltage
> +	 * request to dvfsrc should be disabled.
> +	 */
> +	val = readl_relaxed(port->base + PCIE_MISC_CTRL_REG);
> +	val &= ~PCIE_DISABLE_DVFSRC_VLT_REQ;
> +	if (of_property_read_bool(port->dev->of_node, "disable-dvfsrc-vlt-req"))
> +		val |= PCIE_DISABLE_DVFSRC_VLT_REQ;
> +
> +	writel(val, port->base + PCIE_MISC_CTRL_REG);
> +
>  	/* Assert all reset signals */
>  	val = readl_relaxed(port->base + PCIE_RST_CTRL_REG);
>  	val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB;

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      reply	other threads:[~2021-05-26  7:46 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-14  6:59 [PATCH 0/2] PCI: mediatek-gen3: Add support for disable dvfsrc Jianjun Wang
2021-05-14  6:59 ` [PATCH 1/2] dt-bindings: PCI: mediatek-gen3: Add property to disable dvfsrc voltage request Jianjun Wang
2021-05-14  6:59 ` [PATCH 2/2] PCI: mediatek-gen3: Add support for " Jianjun Wang
2021-05-26  7:44   ` Jianjun Wang [this message]

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