From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9743FC11F65 for ; Wed, 30 Jun 2021 06:06:49 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5915661CA5 for ; Wed, 30 Jun 2021 06:06:49 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5915661CA5 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Date:CC:To:From:Subject:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=iwLqZRmuzeJ5OhbsN4tNibMZVzjlWQwPSL+dPbO6F18=; b=zCZLCIRhDgiJ1W PSNgZBBW/05lSvYFhi/mvIVPOkcd+sfxyQqdc4r+lz45XrKXZGT91tx2Um+sFlG0WevVXkJBwmmo0 ry/xCc2/uns+r1Jss0MFPYUka8ORwnLSsDvCZ8UMJ5DnKbcpxXdtanFqzPG6hIHd0QdfDO4e1y5fj SfpYvMTUhUCARE9G+GIFxpZlxwXOdjWNO1GE9NF7YvGtQe03jzxTENn/hAEKsnc0Nc0JFcwAoocj5 2X1+wzxtCZRoHuUhlXRiXh73BF8EUEs9pUur0FzMZ2b7Py4VdlDXIBRlqrlG3ex4Tbki3blDV6gRu PvdkjN3bcm+JQ4l01NeA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lyTKs-00Ct8G-CT; Wed, 30 Jun 2021 06:04:34 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1lyTKm-00Ct7Y-V5; Wed, 30 Jun 2021 06:04:31 +0000 X-UUID: b7c863231a91454aa7f8cf21a904846f-20210629 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=oQ3O+Pugqw5jM2kl7I+NmHKVQNpcutFzQPIN+4YVbnQ=; b=ns37k6uxVu4dfhz025p34+9L7syQoLN141JL3t5xsMMw4FNxxb9Usqr8IoNOL4vE14hVFTe0iucSIuaL9fMS88tFOetPNA8rXN63i8orPzj6m8oV2HFeyQyF0l6Ac77SRQFQYrwB4ZZzabcQbtuHuLks2p2iQevIXQPFVv7X0Ig=; X-UUID: b7c863231a91454aa7f8cf21a904846f-20210629 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 876818121; Tue, 29 Jun 2021 23:04:24 -0700 Received: from MTKMBS31N1.mediatek.inc (172.27.4.69) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 29 Jun 2021 22:54:21 -0700 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS31N1.mediatek.inc (172.27.4.69) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 30 Jun 2021 13:54:12 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 30 Jun 2021 13:54:11 +0800 Message-ID: <1625032452.22227.1.camel@mhfsdcap03> Subject: Re: [PATCH v10 1/4] dt-bindings: PCI: mediatek: Update the Device tree bindings From: Chuanjia Liu To: CC: , , , , , , , , , , Date: Wed, 30 Jun 2021 13:54:12 +0800 In-Reply-To: <20210611060902.12418-2-chuanjia.liu@mediatek.com> References: <20210611060902.12418-1-chuanjia.liu@mediatek.com> <20210611060902.12418-2-chuanjia.liu@mediatek.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: F391D42AA23CBBEF51E781104F08752640D7F562AE039ECC44C6BBD9E8644E892000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210629_230429_062130_0C54F7A9 X-CRM114-Status: GOOD ( 22.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, lorenzo Gentle ping for this series, Please let me know if you want I change something. thanks chuanjia On Fri, 2021-06-11 at 14:08 +0800, Chuanjia Liu wrote: > There are two independent PCIe controllers in MT2712 and MT7622 > platform. Each of them should contain an independent MSI domain. > > In old dts architecture, MSI domain will be inherited from the root > bridge, and all of the devices will share the same MSI domain. > Hence that, the PCIe devices will not work properly if the irq number > which required is more than 32. > > Split the PCIe node for MT2712 and MT7622 platform to comply with > the hardware design and fix MSI issue. > > Signed-off-by: Chuanjia Liu > Acked-by: Ryder Lee > Reviewed-by: Rob Herring > --- > .../bindings/pci/mediatek-pcie-cfg.yaml | 39 ++++ > .../devicetree/bindings/pci/mediatek-pcie.txt | 201 ++++++++++-------- > 2 files changed, 146 insertions(+), 94 deletions(-) > create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml > > diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml > new file mode 100644 > index 000000000000..841a3d284bbf > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml > @@ -0,0 +1,39 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pci/mediatek-pcie-cfg.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek PCIECFG controller > + > +maintainers: > + - Chuanjia Liu > + - Jianjun Wang > + > +description: | > + The MediaTek PCIECFG controller controls some feature about > + LTSSM, ASPM and so on. > + > +properties: > + compatible: > + items: > + - enum: > + - mediatek,generic-pciecfg > + - const: syscon > + > + reg: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + > +additionalProperties: false > + > +examples: > + - | > + pciecfg: pciecfg@1a140000 { > + compatible = "mediatek,generic-pciecfg", "syscon"; > + reg = <0x1a140000 0x1000>; > + }; > +... > diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt > index 7468d666763a..604792c9b1dc 100644 > --- a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt > +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt > @@ -8,7 +8,7 @@ Required properties: > "mediatek,mt7623-pcie" > "mediatek,mt7629-pcie" > - device_type: Must be "pci" > -- reg: Base addresses and lengths of the PCIe subsys and root ports. > +- reg: Base addresses and lengths of the root ports. > - reg-names: Names of the above areas to use during resource lookup. > - #address-cells: Address representation for root ports (must be 3) > - #size-cells: Size representation for root ports (must be 2) > @@ -143,130 +143,143 @@ Examples for MT7623: > > Examples for MT2712: > > - pcie: pcie@11700000 { > + pcie1: pcie@112ff000 { > compatible = "mediatek,mt2712-pcie"; > device_type = "pci"; > - reg = <0 0x11700000 0 0x1000>, > - <0 0x112ff000 0 0x1000>; > - reg-names = "port0", "port1"; > + reg = <0 0x112ff000 0 0x1000>; > + reg-names = "port1"; > + linux,pci-domain = <1>; > #address-cells = <3>; > #size-cells = <2>; > - interrupts = , > - ; > - clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, > - <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, > - <&pericfg CLK_PERI_PCIE0>, > + interrupts = ; > + interrupt-names = "pcie_irq"; > + clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, > <&pericfg CLK_PERI_PCIE1>; > - clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1"; > - phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>; > - phy-names = "pcie-phy0", "pcie-phy1"; > + clock-names = "sys_ck1", "ahb_ck1"; > + phys = <&u3port1 PHY_TYPE_PCIE>; > + phy-names = "pcie-phy1"; > bus-range = <0x00 0xff>; > - ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; > + ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>; > + status = "disabled"; > > - pcie0: pcie@0,0 { > - reg = <0x0000 0 0 0 0>; > - #address-cells = <3>; > - #size-cells = <2>; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = <0 0 0 1 &pcie_intc1 0>, > + <0 0 0 2 &pcie_intc1 1>, > + <0 0 0 3 &pcie_intc1 2>, > + <0 0 0 4 &pcie_intc1 3>; > + pcie_intc1: interrupt-controller { > + interrupt-controller; > + #address-cells = <0>; > #interrupt-cells = <1>; > - ranges; > - interrupt-map-mask = <0 0 0 7>; > - interrupt-map = <0 0 0 1 &pcie_intc0 0>, > - <0 0 0 2 &pcie_intc0 1>, > - <0 0 0 3 &pcie_intc0 2>, > - <0 0 0 4 &pcie_intc0 3>; > - pcie_intc0: interrupt-controller { > - interrupt-controller; > - #address-cells = <0>; > - #interrupt-cells = <1>; > - }; > }; > + }; > > - pcie1: pcie@1,0 { > - reg = <0x0800 0 0 0 0>; > - #address-cells = <3>; > - #size-cells = <2>; > + pcie0: pcie@11700000 { > + compatible = "mediatek,mt2712-pcie"; > + device_type = "pci"; > + reg = <0 0x11700000 0 0x1000>; > + reg-names = "port0"; > + linux,pci-domain = <0>; > + #address-cells = <3>; > + #size-cells = <2>; > + interrupts = ; > + interrupt-names = "pcie_irq"; > + clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, > + <&pericfg CLK_PERI_PCIE0>; > + clock-names = "sys_ck0", "ahb_ck0"; > + phys = <&u3port0 PHY_TYPE_PCIE>; > + phy-names = "pcie-phy0"; > + bus-range = <0x00 0xff>; > + ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; > + status = "disabled"; > + > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = <0 0 0 1 &pcie_intc0 0>, > + <0 0 0 2 &pcie_intc0 1>, > + <0 0 0 3 &pcie_intc0 2>, > + <0 0 0 4 &pcie_intc0 3>; > + pcie_intc0: interrupt-controller { > + interrupt-controller; > + #address-cells = <0>; > #interrupt-cells = <1>; > - ranges; > - interrupt-map-mask = <0 0 0 7>; > - interrupt-map = <0 0 0 1 &pcie_intc1 0>, > - <0 0 0 2 &pcie_intc1 1>, > - <0 0 0 3 &pcie_intc1 2>, > - <0 0 0 4 &pcie_intc1 3>; > - pcie_intc1: interrupt-controller { > - interrupt-controller; > - #address-cells = <0>; > - #interrupt-cells = <1>; > - }; > }; > }; > > Examples for MT7622: > > - pcie: pcie@1a140000 { > + pcie0: pcie@1a143000 { > compatible = "mediatek,mt7622-pcie"; > device_type = "pci"; > - reg = <0 0x1a140000 0 0x1000>, > - <0 0x1a143000 0 0x1000>, > - <0 0x1a145000 0 0x1000>; > - reg-names = "subsys", "port0", "port1"; > + reg = <0 0x1a143000 0 0x1000>; > + reg-names = "port0"; > + linux,pci-domain = <0>; > #address-cells = <3>; > #size-cells = <2>; > - interrupts = , > - ; > + interrupts = ; > + interrupt-names = "pcie_irq"; > clocks = <&pciesys CLK_PCIE_P0_MAC_EN>, > - <&pciesys CLK_PCIE_P1_MAC_EN>, > <&pciesys CLK_PCIE_P0_AHB_EN>, > - <&pciesys CLK_PCIE_P1_AHB_EN>, > <&pciesys CLK_PCIE_P0_AUX_EN>, > - <&pciesys CLK_PCIE_P1_AUX_EN>, > <&pciesys CLK_PCIE_P0_AXI_EN>, > - <&pciesys CLK_PCIE_P1_AXI_EN>, > <&pciesys CLK_PCIE_P0_OBFF_EN>, > - <&pciesys CLK_PCIE_P1_OBFF_EN>, > - <&pciesys CLK_PCIE_P0_PIPE_EN>, > - <&pciesys CLK_PCIE_P1_PIPE_EN>; > - clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1", > - "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1", > - "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1"; > - phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>; > - phy-names = "pcie-phy0", "pcie-phy1"; > + <&pciesys CLK_PCIE_P0_PIPE_EN>; > + clock-names = "sys_ck0", "ahb_ck0", "aux_ck0", > + "axi_ck0", "obff_ck0", "pipe_ck0"; > + > power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; > bus-range = <0x00 0xff>; > - ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; > + ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>; > + status = "disabled"; > > - pcie0: pcie@0,0 { > - reg = <0x0000 0 0 0 0>; > - #address-cells = <3>; > - #size-cells = <2>; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = <0 0 0 1 &pcie_intc0 0>, > + <0 0 0 2 &pcie_intc0 1>, > + <0 0 0 3 &pcie_intc0 2>, > + <0 0 0 4 &pcie_intc0 3>; > + pcie_intc0: interrupt-controller { > + interrupt-controller; > + #address-cells = <0>; > #interrupt-cells = <1>; > - ranges; > - interrupt-map-mask = <0 0 0 7>; > - interrupt-map = <0 0 0 1 &pcie_intc0 0>, > - <0 0 0 2 &pcie_intc0 1>, > - <0 0 0 3 &pcie_intc0 2>, > - <0 0 0 4 &pcie_intc0 3>; > - pcie_intc0: interrupt-controller { > - interrupt-controller; > - #address-cells = <0>; > - #interrupt-cells = <1>; > - }; > }; > + }; > > - pcie1: pcie@1,0 { > - reg = <0x0800 0 0 0 0>; > - #address-cells = <3>; > - #size-cells = <2>; > + pcie1: pcie@1a145000 { > + compatible = "mediatek,mt7622-pcie"; > + device_type = "pci"; > + reg = <0 0x1a145000 0 0x1000>; > + reg-names = "port1"; > + linux,pci-domain = <1>; > + #address-cells = <3>; > + #size-cells = <2>; > + interrupts = ; > + interrupt-names = "pcie_irq"; > + clocks = <&pciesys CLK_PCIE_P1_MAC_EN>, > + /* designer has connect RC1 with p0_ahb clock */ > + <&pciesys CLK_PCIE_P0_AHB_EN>, > + <&pciesys CLK_PCIE_P1_AUX_EN>, > + <&pciesys CLK_PCIE_P1_AXI_EN>, > + <&pciesys CLK_PCIE_P1_OBFF_EN>, > + <&pciesys CLK_PCIE_P1_PIPE_EN>; > + clock-names = "sys_ck1", "ahb_ck1", "aux_ck1", > + "axi_ck1", "obff_ck1", "pipe_ck1"; > + > + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; > + bus-range = <0x00 0xff>; > + ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>; > + status = "disabled"; > + > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = <0 0 0 1 &pcie_intc1 0>, > + <0 0 0 2 &pcie_intc1 1>, > + <0 0 0 3 &pcie_intc1 2>, > + <0 0 0 4 &pcie_intc1 3>; > + pcie_intc1: interrupt-controller { > + interrupt-controller; > + #address-cells = <0>; > #interrupt-cells = <1>; > - ranges; > - interrupt-map-mask = <0 0 0 7>; > - interrupt-map = <0 0 0 1 &pcie_intc1 0>, > - <0 0 0 2 &pcie_intc1 1>, > - <0 0 0 3 &pcie_intc1 2>, > - <0 0 0 4 &pcie_intc1 3>; > - pcie_intc1: interrupt-controller { > - interrupt-controller; > - #address-cells = <0>; > - #interrupt-cells = <1>; > - }; > }; > }; _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel