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From: Stephen Boyd <sboyd@kernel.org>
To: Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
	linux-clk@vger.kernel.org, mturquette@baylibre.com
Cc: narmstrong@baylibre.com, jbrunet@baylibre.com,
	khilman@baylibre.com, linux-kernel@vger.kernel.org,
	linux-amlogic@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org,
	Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Subject: Re: [PATCH v3 3/3] clk: meson: regmap: switch to determine_rate for the dividers
Date: Wed, 30 Jun 2021 11:39:20 -0700	[thread overview]
Message-ID: <162507836069.3331010.6408437361041793201@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <20210627223959.188139-4-martin.blumenstingl@googlemail.com>

Quoting Martin Blumenstingl (2021-06-27 15:39:59)
> This increases the maxmium supported frequency on 32-bit systems from
> 2^31 (signed long as used by clk_ops.round_rate, maximum value:
> approx. 2.14GHz) to 2^32 (unsigned long as used by
> clk_ops.determine_rate, maximum value: approx. 4.29GHz).
> On Meson8/8b/8m2 the HDMI PLL and it's OD (post-dividers) are
> capable of running at up to 2.97GHz. So switch the divider
> implementation in clk-regmap to clk_ops.determine_rate to support these
> higher frequencies on 32-bit systems.
> 
> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---

Applied to clk-next

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      reply	other threads:[~2021-06-30 18:41 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-27 22:39 [PATCH v3 0/3] clk: meson: rounding for fast clocks on 32-bit SoCs Martin Blumenstingl
2021-06-27 22:39 ` [PATCH v3 1/3] clk: divider: Add re-usable determine_rate implementations Martin Blumenstingl
2021-06-30 18:39   ` Stephen Boyd
2021-06-27 22:39 ` [PATCH v3 2/3] clk: divider: Switch from .round_rate to .determine_rate by default Martin Blumenstingl
2021-06-30 18:39   ` Stephen Boyd
2021-07-01 20:25   ` Guenter Roeck
2021-07-01 20:57     ` Martin Blumenstingl
2021-07-01 21:43       ` Guenter Roeck
2021-07-02  0:53         ` Stephen Boyd
2021-07-02  1:02       ` Stephen Boyd
2021-07-02  9:19         ` Martin Blumenstingl
     [not found]           ` <CGME20210702124612eucas1p1762911deb37e4fb03adc9239bb715135@eucas1p1.samsung.com>
2021-07-02 12:46             ` Marek Szyprowski
2021-07-02 21:00               ` Stephen Boyd
2021-07-02 20:59           ` Stephen Boyd
2021-07-02 22:57             ` Martin Blumenstingl
2021-07-02  1:04   ` Stephen Boyd
2021-06-27 22:39 ` [PATCH v3 3/3] clk: meson: regmap: switch to determine_rate for the dividers Martin Blumenstingl
2021-06-30 18:39   ` Stephen Boyd [this message]

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