Re: [PATCH v1 01/17] dt-bindings: mediatek: add definition for mt8195 display

From: CK Hu <ck.hu@mediatek.com>
To: jason-jh.lin <jason-jh.lin@mediatek.com>
Cc: <chunkuang.hu@kernel.org>, <matthias.bgg@gmail.com>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-mediatek@lists.infradead.org>,
	 <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<Project_Global_Chrome_Upstream_Group@mediatek.com>,
	<fshao@google.com>, <nancy.lin@mediatek.com>,
	<singo.chang@mediatek.com>
Subject: Re: [PATCH v1 01/17] dt-bindings: mediatek: add definition for mt8195 display
Date: Wed, 7 Jul 2021 12:33:03 +0800	[thread overview]
Message-ID: <1625632383.7824.2.camel@mtksdaap41> (raw)
In-Reply-To: <20210707041249.29816-2-jason-jh.lin@mediatek.com>

Hi, Jason:

On Wed, 2021-07-07 at 12:12 +0800, jason-jh.lin wrote:
> Add definition for mt8195 display and add DSC module description.

Break this patch to two patch. One is mt8195 display, another one is DSC
and describe more about what is DSC.

Regards,
CK

> 
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
>  .../bindings/display/mediatek/mediatek,disp.txt     | 13 +++++++++++--
>  1 file changed, 11 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> index fbb59c9ddda6..a5859e7883d5 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> @@ -37,6 +37,7 @@ Required properties (all function blocks):
>  	"mediatek,<chip>-disp-aal"   		- adaptive ambient light controller
>  	"mediatek,<chip>-disp-gamma" 		- gamma correction
>  	"mediatek,<chip>-disp-merge" 		- merge streams from two RDMA sources
> +	"mediatek,<chip>-disp-dsc"		- compressing / decompressing image display streams
>  	"mediatek,<chip>-disp-postmask" 	- control round corner for display frame
>  	"mediatek,<chip>-disp-split" 		- split stream to two encoders
>  	"mediatek,<chip>-disp-ufoe"  		- data compression engine
> @@ -44,7 +45,7 @@ Required properties (all function blocks):
>  	"mediatek,<chip>-dpi"        		- DPI controller, see mediatek,dpi.txt
>  	"mediatek,<chip>-disp-mutex" 		- display mutex
>  	"mediatek,<chip>-disp-od"    		- overdrive
> -  the supported chips are mt2701, mt7623, mt2712, mt8167, mt8173, mt8183 and mt8192.
> +  the supported chips are mt2701, mt7623, mt2712, mt8167, mt8173, mt8183, mt8192 and mt8195.
>  - reg: Physical base address and length of the function block register space
>  - interrupts: The interrupt signal from the function block (required, except for
>    merge and split function blocks).
> @@ -60,7 +61,7 @@ Required properties (DMA function blocks):
>  	"mediatek,<chip>-disp-ovl"
>  	"mediatek,<chip>-disp-rdma"
>  	"mediatek,<chip>-disp-wdma"
> -  the supported chips are mt2701, mt8167 and mt8173.
> +  the supported chips are mt2701, mt8167, mt8173 and mt8195.
>  - larb: Should contain a phandle pointing to the local arbiter device as defined
>    in Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
>  - iommus: Should point to the respective IOMMU block with master port as
> @@ -195,6 +196,14 @@ ufoe@1401a000 {
>  	clocks = <&mmsys CLK_MM_DISP_UFOE>;
>  };
>  
> +dsc0@1c009000 {
> +	compatible = "mediatek,mt8195-disp-dsc";
> +	reg = <0 0x1c009000 0 0x1000>;
> +	interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH>;
> +	power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> +	clocks = <&mmsys CLK_VDO0_DSC_WRAP0>;
> +};
> +
>  dsi0: dsi@1401b000 {
>  	/* See mediatek,dsi.txt for details */
>  };

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