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* [PATCH v1 00/17] Add MediaTek SoC DRM (vdosys0) support for mt8195
@ 2021-07-07  4:12 jason-jh.lin
  2021-07-07  4:12 ` [PATCH v1 01/17] dt-bindings: mediatek: add definition for mt8195 display jason-jh.lin
                   ` (16 more replies)
  0 siblings, 17 replies; 42+ messages in thread
From: jason-jh.lin @ 2021-07-07  4:12 UTC (permalink / raw)
  To: chunkuang.hu, matthias.bgg
  Cc: linux-arm-kernel, linux-mediatek, linux-kernel, devicetree,
	Project_Global_Chrome_Upstream_Group, fshao, jason-jh.lin,
	nancy.lin, singo.chang

The hardware path of vdosys0 with eDP panel output need to go through
by several modules, such as, OVL, RDMA, COLOR, CCORR, AAL, GAMMA,
DITHER, MERGE and DSC.

Add DRM and these modules support by the patches below:
jason-jh.lin (17):
  dt-bindings: mediatek: add definition for mt8195 display
  dt-bindings: arm: mediatek: add definition for mt8195 mmsys
  arm64: dts: mt8195: add display node for vdosys0
  soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
  drm/mediatek: add mediatek-drm of vdosys0 support for MT8195
  soc: mediatek: add mtk-mutex support for mt8195
  drm/mediatek: add OVL support for MT8195
  drm/mediatek: Add component_del in OVL remove function
  drm/mediatek: add OVL support multi-layer
  drm/mediatek: add RDMA support for MT8195
  drm/mediatek: add COLOR support for MT8195
  drm/mediatek: add CCORR support for MT8195
  drm/mediatek: Add AAL support for MT8195
  drm/mediatek: add GAMMA support for MT8195
  drm/mediatek: add DITHER support for MT8195
  drm/mediatek: add MERGE support for MT8195
  drm/mediatek: add DSC support for MT8195

 .../bindings/arm/mediatek/mediatek,mmsys.txt  |  15 +
 .../display/mediatek/mediatek,disp.txt        |  13 +-
 arch/arm64/boot/dts/mediatek/mt8195.dtsi      | 105 +++
 drivers/clk/mediatek/clk-mt8195-vdo0.c        |  24 +-
 drivers/gpu/drm/mediatek/Makefile             |   5 +-
 drivers/gpu/drm/mediatek/mtk_disp_ccorr.c     |   2 +
 drivers/gpu/drm/mediatek/mtk_disp_color.c     |   6 +
 drivers/gpu/drm/mediatek/mtk_disp_drv.h       |  19 +
 drivers/gpu/drm/mediatek/mtk_disp_dsc.c       | 286 ++++++++
 drivers/gpu/drm/mediatek/mtk_disp_gamma.c     |   2 +
 drivers/gpu/drm/mediatek/mtk_disp_merge.c     | 623 ++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c       |  27 +-
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c      |   6 +
 drivers/gpu/drm/mediatek/mtk_drm_crtc.h       |  32 +
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c   |  37 +-
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h   |   2 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c        |  48 ++
 drivers/gpu/drm/mediatek/mtk_drm_drv.h        |   2 +
 drivers/gpu/drm/mediatek/mtk_panel_ext.c      | 136 ++++
 drivers/gpu/drm/mediatek/mtk_panel_ext.h      | 344 ++++++++++
 drivers/soc/mediatek/mt8195-mmsys.h           | 191 ++++++
 drivers/soc/mediatek/mtk-mmsys.c              |  11 +
 drivers/soc/mediatek/mtk-mutex.c              | 107 ++-
 include/linux/soc/mediatek/mtk-mmsys.h        |   9 +
 24 files changed, 2029 insertions(+), 23 deletions(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_dsc.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_panel_ext.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_panel_ext.h
 create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h

-- 
2.18.0
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 42+ messages in thread

* [PATCH v1 01/17] dt-bindings: mediatek: add definition for mt8195 display
  2021-07-07  4:12 [PATCH v1 00/17] Add MediaTek SoC DRM (vdosys0) support for mt8195 jason-jh.lin
@ 2021-07-07  4:12 ` jason-jh.lin
  2021-07-07  4:33   ` CK Hu
  2021-07-07  4:12 ` [PATCH v1 02/17] dt-bindings: arm: mediatek: add definition for mt8195 mmsys jason-jh.lin
                   ` (15 subsequent siblings)
  16 siblings, 1 reply; 42+ messages in thread
From: jason-jh.lin @ 2021-07-07  4:12 UTC (permalink / raw)
  To: chunkuang.hu, matthias.bgg
  Cc: linux-arm-kernel, linux-mediatek, linux-kernel, devicetree,
	Project_Global_Chrome_Upstream_Group, fshao, jason-jh.lin,
	nancy.lin, singo.chang

Add definition for mt8195 display and add DSC module description.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 .../bindings/display/mediatek/mediatek,disp.txt     | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
index fbb59c9ddda6..a5859e7883d5 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
@@ -37,6 +37,7 @@ Required properties (all function blocks):
 	"mediatek,<chip>-disp-aal"   		- adaptive ambient light controller
 	"mediatek,<chip>-disp-gamma" 		- gamma correction
 	"mediatek,<chip>-disp-merge" 		- merge streams from two RDMA sources
+	"mediatek,<chip>-disp-dsc"		- compressing / decompressing image display streams
 	"mediatek,<chip>-disp-postmask" 	- control round corner for display frame
 	"mediatek,<chip>-disp-split" 		- split stream to two encoders
 	"mediatek,<chip>-disp-ufoe"  		- data compression engine
@@ -44,7 +45,7 @@ Required properties (all function blocks):
 	"mediatek,<chip>-dpi"        		- DPI controller, see mediatek,dpi.txt
 	"mediatek,<chip>-disp-mutex" 		- display mutex
 	"mediatek,<chip>-disp-od"    		- overdrive
-  the supported chips are mt2701, mt7623, mt2712, mt8167, mt8173, mt8183 and mt8192.
+  the supported chips are mt2701, mt7623, mt2712, mt8167, mt8173, mt8183, mt8192 and mt8195.
 - reg: Physical base address and length of the function block register space
 - interrupts: The interrupt signal from the function block (required, except for
   merge and split function blocks).
@@ -60,7 +61,7 @@ Required properties (DMA function blocks):
 	"mediatek,<chip>-disp-ovl"
 	"mediatek,<chip>-disp-rdma"
 	"mediatek,<chip>-disp-wdma"
-  the supported chips are mt2701, mt8167 and mt8173.
+  the supported chips are mt2701, mt8167, mt8173 and mt8195.
 - larb: Should contain a phandle pointing to the local arbiter device as defined
   in Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
 - iommus: Should point to the respective IOMMU block with master port as
@@ -195,6 +196,14 @@ ufoe@1401a000 {
 	clocks = <&mmsys CLK_MM_DISP_UFOE>;
 };
 
+dsc0@1c009000 {
+	compatible = "mediatek,mt8195-disp-dsc";
+	reg = <0 0x1c009000 0 0x1000>;
+	interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH>;
+	power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+	clocks = <&mmsys CLK_VDO0_DSC_WRAP0>;
+};
+
 dsi0: dsi@1401b000 {
 	/* See mediatek,dsi.txt for details */
 };
-- 
2.18.0
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 42+ messages in thread

* [PATCH v1 02/17] dt-bindings: arm: mediatek: add definition for mt8195 mmsys
  2021-07-07  4:12 [PATCH v1 00/17] Add MediaTek SoC DRM (vdosys0) support for mt8195 jason-jh.lin
  2021-07-07  4:12 ` [PATCH v1 01/17] dt-bindings: mediatek: add definition for mt8195 display jason-jh.lin
@ 2021-07-07  4:12 ` jason-jh.lin
  2021-07-07  4:12 ` [PATCH v1 03/17] arm64: dts: mt8195: add display node for vdosys0 jason-jh.lin
                   ` (14 subsequent siblings)
  16 siblings, 0 replies; 42+ messages in thread
From: jason-jh.lin @ 2021-07-07  4:12 UTC (permalink / raw)
  To: chunkuang.hu, matthias.bgg
  Cc: linux-arm-kernel, linux-mediatek, linux-kernel, devicetree,
	Project_Global_Chrome_Upstream_Group, fshao, jason-jh.lin,
	nancy.lin, singo.chang

There are 2 display hardware path in mt8195, namely vdosys0 and vdosys1,
so add their definition in mtk-mmsys documentation.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 .../bindings/arm/mediatek/mediatek,mmsys.txt      | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
index 9712a6831fab..be1761010d3c 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
@@ -17,6 +17,8 @@ Required Properties:
 	- "mediatek,mt8173-mmsys", "syscon"
 	- "mediatek,mt8183-mmsys", "syscon"
 	- "mediatek,mt8192-mmsys", "syscon"
+	- "mediatek,mt8195-vdosys0", "syscon"
+	- "mediatek,mt8195-vdosys1", "syscon"
 - #clock-cells: Must be 1
 
 For the clock control, the mmsys controller uses the common clk binding from
@@ -30,3 +32,16 @@ mmsys: syscon@14000000 {
 	reg = <0 0x14000000 0 0x1000>;
 	#clock-cells = <1>;
 };
+
+vdosys0: syscon@1c01a000 {
+	compatible = "mediatek,mt8195-vdosys0", "syscon";
+	reg = <0 0x1c01a000 0 0x1000>;
+	#clock-cells = <1>;
+};
+
+vdosys1: syscon@1c100000 {
+	compatible = "mediatek,mt8195-vdosys1", "syscon";
+	reg = <0 0x1c100000 0 0x1000>;
+	#clock-cells = <1>;
+};
+
-- 
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 42+ messages in thread

* [PATCH v1 03/17] arm64: dts: mt8195: add display node for vdosys0
  2021-07-07  4:12 [PATCH v1 00/17] Add MediaTek SoC DRM (vdosys0) support for mt8195 jason-jh.lin
  2021-07-07  4:12 ` [PATCH v1 01/17] dt-bindings: mediatek: add definition for mt8195 display jason-jh.lin
  2021-07-07  4:12 ` [PATCH v1 02/17] dt-bindings: arm: mediatek: add definition for mt8195 mmsys jason-jh.lin
@ 2021-07-07  4:12 ` jason-jh.lin
  2021-07-07  4:12 ` [PATCH v1 04/17] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0 jason-jh.lin
                   ` (13 subsequent siblings)
  16 siblings, 0 replies; 42+ messages in thread
From: jason-jh.lin @ 2021-07-07  4:12 UTC (permalink / raw)
  To: chunkuang.hu, matthias.bgg
  Cc: linux-arm-kernel, linux-mediatek, linux-kernel, devicetree,
	Project_Global_Chrome_Upstream_Group, fshao, jason-jh.lin,
	nancy.lin, singo.chang

Add display node for vdosys0.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
This patch is based on [1][2][3]

[1]arm64: dts: Add Mediatek SoC MT8195 and evaluation board dts and Makefile
- https://patchwork.kernel.org/project/linux-mediatek/patch/20210601075350.31515-2-seiya.wang@mediatek.com/
[2]arm64: dts: mt8195: add IOMMU and smi nodes
- https://patchwork.kernel.org/project/linux-mediatek/patch/20210615173233.26682-15-tinghan.shen@mediatek.com/
[3]arm64: dts: mt8195: add gce node
- https://patchwork.kernel.org/project/linux-mediatek/patch/20210705053429.4380-4-jason-jh.lin@mediatek.com/
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 105 +++++++++++++++++++++++
 1 file changed, 105 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 47bb3a63ca9c..d69749b931a3 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1155,9 +1155,114 @@
 			#clock-cells = <1>;
 		};
 
+		ovl0: disp_ovl@1c000000 {
+			compatible = "mediatek,mt8195-disp-ovl";
+			reg = <0 0x1c000000 0 0x1000>;
+			interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
+			iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c00XXXX 0x0000 0x1000>;
+		};
+
+		rdma0: disp_rdma@1c002000 {
+			compatible = "mediatek,mt8195-disp-rdma";
+			reg = <0 0x1c002000 0 0x1000>;
+			interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>;
+			iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c00XXXX 0x2000 0x1000>;
+		};
+
+		color0: disp_color@1c003000 {
+			compatible = "mediatek,mt8195-disp-color";
+			reg = <0 0x1c003000 0 0x1000>;
+			interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c00XXXX 0x3000 0x1000>;
+		};
+
+		ccorr0: disp_ccorr@1c004000 {
+			compatible = "mediatek,mt8195-disp-ccorr";
+			reg = <0 0x1c004000 0 0x1000>;
+			interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>;
+			mediatek,gce-client-reg =
+					 <&gce1 SUBSYS_1c00XXXX 0x4000 0x1000>;
+		};
+
+		aal0: disp_aal@1c005000 {
+			compatible = "mediatek,mt8195-disp-aal";
+			reg = <0 0x1c005000 0 0x1000>;
+			interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c00XXXX 0x5000 0x1000>;
+		};
+
+		gamma0: disp_gamma@1c006000 {
+			compatible = "mediatek,mt8195-disp-gamma";
+			reg = <0 0x1c006000 0 0x1000>;
+			interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c00XXXX 0x6000 0x1000>;
+		};
+
+		dither0: disp_dither@1c007000 {
+			compatible = "mediatek,mt8195-disp-dither";
+			reg = <0 0x1c007000 0 0x1000>;
+			interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c00XXXX 0x7000 0x1000>;
+		};
+
+		dsc0: disp_dsc_wrap@1c009000 {
+			compatible = "mediatek,mt8195-disp-dsc";
+			reg = <0 0x1c009000 0 0x1000>;
+			interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;
+		};
+
+		merge0: disp_vpp_merge0@1c014000 {
+			compatible = "mediatek,mt8195-disp-merge";
+			reg = <0 0x1c014000 0 0x1000>;
+			interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c01XXXX 0x4000 0x1000>;
+		};
+
+		mutex: disp_mutex0@1c016000 {
+			compatible = "mediatek,mt8195-disp-mutex";
+			reg = <0 0x1c016000 0 0x1000>;
+			reg-names = "vdo0_mutex";
+			interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
+			clock-names = "vdo0_mutex";
+			mediatek,gce-events =
+				 <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
+		};
+
 		vdosys0: syscon@1c01a000 {
 			compatible = "mediatek,mt8195-vdosys0", "syscon";
 			reg = <0 0x1c01a000 0 0x1000>;
+			mboxes = <&gce1 0 0 CMDQ_THR_PRIO_4>;
 			#clock-cells = <1>;
 		};
 
-- 
2.18.0
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 42+ messages in thread

* [PATCH v1 04/17] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
  2021-07-07  4:12 [PATCH v1 00/17] Add MediaTek SoC DRM (vdosys0) support for mt8195 jason-jh.lin
                   ` (2 preceding siblings ...)
  2021-07-07  4:12 ` [PATCH v1 03/17] arm64: dts: mt8195: add display node for vdosys0 jason-jh.lin
@ 2021-07-07  4:12 ` jason-jh.lin
  2021-07-07  4:44   ` CK Hu
  2021-07-07  4:12 ` [PATCH v1 05/17] drm/mediatek: add mediatek-drm of vdosys0 support for MT8195 jason-jh.lin
                   ` (12 subsequent siblings)
  16 siblings, 1 reply; 42+ messages in thread
From: jason-jh.lin @ 2021-07-07  4:12 UTC (permalink / raw)
  To: chunkuang.hu, matthias.bgg
  Cc: linux-arm-kernel, linux-mediatek, linux-kernel, devicetree,
	Project_Global_Chrome_Upstream_Group, fshao, jason-jh.lin,
	nancy.lin, singo.chang

1. Add mtk-mmsys support for mt8195 vodsys0.
2. Change the clock driver of vdosys0 is probed
   from the probe of mtk-mmsys.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 drivers/clk/mediatek/clk-mt8195-vdo0.c |  24 ++--
 drivers/soc/mediatek/mt8195-mmsys.h    | 173 +++++++++++++++++++++++++
 drivers/soc/mediatek/mtk-mmsys.c       |  11 ++
 3 files changed, 198 insertions(+), 10 deletions(-)
 create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h

diff --git a/drivers/clk/mediatek/clk-mt8195-vdo0.c b/drivers/clk/mediatek/clk-mt8195-vdo0.c
index 8e23f267a1e6..940be5377f70 100644
--- a/drivers/clk/mediatek/clk-mt8195-vdo0.c
+++ b/drivers/clk/mediatek/clk-mt8195-vdo0.c
@@ -94,20 +94,24 @@ static const struct mtk_clk_desc vdo0_desc = {
 	.num_clks = ARRAY_SIZE(vdo0_clks),
 };
 
-static const struct of_device_id of_match_clk_mt8195_vdo0[] = {
-	{
-		.compatible = "mediatek,mt8195-vdosys0",
-		.data = &vdo0_desc,
-	}, {
-		/* sentinel */
-	}
-};
+static int clk_mt8195_vdo0_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *node = dev->parent->of_node;
+	struct clk_onecell_data *clk_data;
+
+	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(vdo0_clks));
+
+	mtk_clk_register_gates(node, vdo0_clks, ARRAY_SIZE(vdo0_clks),
+			clk_data);
+
+	return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
 
 static struct platform_driver clk_mt8195_vdo0_drv = {
-	.probe = mtk_clk_simple_probe,
+	.probe = clk_mt8195_vdo0_probe,
 	.driver = {
 		.name = "clk-mt8195-vdo0",
-		.of_match_table = of_match_clk_mt8195_vdo0,
 	},
 };
 
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
new file mode 100644
index 000000000000..47f3d0ea3c6c
--- /dev/null
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -0,0 +1,173 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
+#define __SOC_MEDIATEK_MT8195_MMSYS_H
+
+#define MT8195_VDO0_OVL_MOUT_EN					0xf14
+#define MOUT_DISP_OVL0_TO_DISP_RDMA0				BIT(0)
+#define MOUT_DISP_OVL0_TO_DISP_WDMA0				BIT(1)
+#define MOUT_DISP_OVL0_TO_DISP_OVL1				BIT(2)
+#define MOUT_DISP_OVL1_TO_DISP_RDMA1				BIT(4)
+#define MOUT_DISP_OVL1_TO_DISP_WDMA1				BIT(5)
+#define MOUT_DISP_OVL1_TO_DISP_OVL0				BIT(6)
+
+#define MT8195_VDO0_SEL_IN					0xf34
+#define SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT			(0 << 0)
+#define SEL_IN_VPP_MERGE_FROM_DISP_DITHER1			(1 << 0)
+#define SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0			(2 << 0)
+#define SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0			(0 << 4)
+#define SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE			(1 << 4)
+#define SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1			(0 << 5)
+#define SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE			(1 << 5)
+#define SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE			(0 << 8)
+#define SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT			(1 << 8)
+#define SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT			(0 << 9)
+#define SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT			(0 << 12)
+#define SEL_IN_DP_INTF0_FROM_VPP_MERGE				(1 << 12)
+#define SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0			(2 << 12)
+#define SEL_IN_DSI0_FROM_DSC_WRAP0_OUT				(0 << 16)
+#define SEL_IN_DSI0_FROM_DISP_DITHER0				(1 << 16)
+#define SEL_IN_DSI1_FROM_DSC_WRAP1_OUT				(0 << 17)
+#define SEL_IN_DSI1_FROM_VPP_MERGE				(1 << 17)
+#define SEL_IN_DISP_WDMA1_FROM_DISP_OVL1			(0 << 20)
+#define SEL_IN_DISP_WDMA1_FROM_VPP_MERGE			(1 << 20)
+#define SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN			(0 << 21)
+#define SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1			(1 << 21)
+#define SEL_IN_DISP_WDMA0_FROM_DISP_OVL0			(0 << 22)
+#define SEL_IN_DISP_WDMA0_FROM_VPP_MERGE			(1 << 22)
+
+#define MT8195_VDO0_SEL_OUT					0xf38
+#define SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN			(0 << 0)
+#define SOUT_DISP_DITHER0_TO_DSI0				(1 << 0)
+#define SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN			(0 << 1)
+#define SOUT_DISP_DITHER1_TO_VPP_MERGE				(1 << 1)
+#define SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT			(2 << 1)
+#define SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE				(0 << 4)
+#define SOUT_VDO1_VIRTUAL0_TO_DP_INTF0				(1 << 4)
+#define SOUT_VPP_MERGE_TO_DSI1					(0 << 8)
+#define SOUT_VPP_MERGE_TO_DP_INTF0				(1 << 8)
+#define SOUT_VPP_MERGE_TO_SINA_VIRTUAL0				(2 << 8)
+#define SOUT_VPP_MERGE_TO_DISP_WDMA1				(3 << 8)
+#define SOUT_VPP_MERGE_TO_DSC_WRAP0_IN				(4 << 8)
+#define SOUT_VPP_MERGE_TO_DSC_WRAP1_IN				(0 << 11)
+#define SOUT_VPP_MERGE_TO_DISP_WDMA0				(1 << 11)
+#define SOUT_DSC_WRAP0_OUT_TO_DSI0				(0 << 12)
+#define SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0			(1 << 12)
+#define SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE				(2 << 12)
+#define SOUT_DSC_WRAP1_OUT_TO_DSI1				(0 << 16)
+#define SOUT_DSC_WRAP1_OUT_TO_DP_INTF0				(1 << 16)
+#define SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0			(2 << 16)
+#define SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE				(3 << 16)
+
+#define MT8195_VDO1_VPP3_ASYNC_SOUT				0xf54
+#define SOUT_TO_VPP_MERGE0_P0_SEL				(0 << 0)
+#define SOUT_TO_VPP_MERGE0_P1_SEL				(1 << 0)
+
+#define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL			0xf40
+#define SOUT_TO_HDR_VDO_FE0					(0 << 0)
+
+#define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL			0xf44
+#define SOUT_TO_HDR_VDO_FE1					(0 << 0)
+
+#define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL			0xf48
+#define SOUT_TO_HDR_GFX_FE0					(0 << 0)
+
+#define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL			0xf4c
+#define SOUT_TO_HDR_GFX_FE1					(0 << 0)
+
+#define MT8195_VDO1_MIXER_IN1_SOUT_SEL				0xf58
+#define MIXER_IN1_SOUT_TO_DISP_MIXER				(0 << 0)
+
+#define MT8195_VDO1_MIXER_IN2_SOUT_SEL				0xf5c
+#define MIXER_IN2_SOUT_TO_DISP_MIXER				(0 << 0)
+
+#define MT8195_VDO1_MIXER_IN3_SOUT_SEL				0xf60
+#define MIXER_IN3_SOUT_TO_DISP_MIXER				(0 << 0)
+
+#define MT8195_VDO1_MIXER_IN4_SOUT_SEL				0xf64
+#define MIXER_IN4_SOUT_TO_DISP_MIXER				(0 << 0)
+
+#define MT8195_VDO1_MIXER_OUT_SOUT_SEL				0xf34
+#define MIXER_SOUT_TO_HDR_VDO_BE0				(0 << 0)
+
+#define MT8195_VDO1_MERGE4_SOUT_SEL				0xf18
+#define MERGE4_SOUT_TO_VDOSYS0					(0 << 0)
+#define MERGE4_SOUT_TO_DPI0_SEL					(1 << 0)
+#define MERGE4_SOUT_TO_DPI1_SEL					(2 << 0)
+#define MERGE4_SOUT_TO_DP_INTF0_SEL				(3 << 0)
+
+#define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN			0xf04
+#define VPP_MERGE0_P0_SEL_IN_FROM_SVPP2				(0 << 0)
+#define VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0			(1 << 0)
+
+#define MT8195_VDO1_VPP_MERGE0_P1_SEL_IN			0xf08
+#define VPP_MERGE0_P1_SEL_IN_FROM_SVPP3				(0 << 0)
+#define VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1			(1 << 0)
+
+#define MT8195_VDO1_VPP_MERGE1_P0_SEL_IN			0xf3c
+#define VPP_MERGE1_P0_SEL_IN_FROM_VPP3_ASYNC_SOUT		(0 << 0)
+#define VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2			(1 << 0)
+
+#define MT8195_VDO1_MIXER_IN1_SEL_IN				0xf24
+#define MIXER_IN1_SEL_IN_FROM_HDR_VDO_FE0			(0 << 0)
+#define MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT			(1 << 0)
+
+#define MT8195_VDO1_MIXER_IN2_SEL_IN				0xf28
+#define MIXER_IN2_SEL_IN_FROM_HDR_VDO_FE1			(0 << 0)
+#define MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT			(1 << 0)
+
+#define MT8195_VDO1_MIXER_IN3_SEL_IN				0xf2c
+#define MIXER_IN3_SEL_IN_FROM_HDR_GFX_FE0			(0 << 0)
+#define MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT			(1 << 0)
+
+#define MT8195_VDO1_MIXER_IN4_SEL_IN				0xf30
+#define MIXER_IN4_SEL_IN_FROM_HDR_GFX_FE1			(0 << 0)
+#define MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT			(1 << 0)
+
+#define MT8195_VDO1_MIXER_SOUT_SEL_IN				0xf68
+#define MIXER_SOUT_SEL_IN_FROM_DISP_MIXER			(0 << 0)
+#define MIXER_SOUT_SEL_IN_FROM_MIXER_IN1_SOUT			(1 << 0)
+#define MIXER_SOUT_SEL_IN_FROM_MIXER_IN2_SOUT			(2 << 0)
+#define MIXER_SOUT_SEL_IN_FROM_MIXER_IN3_SOUTR			(3 << 0)
+#define MIXER_SOUT_SEL_IN_FROM_MIXER_IN4_SOUTR			(4 << 0)
+
+#define MT8195_VDO1_MERGE4_ASYNC_SEL_IN				0xf50
+#define MERGE4_ASYNC_SEL_IN_FROM_HDR_VDO_BE0			(0 << 0)
+#define MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT			(1 << 0)
+#define MERGE4_ASYNC_SEL_IN_FROM_MERGE0_ASYNC_SOUT		(2 << 0)
+#define MERGE4_ASYNC_SEL_IN_FROM_MERGE1_ASYNC_SOUT		(3 << 0)
+#define MERGE4_ASYNC_SEL_IN_FROM_MERGE2_ASYNC_SOUT		(4 << 0)
+#define MERGE4_ASYNC_SEL_IN_FROM_MERGE3_ASYNC_SOUT		(5 << 0)
+
+#define MT8195_VDO1_DISP_DPI0_SEL_IN				0xf0c
+#define DISP_DPI0_SEL_IN_FROM_VPP_MERGE4_MOUT			(0 << 0)
+#define DISP_DPI0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT		(1 << 0)
+#define DISP_DPI0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT		(2 << 0)
+
+#define MT8195_VDO1_DISP_DPI1_SEL_IN				0xf10
+#define DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT			(0 << 0)
+#define DISP_DPI1_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT		(1 << 0)
+#define DISP_DPI1_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT		(2 << 0)
+
+#define MT8195_VDO1_DISP_DP_INTF0_SEL_IN			0xf14
+#define DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT		(0 << 0)
+#define DISP_DP_INTF0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT	(1 << 0)
+#define DISP_DP_INTF0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT	(2 << 0)
+
+static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
+	{
+		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
+		MT8195_VDO0_OVL_MOUT_EN, MOUT_DISP_OVL0_TO_DISP_RDMA0
+	}, {
+		DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
+		MT8195_VDO0_OVL_MOUT_EN, MOUT_DISP_OVL1_TO_DISP_RDMA1
+	}, {
+		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		MT8195_VDO0_SEL_IN, SEL_IN_DSI0_FROM_DISP_DITHER0
+	}, {
+		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		MT8195_VDO0_SEL_OUT, DDP_COMPONENT_DSI0
+	}
+};
+
+#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 080660ef11bf..1fb241750897 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -13,6 +13,7 @@
 #include "mtk-mmsys.h"
 #include "mt8167-mmsys.h"
 #include "mt8183-mmsys.h"
+#include "mt8195-mmsys.h"
 
 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
 	.clk_driver = "clk-mt2701-mm",
@@ -52,6 +53,12 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
 	.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
 };
 
+static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
+	.clk_driver = "clk-mt8195-vdo0",
+	.routes = mmsys_mt8195_routing_table,
+	.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
+};
+
 struct mtk_mmsys {
 	void __iomem *regs;
 	const struct mtk_mmsys_driver_data *data;
@@ -157,6 +164,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
 		.compatible = "mediatek,mt8183-mmsys",
 		.data = &mt8183_mmsys_driver_data,
 	},
+	{
+		.compatible = "mediatek,mt8195-vdosys0",
+		.data = &mt8195_vdosys0_driver_data,
+	},
 	{ }
 };
 
-- 
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 42+ messages in thread

* [PATCH v1 05/17] drm/mediatek: add mediatek-drm of vdosys0 support for MT8195
  2021-07-07  4:12 [PATCH v1 00/17] Add MediaTek SoC DRM (vdosys0) support for mt8195 jason-jh.lin
                   ` (3 preceding siblings ...)
  2021-07-07  4:12 ` [PATCH v1 04/17] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0 jason-jh.lin
@ 2021-07-07  4:12 ` jason-jh.lin
  2021-07-07  4:48   ` CK Hu
  2021-07-07  4:12 ` [PATCH v1 06/17] soc: mediatek: add mtk-mutex support for mt8195 jason-jh.lin
                   ` (11 subsequent siblings)
  16 siblings, 1 reply; 42+ messages in thread
From: jason-jh.lin @ 2021-07-07  4:12 UTC (permalink / raw)
  To: chunkuang.hu, matthias.bgg
  Cc: linux-arm-kernel, linux-mediatek, linux-kernel, devicetree,
	Project_Global_Chrome_Upstream_Group, fshao, jason-jh.lin,
	nancy.lin, singo.chang

Add mediatek-drm of vdosys0 support for MT8195.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_drv.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index b46bdb8985da..9074ce32912c 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -147,6 +147,23 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = {
 	DDP_COMPONENT_DPI0,
 };
 
+static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
+	DDP_COMPONENT_OVL0,
+	DDP_COMPONENT_RDMA0,
+	DDP_COMPONENT_COLOR0,
+	DDP_COMPONENT_CCORR,
+	DDP_COMPONENT_AAL0,
+	DDP_COMPONENT_GAMMA,
+	DDP_COMPONENT_DITHER,
+#ifdef CONFIG_MTK_DPTX_SUPPORT
+	DDP_COMPONENT_DSC0,
+	DDP_COMPONENT_MERGE0,
+	DDP_COMPONENT_DP_INTF0,
+#else
+	DDP_COMPONENT_DSI0,
+#endif
+};
+
 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
 	.main_path = mt2701_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
@@ -186,6 +203,11 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
 	.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
 };
 
+static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
+	.main_path = mt8195_mtk_ddp_main,
+	.main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
+};
+
 static int mtk_drm_kms_init(struct drm_device *drm)
 {
 	struct mtk_drm_private *private = drm->dev_private;
@@ -468,6 +490,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
 	  .data = &mt8173_mmsys_driver_data},
 	{ .compatible = "mediatek,mt8183-mmsys",
 	  .data = &mt8183_mmsys_driver_data},
+	{.compatible = "mediatek,mt8195-vdosys0",
+	  .data = &mt8195_vdosys0_driver_data},
 	{ }
 };
 MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
-- 
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 42+ messages in thread

* [PATCH v1 06/17] soc: mediatek: add mtk-mutex support for mt8195
  2021-07-07  4:12 [PATCH v1 00/17] Add MediaTek SoC DRM (vdosys0) support for mt8195 jason-jh.lin
                   ` (4 preceding siblings ...)
  2021-07-07  4:12 ` [PATCH v1 05/17] drm/mediatek: add mediatek-drm of vdosys0 support for MT8195 jason-jh.lin
@ 2021-07-07  4:12 ` jason-jh.lin
  2021-07-07  4:52   ` CK Hu
  2021-07-07  4:12 ` [PATCH v1 07/17] drm/mediatek: add OVL support for MT8195 jason-jh.lin
                   ` (10 subsequent siblings)
  16 siblings, 1 reply; 42+ messages in thread
From: jason-jh.lin @ 2021-07-07  4:12 UTC (permalink / raw)
  To: chunkuang.hu, matthias.bgg
  Cc: linux-arm-kernel, linux-mediatek, linux-kernel, devicetree,
	Project_Global_Chrome_Upstream_Group, fshao, jason-jh.lin,
	nancy.lin, singo.chang

Add mtk-mutex support for mt8195.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_drv.c |   2 +
 drivers/soc/mediatek/mtk-mutex.c       | 105 +++++++++++++++++++++++--
 2 files changed, 102 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 9074ce32912c..5b7ead493487 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -470,6 +470,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_MUTEX },
 	{ .compatible = "mediatek,mt8183-disp-mutex",
 	  .data = (void *)MTK_DISP_MUTEX },
+	{ .compatible = "mediatek,mt8195-disp-mutex",
+	  .data = (void *)MTK_DISP_MUTEX },
 	{ .compatible = "mediatek,mt2701-disp-pwm",
 	  .data = (void *)MTK_DISP_BLS },
 	{ .compatible = "mediatek,mt8173-disp-pwm",
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 2e4bcc300576..080bdabfb024 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -17,6 +17,9 @@
 #define MT8183_MUTEX0_MOD0			0x30
 #define MT8183_MUTEX0_SOF0			0x2c
 
+#define MT8195_DISP_MUTEX0_MOD0			0x30
+#define MT8195_DISP_MUTEX0_SOF			0x2c
+
 #define DISP_REG_MUTEX_EN(n)			(0x20 + 0x20 * (n))
 #define DISP_REG_MUTEX(n)			(0x24 + 0x20 * (n))
 #define DISP_REG_MUTEX_RST(n)			(0x28 + 0x20 * (n))
@@ -67,6 +70,36 @@
 #define MT8173_MUTEX_MOD_DISP_PWM1		24
 #define MT8173_MUTEX_MOD_DISP_OD		25
 
+#define MT8195_MUTEX_MOD_DISP_OVL0		0
+#define MT8195_MUTEX_MOD_DISP_WDMA0		1
+#define MT8195_MUTEX_MOD_DISP_RDMA0		2
+#define MT8195_MUTEX_MOD_DISP_COLOR0		3
+#define MT8195_MUTEX_MOD_DISP_CCORR0		4
+#define MT8195_MUTEX_MOD_DISP_AAL0		5
+#define MT8195_MUTEX_MOD_DISP_GAMMA0		6
+#define MT8195_MUTEX_MOD_DISP_DITHER0		7
+#define MT8195_MUTEX_MOD_DISP_DSI0		8
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0	9
+#define MT8195_MUTEX_MOD_DISP_OVL1		10
+#define MT8195_MUTEX_MOD_DISP_WDMA1		11
+#define MT8195_MUTEX_MOD_DISP_RDMA1		12
+#define MT8195_MUTEX_MOD_DISP_COLOR1		13
+#define MT8195_MUTEX_MOD_DISP_CCORR1		14
+#define MT8195_MUTEX_MOD_DISP_AAL1		15
+#define MT8195_MUTEX_MOD_DISP_GAMMA1		16
+#define MT8195_MUTEX_MOD_DISP_DITHER1		17
+#define MT8195_MUTEX_MOD_DISP_DSI1		18
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1	19
+#define MT8195_MUTEX_MOD_DISP_VPP_MERGE		20
+#define MT8195_MUTEX_MOD_DISP_DP_INTF0		21
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0	22
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1	23
+#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2	24
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3	25
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4	26
+#define MT8195_MUTEX_MOD_DISP_PWM0		27
+#define MT8195_MUTEX_MOD_DISP_PWM1		28
+
 #define MT2712_MUTEX_MOD_DISP_PWM2		10
 #define MT2712_MUTEX_MOD_DISP_OVL0		11
 #define MT2712_MUTEX_MOD_DISP_OVL1		12
@@ -101,11 +134,36 @@
 #define MT2712_MUTEX_SOF_DSI3			6
 #define MT8167_MUTEX_SOF_DPI0			2
 #define MT8167_MUTEX_SOF_DPI1			3
+
 #define MT8183_MUTEX_SOF_DSI0			1
 #define MT8183_MUTEX_SOF_DPI0			2
 
-#define MT8183_MUTEX_EOF_DSI0			(MT8183_MUTEX_SOF_DSI0 << 6)
-#define MT8183_MUTEX_EOF_DPI0			(MT8183_MUTEX_SOF_DPI0 << 6)
+#define MT8183_MUTEX_EOF_CONVERT(sof)	((sof) << 6)
+#define MT8183_MUTEX_EOF_DSI0 \
+	MT8183_MUTEX_EOF_CONVERT(MT8183_MUTEX_SOF_DSI0)
+#define MT8183_MUTEX_EOF_DPI0 \
+	MT8183_MUTEX_EOF_CONVERT(MT8183_MUTEX_SOF_DPI0)
+
+#define MT8195_MUTEX_SOF_DSI0			1
+#define MT8195_MUTEX_SOF_DSI1			2
+#define MT8195_MUTEX_SOF_DP_INTF0		3
+#define MT8195_MUTEX_SOF_DP_INTF1		4
+#define MT8195_MUTEX_SOF_DPI0			6 /* for HDMI_TX */
+#define MT8195_MUTEX_SOF_DPI1			5 /* for digital video out */
+
+#define MT8195_MUTEX_EOF_CONVERT(sof)	((sof) << 7)
+#define MT8195_MUTEX_EOF_DSI0 \
+	MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DSI0)
+#define MT8195_MUTEX_EOF_DSI1 \
+	MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DSI1)
+#define MT8195_MUTEX_EOF_DP_INTF0 \
+	MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DP_INTF0)
+#define MT8195_MUTEX_EOF_DP_INTF1 \
+	MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DP_INTF1)
+#define MT8195_MUTEX_EOF_DPI0 \
+	MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DPI0)
+#define MT8195_MUTEX_EOF_DPI1 \
+	MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DPI1)
 
 struct mtk_mutex {
 	int id;
@@ -120,6 +178,9 @@ enum mtk_mutex_sof_id {
 	MUTEX_SOF_DPI1,
 	MUTEX_SOF_DSI2,
 	MUTEX_SOF_DSI3,
+	MUTEX_SOF_DP_INTF0,
+	MUTEX_SOF_DP_INTF1,
+	DDP_MUTEX_SOF_MAX,
 };
 
 struct mtk_mutex_data {
@@ -214,7 +275,20 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
 };
 
-static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+	[DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
+	[DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
+	[DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
+	[DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0,
+	[DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
+	[DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
+	[DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
+	[DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
+	[DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
+	[DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
+};
+
+static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
 	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
 	[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
 	[MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
@@ -224,7 +298,7 @@ static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
 	[MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
 };
 
-static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = {
 	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
 	[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
 	[MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
@@ -232,12 +306,24 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
 };
 
 /* Add EOF setting so overlay hardware can receive frame done irq */
-static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = {
 	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
 	[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
 	[MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
 };
 
+static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
+	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
+	[MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0,
+	[MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1,
+	[MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0,
+	[MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1,
+	[MUTEX_SOF_DP_INTF0] =
+		MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0,
+	[MUTEX_SOF_DP_INTF1] =
+		MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1,
+};
+
 static const struct mtk_mutex_data mt2701_mutex_driver_data = {
 	.mutex_mod = mt2701_mutex_mod,
 	.mutex_sof = mt2712_mutex_sof,
@@ -275,6 +361,13 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = {
 	.no_clk = true,
 };
 
+static const struct mtk_mutex_data mt8195_mutex_driver_data = {
+	.mutex_mod = mt8195_mutex_mod,
+	.mutex_sof = mt8195_mutex_sof,
+	.mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
+	.mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
+};
+
 struct mtk_mutex *mtk_mutex_get(struct device *dev)
 {
 	struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
@@ -507,6 +600,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
 	  .data = &mt8173_mutex_driver_data},
 	{ .compatible = "mediatek,mt8183-disp-mutex",
 	  .data = &mt8183_mutex_driver_data},
+	{ .compatible = "mediatek,mt8195-disp-mutex",
+	  .data = &mt8195_mutex_driver_data},
 	{},
 };
 MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
-- 
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 42+ messages in thread

* [PATCH v1 07/17] drm/mediatek: add OVL support for MT8195
  2021-07-07  4:12 [PATCH v1 00/17] Add MediaTek SoC DRM (vdosys0) support for mt8195 jason-jh.lin
                   ` (5 preceding siblings ...)
  2021-07-07  4:12 ` [PATCH v1 06/17] soc: mediatek: add mtk-mutex support for mt8195 jason-jh.lin
@ 2021-07-07  4:12 ` jason-jh.lin
  2021-07-07  5:03   ` CK Hu
  2021-07-07  4:12 ` [PATCH v1 08/17] drm/mediatek: Add component_del in OVL remove function jason-jh.lin
                   ` (9 subsequent siblings)
  16 siblings, 1 reply; 42+ messages in thread
From: jason-jh.lin @ 2021-07-07  4:12 UTC (permalink / raw)
  To: chunkuang.hu, matthias.bgg
  Cc: linux-arm-kernel, linux-mediatek, linux-kernel, devicetree,
	Project_Global_Chrome_Upstream_Group, fshao, jason-jh.lin,
	nancy.lin, singo.chang

Add OVL support for MT8195.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 9 +++++++++
 drivers/gpu/drm/mediatek/mtk_drm_drv.c  | 2 ++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 961f87f8d4d1..99c39487026d 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -455,6 +455,13 @@ static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = {
 	.fmt_rgb565_is_0 = true,
 };
 
+static const struct mtk_disp_ovl_data mt8195_ovl_driver_data = {
+	.addr = DISP_REG_OVL_ADDR_MT8173,
+	.gmc_bits = 10,
+	.layer_nr = 4,
+	.fmt_rgb565_is_0 = true,
+};
+
 static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
 	{ .compatible = "mediatek,mt2701-disp-ovl",
 	  .data = &mt2701_ovl_driver_data},
@@ -464,6 +471,8 @@ static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
 	  .data = &mt8183_ovl_driver_data},
 	{ .compatible = "mediatek,mt8183-disp-ovl-2l",
 	  .data = &mt8183_ovl_2l_driver_data},
+	{ .compatible = "mediatek,mt8195-disp-ovl",
+	  .data = &mt8195_ovl_driver_data},
 	{},
 };
 MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 5b7ead493487..65038d5b19cb 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -424,6 +424,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_OVL },
 	{ .compatible = "mediatek,mt8183-disp-ovl",
 	  .data = (void *)MTK_DISP_OVL },
+	{ .compatible = "mediatek,mt8195-disp-ovl",
+	  .data = (void *)MTK_DISP_OVL },
 	{ .compatible = "mediatek,mt8183-disp-ovl-2l",
 	  .data = (void *)MTK_DISP_OVL_2L },
 	{ .compatible = "mediatek,mt2701-disp-rdma",
-- 
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 42+ messages in thread

* [PATCH v1 08/17] drm/mediatek: Add component_del in OVL remove function
  2021-07-07  4:12 [PATCH v1 00/17] Add MediaTek SoC DRM (vdosys0) support for mt8195 jason-jh.lin
                   ` (6 preceding siblings ...)
  2021-07-07  4:12 ` [PATCH v1 07/17] drm/mediatek: add OVL support for MT8195 jason-jh.lin
@ 2021-07-07  4:12 ` jason-jh.lin
  2021-07-07  5:12   ` CK Hu
  2021-07-07  4:12 ` [PATCH v1 09/17] drm/mediatek: add OVL support multi-layer jason-jh.lin
                   ` (8 subsequent siblings)
  16 siblings, 1 reply; 42+ messages in thread
From: jason-jh.lin @ 2021-07-07  4:12 UTC (permalink / raw)
  To: chunkuang.hu, matthias.bgg
  Cc: linux-arm-kernel, linux-mediatek, linux-kernel, devicetree,
	Project_Global_Chrome_Upstream_Group, fshao, jason-jh.lin,
	nancy.lin, singo.chang

Add component_del in OVL remove function.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 99c39487026d..7504e86b167a 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -158,7 +158,6 @@ void mtk_ovl_stop(struct device *dev)
 		reg = reg & ~OVL_LAYER_SMI_ID_EN;
 		writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
 	}
-
 }
 
 void mtk_ovl_config(struct device *dev, unsigned int w,
@@ -424,6 +423,8 @@ static int mtk_disp_ovl_probe(struct platform_device *pdev)
 
 static int mtk_disp_ovl_remove(struct platform_device *pdev)
 {
+	component_del(&pdev->dev, &mtk_disp_ovl_component_ops);
+
 	return 0;
 }
 
-- 
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 42+ messages in thread

* [PATCH v1 09/17] drm/mediatek: add OVL support multi-layer
  2021-07-07  4:12 [PATCH v1 00/17] Add MediaTek SoC DRM (vdosys0) support for mt8195 jason-jh.lin
                   ` (7 preceding siblings ...)
  2021-07-07  4:12 ` [PATCH v1 08/17] drm/mediatek: Add component_del in OVL remove function jason-jh.lin
@ 2021-07-07  4:12 ` jason-jh.lin
  2021-07-07  5:43   ` CK Hu
  2021-07-07  4:12 ` [PATCH v1 10/17] drm/mediatek: add RDMA support for MT8195 jason-jh.lin
                   ` (7 subsequent siblings)
  16 siblings, 1 reply; 42+ messages in thread
From: jason-jh.lin @ 2021-07-07  4:12 UTC (permalink / raw)
  To: chunkuang.hu, matthias.bgg
  Cc: linux-arm-kernel, linux-mediatek, linux-kernel, devicetree,
	Project_Global_Chrome_Upstream_Group, fshao, jason-jh.lin,
	nancy.lin, singo.chang

Add datapath_con settings to support multi-layer output.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 7504e86b167a..95fd5e00eb91 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -18,14 +18,17 @@
 #include "mtk_drm_ddp_comp.h"
 
 #define DISP_REG_OVL_INTEN			0x0004
-#define OVL_FME_CPL_INT					BIT(1)
+#define OVL_FME_CPL_INT				BIT(1)
 #define DISP_REG_OVL_INTSTA			0x0008
 #define DISP_REG_OVL_EN				0x000c
 #define DISP_REG_OVL_RST			0x0014
 #define DISP_REG_OVL_ROI_SIZE			0x0020
 #define DISP_REG_OVL_DATAPATH_CON		0x0024
-#define OVL_LAYER_SMI_ID_EN				BIT(0)
-#define OVL_BGCLR_SEL_IN				BIT(2)
+#define OVL_LAYER_SMI_ID_EN			BIT(0)
+#define OVL_BGCLR_SEL_IN			BIT(2)
+#define OVL_GCLAST_EN				BIT(24)
+#define OVL_HDR_GCLAST_EN			BIT(25)
+#define OVL_OUTPUT_CLAMP			BIT(26)
 #define DISP_REG_OVL_ROI_BGCLR			0x0028
 #define DISP_REG_OVL_SRC_CON			0x002c
 #define DISP_REG_OVL_CON(n)			(0x0030 + 0x20 * (n))
@@ -222,6 +225,7 @@ void mtk_ovl_layer_on(struct device *dev, unsigned int idx,
 	unsigned int gmc_thrshd_l;
 	unsigned int gmc_thrshd_h;
 	unsigned int gmc_value;
+	unsigned int datapatch_con;
 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
 
 	mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs,
@@ -237,6 +241,11 @@ void mtk_ovl_layer_on(struct device *dev, unsigned int idx,
 			    gmc_thrshd_h << 16 | gmc_thrshd_h << 24;
 	mtk_ddp_write(cmdq_pkt, gmc_value,
 		      &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RDMA_GMC(idx));
+
+	datapatch_con = OVL_GCLAST_EN | OVL_HDR_GCLAST_EN | OVL_OUTPUT_CLAMP;
+	mtk_ddp_write_mask(cmdq_pkt, datapatch_con, &ovl->cmdq_reg, ovl->regs,
+				 DISP_REG_OVL_DATAPATH_CON, datapatch_con);
+
 	mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &ovl->cmdq_reg, ovl->regs,
 			   DISP_REG_OVL_SRC_CON, BIT(idx));
 }
-- 
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 42+ messages in thread

* [PATCH v1 10/17] drm/mediatek: add RDMA support for MT8195
  2021-07-07  4:12 [PATCH v1 00/17] Add MediaTek SoC DRM (vdosys0) support for mt8195 jason-jh.lin
                   ` (8 preceding siblings ...)
  2021-07-07  4:12 ` [PATCH v1 09/17] drm/mediatek: add OVL support multi-layer jason-jh.lin
@ 2021-07-07  4:12 ` jason-jh.lin
  2021-07-07  4:12 ` [PATCH v1 11/17] drm/mediatek: add COLOR " jason-jh.lin
                   ` (6 subsequent siblings)
  16 siblings, 0 replies; 42+ messages in thread
From: jason-jh.lin @ 2021-07-07  4:12 UTC (permalink / raw)
  To: chunkuang.hu, matthias.bgg
  Cc: linux-arm-kernel, linux-mediatek, linux-kernel, devicetree,
	Project_Global_Chrome_Upstream_Group, fshao, jason-jh.lin,
	nancy.lin, singo.chang

Add RDMA support for MT8195.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++++
 drivers/gpu/drm/mediatek/mtk_drm_drv.c   | 2 ++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 728aaadfea8c..00e9827acefe 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -355,6 +355,10 @@ static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = {
 	.fifo_size = 5 * SZ_1K,
 };
 
+static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = {
+	.fifo_size = 1920,
+};
+
 static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
 	{ .compatible = "mediatek,mt2701-disp-rdma",
 	  .data = &mt2701_rdma_driver_data},
@@ -362,6 +366,8 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
 	  .data = &mt8173_rdma_driver_data},
 	{ .compatible = "mediatek,mt8183-disp-rdma",
 	  .data = &mt8183_rdma_driver_data},
+	{ .compatible = "mediatek,mt8195-disp-rdma",
+	  .data = &mt8195_rdma_driver_data},
 	{},
 };
 MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 65038d5b19cb..8b24623dcd91 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -434,6 +434,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_RDMA },
 	{ .compatible = "mediatek,mt8183-disp-rdma",
 	  .data = (void *)MTK_DISP_RDMA },
+	{ .compatible = "mediatek,mt8195-disp-rdma",
+	  .data = (void *)MTK_DISP_RDMA },
 	{ .compatible = "mediatek,mt8173-disp-wdma",
 	  .data = (void *)MTK_DISP_WDMA },
 	{ .compatible = "mediatek,mt8183-disp-ccorr",
-- 
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 42+ messages in thread

* [PATCH v1 11/17] drm/mediatek: add COLOR support for MT8195
  2021-07-07  4:12 [PATCH v1 00/17] Add MediaTek SoC DRM (vdosys0) support for mt8195 jason-jh.lin
                   ` (9 preceding siblings ...)
  2021-07-07  4:12 ` [PATCH v1 10/17] drm/mediatek: add RDMA support for MT8195 jason-jh.lin
@ 2021-07-07  4:12 ` jason-jh.lin
  2021-07-07  6:01   ` CK Hu
  2021-07-07  4:12 ` [PATCH v1 12/17] drm/mediatek: add CCORR " jason-jh.lin
                   ` (5 subsequent siblings)
  16 siblings, 1 reply; 42+ messages in thread
From: jason-jh.lin @ 2021-07-07  4:12 UTC (permalink / raw)
  To: chunkuang.hu, matthias.bgg
  Cc: linux-arm-kernel, linux-mediatek, linux-kernel, devicetree,
	Project_Global_Chrome_Upstream_Group, fshao, jason-jh.lin,
	nancy.lin, singo.chang

Add COLOR support for MT8195.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_disp_color.c | 6 ++++++
 drivers/gpu/drm/mediatek/mtk_drm_drv.c    | 2 ++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_color.c b/drivers/gpu/drm/mediatek/mtk_disp_color.c
index 63f411ab393b..ce2cf9f504cc 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_color.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_color.c
@@ -149,6 +149,10 @@ static const struct mtk_disp_color_data mt8173_color_driver_data = {
 	.color_offset = DISP_COLOR_START_MT8173,
 };
 
+static const struct mtk_disp_color_data mt8195_color_driver_data = {
+	.color_offset = DISP_COLOR_START_MT8173,
+};
+
 static const struct of_device_id mtk_disp_color_driver_dt_match[] = {
 	{ .compatible = "mediatek,mt2701-disp-color",
 	  .data = &mt2701_color_driver_data},
@@ -156,6 +160,8 @@ static const struct of_device_id mtk_disp_color_driver_dt_match[] = {
 	  .data = &mt8167_color_driver_data},
 	{ .compatible = "mediatek,mt8173-disp-color",
 	  .data = &mt8173_color_driver_data},
+	{ .compatible = "mediatek,mt8195-disp-color",
+	  .data = &mt8195_color_driver_data},
 	{},
 };
 MODULE_DEVICE_TABLE(of, mtk_disp_color_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 8b24623dcd91..28bf4a11efb0 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -444,6 +444,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_COLOR },
 	{ .compatible = "mediatek,mt8173-disp-color",
 	  .data = (void *)MTK_DISP_COLOR },
+	{ .compatible = "mediatek,mt8195-disp-color",
+	  .data = (void *)MTK_DISP_COLOR },
 	{ .compatible = "mediatek,mt8173-disp-aal",
 	  .data = (void *)MTK_DISP_AAL},
 	{ .compatible = "mediatek,mt8173-disp-gamma",
-- 
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 42+ messages in thread

* [PATCH v1 12/17] drm/mediatek: add CCORR support for MT8195
  2021-07-07  4:12 [PATCH v1 00/17] Add MediaTek SoC DRM (vdosys0) support for mt8195 jason-jh.lin
                   ` (10 preceding siblings ...)
  2021-07-07  4:12 ` [PATCH v1 11/17] drm/mediatek: add COLOR " jason-jh.lin
@ 2021-07-07  4:12 ` jason-jh.lin
  2021-07-07  6:02   ` CK Hu
  2021-07-07  4:12 ` [PATCH v1 13/17] drm/mediatek: Add AAL " jason-jh.lin
                   ` (4 subsequent siblings)
  16 siblings, 1 reply; 42+ messages in thread
From: jason-jh.lin @ 2021-07-07  4:12 UTC (permalink / raw)
  To: chunkuang.hu, matthias.bgg
  Cc: linux-arm-kernel, linux-mediatek, linux-kernel, devicetree,
	Project_Global_Chrome_Upstream_Group, fshao, jason-jh.lin,
	nancy.lin, singo.chang

Add CCORR support for MT8195.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 2 ++
 drivers/gpu/drm/mediatek/mtk_drm_drv.c    | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
index 141cb36b9c07..8188b220cc6d 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
@@ -208,6 +208,8 @@ static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = {
 static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = {
 	{ .compatible = "mediatek,mt8183-disp-ccorr",
 	  .data = &mt8183_ccorr_driver_data},
+	{ .compatible = "mediatek,mt8195-disp-ccorr",
+	  .data = &mt8183_ccorr_driver_data},
 	{},
 };
 MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 28bf4a11efb0..058b50d0e64b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -440,6 +440,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_WDMA },
 	{ .compatible = "mediatek,mt8183-disp-ccorr",
 	  .data = (void *)MTK_DISP_CCORR },
+	{ .compatible = "mediatek,mt8195-disp-ccorr",
+	  .data = (void *)MTK_DISP_CCORR },
 	{ .compatible = "mediatek,mt2701-disp-color",
 	  .data = (void *)MTK_DISP_COLOR },
 	{ .compatible = "mediatek,mt8173-disp-color",
-- 
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 42+ messages in thread

* [PATCH v1 13/17] drm/mediatek: Add AAL support for MT8195
  2021-07-07  4:12 [PATCH v1 00/17] Add MediaTek SoC DRM (vdosys0) support for mt8195 jason-jh.lin
                   ` (11 preceding siblings ...)
  2021-07-07  4:12 ` [PATCH v1 12/17] drm/mediatek: add CCORR " jason-jh.lin
@ 2021-07-07  4:12 ` jason-jh.lin
  2021-07-07  6:14   ` CK Hu
  2021-07-07  4:12 ` [PATCH v1 14/17] drm/mediatek: add GAMMA " jason-jh.lin
                   ` (3 subsequent siblings)
  16 siblings, 1 reply; 42+ messages in thread
From: jason-jh.lin @ 2021-07-07  4:12 UTC (permalink / raw)
  To: chunkuang.hu, matthias.bgg
  Cc: linux-arm-kernel, linux-mediatek, linux-kernel, devicetree,
	Project_Global_Chrome_Upstream_Group, fshao, jason-jh.lin,
	nancy.lin, singo.chang

1. Add AAL support for MT8195.
2. Add AAL_OUTPUT_SIZE configuration.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 8 +++++++-
 drivers/gpu/drm/mediatek/mtk_drm_drv.c      | 2 ++
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 75bc00e17fc4..f154f7c0cd11 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -34,6 +34,7 @@
 
 #define DISP_AAL_EN				0x0000
 #define DISP_AAL_SIZE				0x0030
+#define DISP_AAL_OUTPUT_SIZE			0x04d8
 
 #define DISP_DITHER_EN				0x0000
 #define DITHER_EN				BIT(0)
@@ -196,7 +197,12 @@ static void mtk_aal_config(struct device *dev, unsigned int w,
 {
 	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 
-	mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_AAL_SIZE);
+	mtk_ddp_write(cmdq_pkt, w << 16 | h,
+				&priv->cmdq_reg, priv->regs,
+				DISP_AAL_SIZE);
+	mtk_ddp_write(cmdq_pkt, w << 16 | h,
+				&priv->cmdq_reg, priv->regs,
+				DISP_AAL_OUTPUT_SIZE);
 }
 
 static void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 058b50d0e64b..459bb1e53f2e 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -450,6 +450,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_COLOR },
 	{ .compatible = "mediatek,mt8173-disp-aal",
 	  .data = (void *)MTK_DISP_AAL},
+	{ .compatible = "mediatek,mt8195-disp-aal",
+	  .data = (void *)MTK_DISP_AAL},
 	{ .compatible = "mediatek,mt8173-disp-gamma",
 	  .data = (void *)MTK_DISP_GAMMA, },
 	{ .compatible = "mediatek,mt8183-disp-gamma",
-- 
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 42+ messages in thread

* [PATCH v1 14/17] drm/mediatek: add GAMMA support for MT8195
  2021-07-07  4:12 [PATCH v1 00/17] Add MediaTek SoC DRM (vdosys0) support for mt8195 jason-jh.lin
                   ` (12 preceding siblings ...)
  2021-07-07  4:12 ` [PATCH v1 13/17] drm/mediatek: Add AAL " jason-jh.lin
@ 2021-07-07  4:12 ` jason-jh.lin
  2021-07-07  4:12 ` [PATCH v1 15/17] drm/mediatek: add DITHER " jason-jh.lin
                   ` (2 subsequent siblings)
  16 siblings, 0 replies; 42+ messages in thread
From: jason-jh.lin @ 2021-07-07  4:12 UTC (permalink / raw)
  To: chunkuang.hu, matthias.bgg
  Cc: linux-arm-kernel, linux-mediatek, linux-kernel, devicetree,
	Project_Global_Chrome_Upstream_Group, fshao, jason-jh.lin,
	nancy.lin, singo.chang

Add GAMMA support for MT8195.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 2 ++
 drivers/gpu/drm/mediatek/mtk_drm_drv.c    | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
index 3ebf91e0ab41..812b70b32b0c 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
@@ -182,6 +182,8 @@ static const struct of_device_id mtk_disp_gamma_driver_dt_match[] = {
 	{ .compatible = "mediatek,mt8173-disp-gamma",
 	  .data = &mt8173_gamma_driver_data},
 	{ .compatible = "mediatek,mt8183-disp-gamma"},
+	{ .compatible = "mediatek,mt8195-disp-gamma",
+	  .data = &mt8173_gamma_driver_data},
 	{},
 };
 MODULE_DEVICE_TABLE(of, mtk_disp_gamma_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 459bb1e53f2e..ac89e7fefb96 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -456,6 +456,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_GAMMA, },
 	{ .compatible = "mediatek,mt8183-disp-gamma",
 	  .data = (void *)MTK_DISP_GAMMA, },
+	{ .compatible = "mediatek,mt8195-disp-gamma",
+	  .data = (void *)MTK_DISP_GAMMA, },
 	{ .compatible = "mediatek,mt8183-disp-dither",
 	  .data = (void *)MTK_DISP_DITHER },
 	{ .compatible = "mediatek,mt8173-disp-ufoe",
-- 
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 42+ messages in thread

* [PATCH v1 15/17] drm/mediatek: add DITHER support for MT8195
  2021-07-07  4:12 [PATCH v1 00/17] Add MediaTek SoC DRM (vdosys0) support for mt8195 jason-jh.lin
                   ` (13 preceding siblings ...)
  2021-07-07  4:12 ` [PATCH v1 14/17] drm/mediatek: add GAMMA " jason-jh.lin
@ 2021-07-07  4:12 ` jason-jh.lin
  2021-07-07  4:12 ` [PATCH v1 16/17] drm/mediatek: add MERGE " jason-jh.lin
  2021-07-07  4:12 ` [PATCH v1 17/17] drm/mediatek: add DSC " jason-jh.lin
  16 siblings, 0 replies; 42+ messages in thread
From: jason-jh.lin @ 2021-07-07  4:12 UTC (permalink / raw)
  To: chunkuang.hu, matthias.bgg
  Cc: linux-arm-kernel, linux-mediatek, linux-kernel, devicetree,
	Project_Global_Chrome_Upstream_Group, fshao, jason-jh.lin,
	nancy.lin, singo.chang

Add DITHER support for MT8195.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index ac89e7fefb96..635cebf9ff0f 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -460,6 +460,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_GAMMA, },
 	{ .compatible = "mediatek,mt8183-disp-dither",
 	  .data = (void *)MTK_DISP_DITHER },
+	{ .compatible = "mediatek,mt8195-disp-dither",
+	  .data = (void *)MTK_DISP_DITHER },
 	{ .compatible = "mediatek,mt8173-disp-ufoe",
 	  .data = (void *)MTK_DISP_UFOE },
 	{ .compatible = "mediatek,mt2701-dsi",
-- 
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 42+ messages in thread

* [PATCH v1 16/17] drm/mediatek: add MERGE support for MT8195
  2021-07-07  4:12 [PATCH v1 00/17] Add MediaTek SoC DRM (vdosys0) support for mt8195 jason-jh.lin
                   ` (14 preceding siblings ...)
  2021-07-07  4:12 ` [PATCH v1 15/17] drm/mediatek: add DITHER " jason-jh.lin
@ 2021-07-07  4:12 ` jason-jh.lin
  2021-07-07  7:02   ` CK Hu
  2021-07-07  4:12 ` [PATCH v1 17/17] drm/mediatek: add DSC " jason-jh.lin
  16 siblings, 1 reply; 42+ messages in thread
From: jason-jh.lin @ 2021-07-07  4:12 UTC (permalink / raw)
  To: chunkuang.hu, matthias.bgg
  Cc: linux-arm-kernel, linux-mediatek, linux-kernel, devicetree,
	Project_Global_Chrome_Upstream_Group, fshao, jason-jh.lin,
	nancy.lin, singo.chang

1. Add MERGE module file.
2. Add REG_FLD macro in mtk_dem_crtc header to support
   bitwise register settings.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 drivers/gpu/drm/mediatek/Makefile           |   1 +
 drivers/gpu/drm/mediatek/mtk_disp_drv.h     |  11 +
 drivers/gpu/drm/mediatek/mtk_disp_merge.c   | 623 ++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_drm_crtc.h     |  31 +
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |  16 +
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |   1 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c      |   4 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.h      |   1 +
 drivers/soc/mediatek/mtk-mutex.c            |   1 +
 include/linux/soc/mediatek/mtk-mmsys.h      |   6 +
 10 files changed, 695 insertions(+)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c

diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index dc54a7a69005..5fd95b9d5aae 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -5,6 +5,7 @@ mediatek-drm-y := mtk_disp_ccorr.o \
 		  mtk_disp_gamma.o \
 		  mtk_disp_ovl.o \
 		  mtk_disp_rdma.o \
+		  mtk_disp_merge.o \
 		  mtk_drm_crtc.o \
 		  mtk_drm_ddp_comp.o \
 		  mtk_drm_drv.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index cafd9df2d63b..7fd5260e2a72 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -89,4 +89,15 @@ void mtk_rdma_enable_vblank(struct device *dev,
 			    void *vblank_cb_data);
 void mtk_rdma_disable_vblank(struct device *dev);
 
+int mtk_merge_clk_enable(struct device *dev);
+void mtk_merge_clk_disable(struct device *dev);
+void mtk_merge_enable_vblank(struct device *dev,
+		    void (*vblank_cb)(void *), void *vblank_cb_data);
+void mtk_merge_disable_vblank(struct device *dev);
+void mtk_merge_config(struct device *dev, unsigned int width,
+		     unsigned int height, unsigned int vrefresh,
+		     unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_merge_start(struct device *dev);
+void mtk_merge_stop(struct device *dev);
+
 #endif
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
new file mode 100644
index 000000000000..4867fe3fb93f
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
@@ -0,0 +1,623 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_drm_drv.h"
+#include "mtk_disp_drv.h"
+
+#define DISP_REG_MERGE_CTRL (0x000)
+#define FLD_MERGE_EN REG_FLD_MSB_LSB(0, 0)
+#define FLD_MERGE_RST REG_FLD_MSB_LSB(4, 4)
+#define FLD_MERGE_LR_SWAP REG_FLD_MSB_LSB(8, 8)
+#define FLD_MERGE_DCM_DIS REG_FLD_MSB_LSB(12, 12)
+
+#define DISP_REG_MERGE_WIDTH (0x004)
+#define FLD_IN_WIDHT_L REG_FLD_MSB_LSB(15, 0)
+#define FLD_IN_WIDHT_R REG_FLD_MSB_LSB(31, 16)
+
+#define DISP_REG_MERGE_HEIGHT (0x008)
+#define FLD_IN_HEIGHT REG_FLD_MSB_LSB(15, 0)
+
+#define DISP_REG_MERGE_SHADOW_CRTL (0x00c)
+
+#define DISP_REG_MERGE_DGB0 (0x010)
+#define FLD_PIXEL_CNT REG_FLD_MSB_LSB(15, 0)
+#define FLD_MERGE_STATE REG_FLD_MSB_LSB(17, 16)
+
+#define DISP_REG_MERGE_DGB1 (0x014)
+#define FLD_LINE_CNT REG_FLD_MSB_LSB(15, 0)
+
+#define DISP_REG_MERGE_CFG2_0 (0x160)
+
+#define DISP_REG_MERGE_CFG2_2 (0x168)
+
+#define MT8195_DISP_MERGE_RESET		0x004
+#define MT8195_DISP_MERGE_CFG_0		0x010
+#define MT8195_DISP_MERGE_CFG_1		0x014
+#define MT8195_DISP_MERGE_CFG_4		0x020
+#define MT8195_DISP_MERGE_CFG_5		0x024
+#define MT8195_DISP_MERGE_CFG_8		0x030
+#define MT8195_DISP_MERGE_CFG_9		0x034
+#define MT8195_DISP_MERGE_CFG_10	0x038
+#define MT8195_DISP_MERGE_CFG_11	0x03c
+#define MT8195_DISP_MERGE_CFG_12	0x040
+#define CFG_11_11_1PI_1PO_BYPASS	1
+#define CFG_11_11_2PI_2PO_BYPASS	2
+#define CFG_10_10_2PI_1PO_BYPASS	3
+#define CFG_10_10_2PI_2PO_BYPASS	4
+#define CFG_10_10_1PI_1PO_BUF_MODE	5
+#define CFG_10_10_1PI_2PO_BUF_MODE	6
+#define CFG_10_10_2PI_1PO_BUF_MODE	7
+#define CFG_10_10_2PI_2PO_BUF_MODE	8
+#define CFG_10_01_1PI_1PO_BUF_MODE	9
+#define CFG_10_01_2PI_1PO_BUF_MODE	10
+#define CFG_01_10_1PI_1PO_BUF_MODE	11
+#define CFG_01_10_1PI_2PO_BUF_MODE	12
+#define CFG_01_01_1PI_1PO_BUF_MODE	13
+#define CFG_10_11_1PI_1PO_SPLIT		14
+#define CFG_10_11_2PI_1PO_SPLIT		15
+#define CFG_01_11_1PI_1PO_SPLIT		16
+#define CFG_11_10_1PI_1PO_MERGE		17
+#define CFG_11_10_1PI_2PO_MERGE		18
+#define CFG_10_10_1PI_1PO_TO422		19
+#define CFG_10_10_1PI_2PO_TO444		20
+#define CFG_10_10_2PI_2PO_TO444		21
+#define MT8195_DISP_MERGE_CFG_13	0x044
+#define MT8195_DISP_MERGE_CFG_14	0x048
+#define MT8195_DISP_MERGE_CFG_15	0x04c
+#define MT8195_DISP_MERGE_CFG_17	0x054
+#define MT8195_DISP_MERGE_CFG_18	0x058
+#define MT8195_DISP_MERGE_CFG_19	0x05c
+#define MT8195_DISP_MERGE_CFG_20	0x060
+#define MT8195_DISP_MERGE_CFG_21	0x064
+#define MT8195_DISP_MERGE_CFG_22	0x068
+#define MT8195_DISP_MERGE_CFG_23	0x06c
+#define MT8195_DISP_MERGE_CFG_24	0x070
+#define MT8195_DISP_MERGE_CFG_25	0x074
+#define MT8195_DISP_MERGE_CFG_26	0x078
+#define MT8195_DISP_MERGE_CFG_27	0x07c
+#define MT8195_DISP_MERGE_CFG_28	0x080
+#define MT8195_DISP_MERGE_CFG_29	0x084
+#define MT8195_DISP_MERGE_CFG_36	0x0a0
+#define MT8195_DISP_MERGE_CFG_36_FLD_ULTRA_EN \
+	REG_FLD(1, 0)
+#define MT8195_DISP_MERGE_CFG_36_FLD_PREULTRA_EN \
+	REG_FLD(1, 4)
+#define MT8195_DISP_MERGE_CFG_36_FLD_HALT_FOR_DVFS_EN \
+	REG_FLD(1, 8)
+#define MT8195_DISP_MERGE_CFG_36_VAL_ULTRA_EN(val) \
+	REG_FLD_VAL(MT8195_DISP_MERGE_CFG_36_FLD_ULTRA_EN, val)
+#define MT8195_DISP_MERGE_CFG_36_VAL_PREULTRA_EN(val) \
+	REG_FLD_VAL(MT8195_DISP_MERGE_CFG_36_FLD_PREULTRA_EN, val)
+#define MT8195_DISP_MERGE_CFG_36_VAL_HALT_FOR_DVFS_EN(val) \
+	REG_FLD_VAL(MT8195_DISP_MERGE_CFG_36_FLD_HALT_FOR_DVFS_EN, val)
+#define MT8195_DISP_MERGE_CFG_37	0x0a4
+#define MT8195_DISP_MERGE_CFG_37_FLD_BUFFER_MODE \
+	REG_FLD(2, 0)
+#define MT8195_DISP_MERGE_CFG_37_VAL_BUFFER_MODE(val) \
+	REG_FLD_VAL(MT8195_DISP_MERGE_CFG_37_FLD_BUFFER_MODE, val)
+#define MT8195_DISP_MERGE_CFG_38	0x0a8
+#define MT8195_DISP_MERGE_CFG_38_FLD_VDE_BLOCK_ULTRA \
+	REG_FLD(1, 0)
+#define MT8195_DISP_MERGE_CFG_38_FLD_VALID_TH_BLOCK_ULTRA \
+	REG_FLD(1, 4)
+#define MT8195_DISP_MERGE_CFG_38_FLD_ULTRA_FIFO_VALID_TH \
+	REG_FLD(16, 16)
+#define MT8195_DISP_MERGE_CFG_38_VAL_VDE_BLOCK_ULTRA(val) \
+	REG_FLD_VAL(MT8195_DISP_MERGE_CFG_38_FLD_VDE_BLOCK_ULTRA, val)
+#define MT8195_DISP_MERGE_CFG_38_VAL_VALID_TH_BLOCK_ULTRA(val) \
+	REG_FLD_VAL(MT8195_DISP_MERGE_CFG_38_FLD_VALID_TH_BLOCK_ULTRA, val)
+#define MT8195_DISP_MERGE_CFG_38_VAL_ULTRA_FIFO_VALID_TH(val) \
+	REG_FLD_VAL(MT8195_DISP_MERGE_CFG_38_FLD_ULTRA_FIFO_VALID_TH, val)
+#define MT8195_DISP_MERGE_CFG_39	0x0ac
+#define MT8195_DISP_MERGE_CFG_39_FLD_NVDE_FORCE_PREULTRA \
+	REG_FLD(1, 8)
+#define MT8195_DISP_MERGE_CFG_39_FLD_NVALID_TH_FORCE_PREULTRA \
+	REG_FLD(1, 12)
+#define MT8195_DISP_MERGE_CFG_39_FLD_PREULTRA_FIFO_VALID_TH \
+	REG_FLD(16, 16)
+#define MT8195_DISP_MERGE_CFG_39_VAL_NVDE_FORCE_PREULTRA(val) \
+	REG_FLD_VAL(MT8195_DISP_MERGE_CFG_39_FLD_NVDE_FORCE_PREULTRA, val)
+#define MT8195_DISP_MERGE_CFG_39_VAL_NVALID_TH_FORCE_PREULTRA(val) \
+	REG_FLD_VAL(MT8195_DISP_MERGE_CFG_39_FLD_NVALID_TH_FORCE_PREULTRA, val)
+#define MT8195_DISP_MERGE_CFG_39_VAL_PREULTRA_FIFO_VALID_TH(val) \
+	REG_FLD_VAL(MT8195_DISP_MERGE_CFG_39_FLD_PREULTRA_FIFO_VALID_TH, val)
+#define MT8195_DISP_MERGE_CFG_40	0x0b0
+#define MT8195_DISP_MERGE_CFG_40_FLD_ULTRA_TH_LOW \
+	REG_FLD(16, 0)
+#define MT8195_DISP_MERGE_CFG_40_FLD_ULTRA_TH_HIGH \
+	REG_FLD(16, 16)
+#define MT8195_DISP_MERGE_CFG_40_VAL_ULTRA_TH_LOW(val) \
+	REG_FLD_VAL(MT8195_DISP_MERGE_CFG_40_FLD_ULTRA_TH_LOW, (val))
+#define MT8195_DISP_MERGE_CFG_40_VAL_ULTRA_TH_HIGH(val) \
+	REG_FLD_VAL(MT8195_DISP_MERGE_CFG_40_FLD_ULTRA_TH_HIGH, val)
+#define MT8195_DISP_MERGE_CFG_41	0x0b4
+#define MT8195_DISP_MERGE_CFG_41_FLD_PREULTRA_TH_LOW \
+	REG_FLD(16, 0)
+#define MT8195_DISP_MERGE_CFG_41_FLD_PREULTRA_TH_HIGH \
+	REG_FLD(16, 16)
+#define MT8195_DISP_MERGE_CFG_41_VAL_PREULTRA_TH_LOW(val) \
+	REG_FLD_VAL(MT8195_DISP_MERGE_CFG_41_FLD_PREULTRA_TH_LOW, val)
+#define MT8195_DISP_MERGE_CFG_41_VAL_PREULTRA_TH_HIGH(val) \
+	REG_FLD_VAL(MT8195_DISP_MERGE_CFG_41_FLD_PREULTRA_TH_HIGH, val)
+
+struct mtk_disp_merge_data {
+	bool need_golden_setting;
+	enum mtk_ddp_comp_id gs_comp_id;
+};
+
+struct mtk_merge_config_struct {
+	unsigned short width_right;
+	unsigned short width_left;
+	unsigned int height;
+	unsigned int fmt;
+	unsigned int mode;
+	unsigned int swap;
+};
+
+struct mtk_disp_merge {
+	struct mtk_ddp_comp ddp_comp;
+	struct drm_crtc *crtc;
+	struct clk *clk;
+	struct clk *async_clk;
+	void __iomem *regs;
+	struct cmdq_client_reg		cmdq_reg;
+	int irq;
+	void (*vblank_cb)(void *data);
+	void *vblank_cb_data;
+	const struct mtk_disp_merge_data *data;
+};
+
+static struct mtk_ddp_comp *merge_5_comp;
+
+static inline struct mtk_disp_merge *comp_to_merge(struct mtk_ddp_comp *comp)
+{
+	return container_of(comp, struct mtk_disp_merge, ddp_comp);
+}
+
+void mtk_merge_start(struct device *dev)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	mtk_ddp_write_mask(NULL, 0x1, &priv->cmdq_reg, priv->regs,
+		DISP_REG_MERGE_CTRL, ~0);
+}
+
+void mtk_merge_stop(struct device *dev)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	mtk_ddp_write_mask(NULL, 0x0, &priv->cmdq_reg, priv->regs,
+		DISP_REG_MERGE_CTRL, ~0);
+}
+
+static int mtk_merge_check_params(struct mtk_merge_config_struct *merge_config)
+{
+	if (!merge_config->height ||
+		!merge_config->width_left || !merge_config->width_right) {
+		pr_err("%s:merge input width l(%u) w(%u) h(%u)\n",
+			  __func__, merge_config->width_left,
+			  merge_config->width_right, merge_config->height);
+		return -EINVAL;
+	}
+	pr_debug("%s:merge input width l(%u) r(%u) height(%u)\n",
+			  __func__, merge_config->width_left,
+			  merge_config->width_right, merge_config->height);
+	return 0;
+}
+
+static int mtk_merge_golden_setting(struct mtk_disp_merge *priv,
+				  struct cmdq_pkt *handle)
+{
+	int ultra_en = 1;
+	int preultra_en = 1;
+	int halt_for_dvfs_en = 0;
+	int buffer_mode = 3;
+	int vde_block_ultra = 0;
+	int valid_th_block_ultra = 0;
+	int ultra_fifo_valid_th = 0;
+	int nvde_force_preultra = 0;
+	int nvalid_th_force_preultra = 0;
+	int preultra_fifo_valid_th = 0;
+	int ultra_th_low = 0xe10;
+	int ultra_th_high = 0x12c0;
+	int preultra_th_low = 0x12c0;
+	int preultra_th_high = 0x1518;
+
+	mtk_ddp_write_mask(handle,
+		MT8195_DISP_MERGE_CFG_36_VAL_ULTRA_EN(ultra_en) |
+		MT8195_DISP_MERGE_CFG_36_VAL_PREULTRA_EN(preultra_en) |
+		MT8195_DISP_MERGE_CFG_36_VAL_HALT_FOR_DVFS_EN(halt_for_dvfs_en),
+		&priv->cmdq_reg, priv->regs,
+		MT8195_DISP_MERGE_CFG_36,
+		REG_FLD_MASK(MT8195_DISP_MERGE_CFG_36_FLD_ULTRA_EN) |
+		REG_FLD_MASK(MT8195_DISP_MERGE_CFG_36_FLD_PREULTRA_EN) |
+		REG_FLD_MASK(MT8195_DISP_MERGE_CFG_36_FLD_HALT_FOR_DVFS_EN));
+
+	mtk_ddp_write_mask(handle,
+		MT8195_DISP_MERGE_CFG_37_VAL_BUFFER_MODE(buffer_mode),
+		&priv->cmdq_reg, priv->regs,
+		MT8195_DISP_MERGE_CFG_37,
+		REG_FLD_MASK(MT8195_DISP_MERGE_CFG_37_FLD_BUFFER_MODE));
+
+	mtk_ddp_write_mask(handle,
+		MT8195_DISP_MERGE_CFG_38_VAL_VDE_BLOCK_ULTRA
+		(vde_block_ultra) |
+		MT8195_DISP_MERGE_CFG_38_VAL_VALID_TH_BLOCK_ULTRA
+		(valid_th_block_ultra) |
+		MT8195_DISP_MERGE_CFG_38_VAL_ULTRA_FIFO_VALID_TH
+		(ultra_fifo_valid_th),
+		&priv->cmdq_reg, priv->regs,
+		MT8195_DISP_MERGE_CFG_38,
+		REG_FLD_MASK
+		(MT8195_DISP_MERGE_CFG_38_FLD_VDE_BLOCK_ULTRA) |
+		REG_FLD_MASK
+		(MT8195_DISP_MERGE_CFG_38_FLD_VALID_TH_BLOCK_ULTRA) |
+		REG_FLD_MASK
+		(MT8195_DISP_MERGE_CFG_38_FLD_ULTRA_FIFO_VALID_TH));
+
+	mtk_ddp_write_mask(handle,
+		MT8195_DISP_MERGE_CFG_39_VAL_NVDE_FORCE_PREULTRA
+		(nvde_force_preultra) |
+		MT8195_DISP_MERGE_CFG_39_VAL_NVALID_TH_FORCE_PREULTRA
+		(nvalid_th_force_preultra) |
+		MT8195_DISP_MERGE_CFG_39_VAL_PREULTRA_FIFO_VALID_TH
+		(preultra_fifo_valid_th),
+		&priv->cmdq_reg, priv->regs,
+		MT8195_DISP_MERGE_CFG_39,
+		REG_FLD_MASK
+		(MT8195_DISP_MERGE_CFG_39_FLD_NVDE_FORCE_PREULTRA) |
+		REG_FLD_MASK
+		(MT8195_DISP_MERGE_CFG_39_FLD_NVALID_TH_FORCE_PREULTRA) |
+		REG_FLD_MASK
+		(MT8195_DISP_MERGE_CFG_39_FLD_PREULTRA_FIFO_VALID_TH));
+
+	mtk_ddp_write_mask(handle,
+		MT8195_DISP_MERGE_CFG_40_VAL_ULTRA_TH_LOW(ultra_th_low) |
+		MT8195_DISP_MERGE_CFG_40_VAL_ULTRA_TH_HIGH(ultra_th_high),
+		&priv->cmdq_reg, priv->regs,
+		MT8195_DISP_MERGE_CFG_40,
+		REG_FLD_MASK(MT8195_DISP_MERGE_CFG_40_FLD_ULTRA_TH_LOW) |
+		REG_FLD_MASK(MT8195_DISP_MERGE_CFG_40_FLD_ULTRA_TH_HIGH));
+
+	mtk_ddp_write_mask(handle,
+		MT8195_DISP_MERGE_CFG_41_VAL_PREULTRA_TH_LOW(preultra_th_low) |
+		MT8195_DISP_MERGE_CFG_41_VAL_PREULTRA_TH_HIGH(preultra_th_high),
+		&priv->cmdq_reg, priv->regs,
+		MT8195_DISP_MERGE_CFG_41,
+		REG_FLD_MASK(MT8195_DISP_MERGE_CFG_41_FLD_PREULTRA_TH_LOW) |
+		REG_FLD_MASK(MT8195_DISP_MERGE_CFG_41_FLD_PREULTRA_TH_HIGH));
+
+	return 0;
+}
+
+void mtk_merge_config(struct device *dev, unsigned int w,
+				  unsigned int h, unsigned int vrefresh,
+				  unsigned int bpc, struct cmdq_pkt *handle)
+{
+	struct mtk_merge_config_struct merge_config;
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+	struct mtk_ddp_comp *comp = &priv->ddp_comp;
+
+	/*golden setting*/
+	if (priv->data) {
+		if (priv->data->need_golden_setting &&
+			priv->data->gs_comp_id == comp->id)
+			mtk_merge_golden_setting(priv, handle);
+	}
+
+	switch (comp->id) {
+	case DDP_COMPONENT_MERGE0:
+		merge_config.mode = CFG_10_10_1PI_2PO_BUF_MODE;
+		merge_config.width_left = w;
+		merge_config.width_right = w;
+		merge_config.height = h;
+		merge_config.swap = 0;
+		break;
+	case DDP_COMPONENT_MERGE5:
+		merge_config.mode = CFG_10_10_2PI_2PO_BUF_MODE;
+		merge_config.width_left = w;
+		merge_config.width_right = w;
+		merge_config.height = h;
+		merge_config.swap = 0;
+		break;
+	default:
+		pr_err("No find component merge %d\n", comp->id);
+		return;
+	}
+
+	mtk_merge_check_params(&merge_config);
+
+	switch (merge_config.mode) {
+	case CFG_10_10_1PI_1PO_BUF_MODE:
+	case CFG_10_10_1PI_2PO_BUF_MODE:
+	case CFG_10_10_2PI_2PO_BUF_MODE:
+		mtk_ddp_write_mask(handle,
+			(merge_config.height << 16 | merge_config.width_left),
+			&priv->cmdq_reg, priv->regs,
+			MT8195_DISP_MERGE_CFG_0, ~0);
+
+		mtk_ddp_write_mask(handle,
+			(merge_config.height << 16 | merge_config.width_left),
+			&priv->cmdq_reg, priv->regs,
+			MT8195_DISP_MERGE_CFG_4, ~0);
+
+		mtk_ddp_write_mask(handle,
+			(merge_config.height << 16 | merge_config.width_left),
+			&priv->cmdq_reg, priv->regs,
+			MT8195_DISP_MERGE_CFG_24, ~0);
+
+		mtk_ddp_write_mask(handle,
+			(merge_config.height << 16 | merge_config.width_left),
+			&priv->cmdq_reg, priv->regs,
+			MT8195_DISP_MERGE_CFG_25, ~0);
+
+		mtk_ddp_write_mask(handle,
+			merge_config.swap,
+			&priv->cmdq_reg, priv->regs,
+			MT8195_DISP_MERGE_CFG_10, 0x1f);
+	break;
+	case CFG_11_10_1PI_2PO_MERGE:
+		mtk_ddp_write_mask(handle,
+			(merge_config.height << 16 | merge_config.width_left),
+			&priv->cmdq_reg, priv->regs,
+			MT8195_DISP_MERGE_CFG_0, ~0);
+
+		mtk_ddp_write_mask(handle,
+			(merge_config.height << 16 | merge_config.width_right),
+			&priv->cmdq_reg, priv->regs,
+			MT8195_DISP_MERGE_CFG_1, ~0);
+
+		mtk_ddp_write_mask(handle,
+			(merge_config.height << 16 | w),
+			&priv->cmdq_reg, priv->regs,
+			MT8195_DISP_MERGE_CFG_4, ~0);
+
+		mtk_ddp_write_mask(handle,
+			(merge_config.height << 16 | merge_config.width_left),
+			&priv->cmdq_reg, priv->regs,
+			MT8195_DISP_MERGE_CFG_24, ~0);
+
+		mtk_ddp_write_mask(handle,
+			(merge_config.height << 16 | merge_config.width_right),
+			&priv->cmdq_reg, priv->regs,
+			MT8195_DISP_MERGE_CFG_25, ~0);
+
+		mtk_ddp_write_mask(handle,
+			(merge_config.height << 16 | merge_config.width_left),
+			&priv->cmdq_reg, priv->regs,
+			MT8195_DISP_MERGE_CFG_26, ~0);
+
+		mtk_ddp_write_mask(handle,
+			(merge_config.height << 16 | merge_config.width_right),
+			&priv->cmdq_reg, priv->regs,
+			MT8195_DISP_MERGE_CFG_27, ~0);
+
+		mtk_ddp_write_mask(handle,
+			merge_config.swap,
+			&priv->cmdq_reg, priv->regs,
+			MT8195_DISP_MERGE_CFG_10, 0x1f);
+	break;
+	default:
+	break;
+	}
+	mtk_ddp_write_mask(handle, merge_config.mode,
+		&priv->cmdq_reg, priv->regs, MT8195_DISP_MERGE_CFG_12, 0x1f);
+	mtk_ddp_write_mask(handle, 0x1,
+		&priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CTRL, 0x1);
+}
+
+int mtk_merge_clk_enable(struct device *dev)
+{
+	int ret = 0;
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	ret = pm_runtime_get_sync(dev);
+
+	if (priv->clk) {
+		ret = clk_prepare_enable(priv->clk);
+		if (ret)
+			pr_err("merge clk prepare enable failed\n");
+	}
+
+	if (priv->async_clk) {
+		ret = clk_prepare_enable(priv->async_clk);
+		if (ret)
+			pr_err("async clk prepare enable failed\n");
+	}
+
+	return ret;
+}
+
+void mtk_merge_clk_disable(struct device *dev)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	if (priv->async_clk)
+		clk_disable_unprepare(priv->async_clk);
+
+	if (priv->clk)
+		clk_disable_unprepare(priv->clk);
+
+	pm_runtime_put_sync(dev);
+}
+
+void mtk_merge_enable_vblank(struct device *dev,
+			    void (*vblank_cb)(void *),
+			    void *vblank_cb_data)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+	int irq_frame_done_en = BIT(16);
+
+	priv->vblank_cb = vblank_cb;
+	priv->vblank_cb_data = vblank_cb_data;
+
+	writel(irq_frame_done_en, priv->regs + DISP_REG_MERGE_CFG2_0);
+}
+
+void mtk_merge_disable_vblank(struct device *dev)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	priv->vblank_cb = NULL;
+	priv->vblank_cb_data = NULL;
+
+	writel(0x0, priv->regs + DISP_REG_MERGE_CFG2_0);
+}
+
+static int mtk_disp_merge_bind(struct device *dev, struct device *master,
+			       void *data)
+{
+	return 0;
+}
+
+static void mtk_disp_merge_unbind(struct device *dev, struct device *master,
+				  void *data)
+{
+}
+
+static irqreturn_t mtk_disp_merge_irq_handler(int irq, void *dev_id)
+{
+	struct mtk_disp_merge *priv = dev_id;
+
+	/* Clear frame completion interrupt */
+	writel(0x1, priv->regs + DISP_REG_MERGE_CFG2_2);
+	writel(0x0, priv->regs + DISP_REG_MERGE_CFG2_2);
+
+	if (!priv->vblank_cb)
+		return IRQ_NONE;
+
+	priv->vblank_cb(priv->vblank_cb_data);
+
+	return IRQ_HANDLED;
+}
+
+static const struct component_ops mtk_disp_merge_component_ops = {
+	.bind	= mtk_disp_merge_bind,
+	.unbind = mtk_disp_merge_unbind,
+};
+
+static int mtk_disp_merge_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct resource *res;
+	struct mtk_disp_merge *priv;
+	enum mtk_ddp_comp_id comp_id;
+	int ret;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_MERGE);
+	if ((int)comp_id < 0) {
+		dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
+		return comp_id;
+	}
+
+	priv->ddp_comp.id = comp_id;
+
+	if (comp_id == DDP_COMPONENT_MERGE5)
+		merge_5_comp = &priv->ddp_comp;
+
+	priv->clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(priv->clk)) {
+		dev_err(dev, "failed to get merge clk\n");
+		return PTR_ERR(priv->clk);
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	priv->regs = devm_ioremap_resource(dev, res);
+	if (IS_ERR(priv->regs)) {
+		dev_err(dev, "failed to ioremap merge\n");
+		return PTR_ERR(priv->regs);
+	}
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+	ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
+	if (ret)
+		dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+
+	priv->irq = platform_get_irq(pdev, 0);
+	if (priv->irq < 0)
+		priv->irq = 0;
+
+	priv->async_clk = of_clk_get(dev->of_node, 1);
+	if (IS_ERR(priv->async_clk)) {
+		ret = PTR_ERR(priv->async_clk);
+		dev_dbg(dev, "No merge async clock: %d\n", ret);
+		priv->async_clk = NULL;
+	}
+
+	priv->data = of_device_get_match_data(dev);
+
+	if (priv->irq) {
+		ret = devm_request_irq(dev, priv->irq,
+					mtk_disp_merge_irq_handler,
+					IRQF_TRIGGER_NONE, dev_name(dev), priv);
+		if (ret < 0) {
+			dev_err(dev, "Failed to request irq %d: %d\n",
+					priv->irq, ret);
+			return ret;
+		}
+	}
+
+	platform_set_drvdata(pdev, priv);
+
+	pm_runtime_enable(dev);
+
+	ret = component_add(dev, &mtk_disp_merge_component_ops);
+	if (ret != 0) {
+		dev_err(dev, "Failed to add component: %d\n", ret);
+		pm_runtime_disable(dev);
+	}
+
+	return ret;
+}
+
+static int mtk_disp_merge_remove(struct platform_device *pdev)
+{
+	component_del(&pdev->dev, &mtk_disp_merge_component_ops);
+
+	pm_runtime_disable(&pdev->dev);
+
+	return 0;
+}
+
+static const struct mtk_disp_merge_data mt8195_merge_driver_data = {
+	.need_golden_setting = true,
+	.gs_comp_id = DDP_COMPONENT_MERGE5,
+};
+
+static const struct of_device_id mtk_disp_merge_driver_dt_match[] = {
+	{
+		.compatible = "mediatek,mt8195-disp-merge",
+		.data = &mt8195_merge_driver_data
+	},
+	{},
+};
+
+MODULE_DEVICE_TABLE(of, mtk_disp_merge_driver_dt_match);
+
+struct platform_driver mtk_disp_merge_driver = {
+	.probe = mtk_disp_merge_probe,
+	.remove = mtk_disp_merge_remove,
+	.driver = {
+		.name = "mediatek-disp-merge",
+		.owner = THIS_MODULE,
+		.of_match_table = mtk_disp_merge_driver_dt_match,
+	},
+};
+
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
index cb9a36c48d4f..7419cd0fb424 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
@@ -14,6 +14,37 @@
 #define MTK_MAX_BPC	10
 #define MTK_MIN_BPC	3
 
+#define _MASK_SHIFT(val, width, shift) \
+	(((val) >> (shift)) & ((1 << (width)) - 1))
+
+#define REG_FLD(width, shift) \
+	((unsigned int)((((width) & 0xff) << 16) | ((shift) & 0xff)))
+
+#define REG_FLD_MSB_LSB(msb, lsb) REG_FLD((msb) - (lsb) + 1, (lsb))
+
+#define REG_FLD_WIDTH(field) ((unsigned int)(((field) >> 16) & 0xff))
+
+#define REG_FLD_SHIFT(field) ((unsigned int)((field) & 0xff))
+
+#define REG_FLD_MASK(field) \
+	((unsigned int)((1ULL << REG_FLD_WIDTH(field)) - 1) \
+	 << REG_FLD_SHIFT(field))
+
+#define REG_FLD_VAL(field, val) \
+	(((val) << REG_FLD_SHIFT(field)) & REG_FLD_MASK(field))
+
+#define REG_FLD_VAL_GET(field, regval) \
+	(((regval) & REG_FLD_MASK(field)) >> REG_FLD_SHIFT(field))
+
+#define DISP_REG_GET_FIELD(field, reg32) \
+	REG_FLD_VAL_GET(field, __raw_readl((unsigned long *)(reg32)))
+
+#define SET_VAL_MASK(o_val, o_mask, i_val, i_fld) \
+	do { \
+		(o_val) |= ((i_val) << REG_FLD_SHIFT(i_fld)); \
+		(o_mask) |= (REG_FLD_MASK(i_fld)); \
+	} while (0)
+
 void mtk_drm_crtc_commit(struct drm_crtc *crtc);
 int mtk_drm_crtc_create(struct drm_device *drm_dev,
 			const enum mtk_ddp_comp_id *path,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index f154f7c0cd11..2ccf3db1950d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -339,6 +339,14 @@ static const struct mtk_ddp_comp_funcs ddp_rdma = {
 	.layer_config = mtk_rdma_layer_config,
 };
 
+static const struct mtk_ddp_comp_funcs ddp_merge = {
+	.clk_enable = mtk_merge_clk_enable,
+	.clk_disable = mtk_merge_clk_disable,
+	.start = mtk_merge_start,
+	.stop = mtk_merge_stop,
+	.config = mtk_merge_config,
+};
+
 static const struct mtk_ddp_comp_funcs ddp_ufoe = {
 	.clk_enable = mtk_ddp_clk_enable,
 	.clk_disable = mtk_ddp_clk_disable,
@@ -362,6 +370,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
 	[MTK_DISP_MUTEX] = "mutex",
 	[MTK_DISP_OD] = "od",
 	[MTK_DISP_BLS] = "bls",
+	[MTK_DISP_MERGE] = "merge",
 };
 
 struct mtk_ddp_comp_match {
@@ -397,6 +406,12 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_RDMA0]	= { MTK_DISP_RDMA,	0, &ddp_rdma },
 	[DDP_COMPONENT_RDMA1]	= { MTK_DISP_RDMA,	1, &ddp_rdma },
 	[DDP_COMPONENT_RDMA2]	= { MTK_DISP_RDMA,	2, &ddp_rdma },
+	[DDP_COMPONENT_MERGE0]	= { MTK_DISP_MERGE,	0, &ddp_merge },
+	[DDP_COMPONENT_MERGE1]	= { MTK_DISP_MERGE,	1, &ddp_merge },
+	[DDP_COMPONENT_MERGE2]	= { MTK_DISP_MERGE,	2, &ddp_merge },
+	[DDP_COMPONENT_MERGE3]	= { MTK_DISP_MERGE,	3, &ddp_merge },
+	[DDP_COMPONENT_MERGE4]	= { MTK_DISP_MERGE,	4, &ddp_merge },
+	[DDP_COMPONENT_MERGE5]	= { MTK_DISP_MERGE,	5, &ddp_merge },
 	[DDP_COMPONENT_UFOE]	= { MTK_DISP_UFOE,	0, &ddp_ufoe },
 	[DDP_COMPONENT_WDMA0]	= { MTK_DISP_WDMA,	0, NULL },
 	[DDP_COMPONENT_WDMA1]	= { MTK_DISP_WDMA,	1, NULL },
@@ -515,6 +530,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
 	    type == MTK_DISP_CCORR ||
 	    type == MTK_DISP_COLOR ||
 	    type == MTK_DISP_GAMMA ||
+	    type == MTK_DISP_MERGE ||
 	    type == MTK_DPI ||
 	    type == MTK_DSI ||
 	    type == MTK_DISP_OVL ||
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index bb914d976cf5..038775b4531b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -34,6 +34,7 @@ enum mtk_ddp_comp_type {
 	MTK_DISP_MUTEX,
 	MTK_DISP_OD,
 	MTK_DISP_BLS,
+	MTK_DISP_MERGE,
 	MTK_DDP_COMP_TYPE_MAX,
 };
 
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 635cebf9ff0f..f891316008aa 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -462,6 +462,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_DITHER },
 	{ .compatible = "mediatek,mt8195-disp-dither",
 	  .data = (void *)MTK_DISP_DITHER },
+	{ .compatible = "mediatek,mt8195-disp-merge",
+	  .data = (void *)MTK_DISP_MERGE },
 	{ .compatible = "mediatek,mt8173-disp-ufoe",
 	  .data = (void *)MTK_DISP_UFOE },
 	{ .compatible = "mediatek,mt2701-dsi",
@@ -579,6 +581,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
 		if (comp_type == MTK_DISP_CCORR ||
 		    comp_type == MTK_DISP_COLOR ||
 		    comp_type == MTK_DISP_GAMMA ||
+		    comp_type == MTK_DISP_MERGE ||
 		    comp_type == MTK_DISP_OVL ||
 		    comp_type == MTK_DISP_OVL_2L ||
 		    comp_type == MTK_DISP_RDMA ||
@@ -683,6 +686,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
 	&mtk_disp_rdma_driver,
 	&mtk_dpi_driver,
 	&mtk_drm_platform_driver,
+	&mtk_disp_merge_driver,
 	&mtk_dsi_driver,
 };
 
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 637f5669e895..18548a373626 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -51,6 +51,7 @@ extern struct platform_driver mtk_disp_color_driver;
 extern struct platform_driver mtk_disp_gamma_driver;
 extern struct platform_driver mtk_disp_ovl_driver;
 extern struct platform_driver mtk_disp_rdma_driver;
+extern struct platform_driver mtk_disp_merge_driver;
 extern struct platform_driver mtk_dpi_driver;
 extern struct platform_driver mtk_dsi_driver;
 
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 080bdabfb024..84ece5486902 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -284,6 +284,7 @@ static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
 	[DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
 	[DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
+	[DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
 	[DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
 	[DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
 };
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 2228bf6133da..3135ce82a7f7 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -39,6 +39,12 @@ enum mtk_ddp_comp_id {
 	DDP_COMPONENT_UFOE,
 	DDP_COMPONENT_WDMA0,
 	DDP_COMPONENT_WDMA1,
+	DDP_COMPONENT_MERGE0,
+	DDP_COMPONENT_MERGE1,
+	DDP_COMPONENT_MERGE2,
+	DDP_COMPONENT_MERGE3,
+	DDP_COMPONENT_MERGE4,
+	DDP_COMPONENT_MERGE5,
 	DDP_COMPONENT_ID_MAX,
 };
 
-- 
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 42+ messages in thread

* [PATCH v1 17/17] drm/mediatek: add DSC support for MT8195
  2021-07-07  4:12 [PATCH v1 00/17] Add MediaTek SoC DRM (vdosys0) support for mt8195 jason-jh.lin
                   ` (15 preceding siblings ...)
  2021-07-07  4:12 ` [PATCH v1 16/17] drm/mediatek: add MERGE " jason-jh.lin
@ 2021-07-07  4:12 ` jason-jh.lin
  2021-07-07  7:35   ` CK Hu
  16 siblings, 1 reply; 42+ messages in thread
From: jason-jh.lin @ 2021-07-07  4:12 UTC (permalink / raw)
  To: chunkuang.hu, matthias.bgg
  Cc: linux-arm-kernel, linux-mediatek, linux-kernel, devicetree,
	Project_Global_Chrome_Upstream_Group, fshao, jason-jh.lin,
	nancy.lin, singo.chang

1. Add DSC module file.
2. Add mtk_panel_ext source file to get the mtk_panel_dsc_params
   from panel.
3. Add DSC related path to mtk-mmsys routing table.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 drivers/gpu/drm/mediatek/Makefile           |   4 +-
 drivers/gpu/drm/mediatek/mtk_disp_drv.h     |   8 +
 drivers/gpu/drm/mediatek/mtk_disp_dsc.c     | 286 ++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_drm_crtc.h     |   1 +
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |  13 +
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |   1 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c      |   4 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.h      |   1 +
 drivers/gpu/drm/mediatek/mtk_panel_ext.c    | 136 ++++++++
 drivers/gpu/drm/mediatek/mtk_panel_ext.h    | 344 ++++++++++++++++++++
 drivers/soc/mediatek/mt8195-mmsys.h         |  18 +
 drivers/soc/mediatek/mtk-mutex.c            |   1 +
 include/linux/soc/mediatek/mtk-mmsys.h      |   3 +
 13 files changed, 819 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_dsc.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_panel_ext.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_panel_ext.h

diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 5fd95b9d5aae..4dc0b2901a22 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -6,13 +6,15 @@ mediatek-drm-y := mtk_disp_ccorr.o \
 		  mtk_disp_ovl.o \
 		  mtk_disp_rdma.o \
 		  mtk_disp_merge.o \
+		  mtk_disp_dsc.o \
 		  mtk_drm_crtc.o \
 		  mtk_drm_ddp_comp.o \
 		  mtk_drm_drv.o \
 		  mtk_drm_gem.o \
 		  mtk_drm_plane.o \
 		  mtk_dsi.o \
-		  mtk_dpi.o
+		  mtk_dpi.o \
+		  mtk_panel_ext.o
 
 obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
 
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 7fd5260e2a72..11a6c9d6cff3 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -100,4 +100,12 @@ void mtk_merge_config(struct device *dev, unsigned int width,
 void mtk_merge_start(struct device *dev);
 void mtk_merge_stop(struct device *dev);
 
+int mtk_dsc_clk_enable(struct device *dev);
+void mtk_dsc_clk_disable(struct device *dev);
+void mtk_dsc_config(struct device *dev, unsigned int width,
+		     unsigned int height, unsigned int vrefresh,
+		     unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_dsc_start(struct device *dev);
+void mtk_dsc_stop(struct device *dev);
+
 #endif
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_dsc.c b/drivers/gpu/drm/mediatek/mtk_disp_dsc.c
new file mode 100644
index 000000000000..5da820feead5
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_dsc.c
@@ -0,0 +1,286 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_drm_gem.h"
+#include "mtk_disp_drv.h"
+#ifdef CONFIG_MTK_DPTX_SUPPORT
+#include "mtk_dp_api.h"
+#endif
+
+#define DISP_REG_DSC_CON			0x0000
+#define DSC_EN						BIT(0)
+#define DSC_DUAL_INOUT				BIT(2)
+#define DSC_IN_SRC_SEL				BIT(3)
+#define DSC_BYPASS					BIT(4)
+#define DSC_RELAY					BIT(5)
+#define DSC_EMPTY_FLAG_SEL			0xc000
+#define DSC_UFOE_SEL				BIT(16)
+#define DISP_REG_DSC_OBUF			0x0070
+
+struct mtk_disp_dsc_data {
+	bool support_shadow;
+};
+
+/**
+ * struct mtk_disp_dsc - DISP_DSC driver structure
+ * @clk - clk of dsc hardware
+ * @regs - hardware register address of dsc
+ * @ddp_comp - structure containing type enum and hardware resources
+ * @cmdq_reg - structure containing cmdq hardware resource
+ * @data - dsc driver data
+ * @enable - enable dsc hardward
+ */
+struct mtk_disp_dsc {
+	struct clk *clk;
+	void __iomem *regs;
+	struct mtk_ddp_comp	ddp_comp;
+	struct cmdq_client_reg		cmdq_reg;
+	const struct mtk_disp_dsc_data *data;
+	int enable;
+};
+
+void mtk_dsc_start(struct device *dev)
+{
+	struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
+	void __iomem *baddr = dsc->regs;
+	int ret = 0;
+
+	ret = pm_runtime_get_sync(dev);
+	if (ret < 0)
+		DRM_ERROR("Failed to enable power domain: %d\n", ret);
+
+	if (dsc->enable) {
+		int high = BIT(14);
+		int obud_sw = BIT(31);
+		int obud_size = 706; /* unit is 6 byte */
+
+		/* DSC Empty flag always high */
+		mtk_ddp_write_mask(NULL, high,
+			&dsc->cmdq_reg, baddr,
+			DISP_REG_DSC_CON, DSC_EMPTY_FLAG_SEL);
+
+		/* DSC output buffer as FHD(plus) */
+		mtk_ddp_write_mask(NULL, (obud_sw | obud_size),
+			&dsc->cmdq_reg, baddr,
+			DISP_REG_DSC_OBUF, ~0);
+	}
+
+	mtk_ddp_write_mask(NULL, DSC_EN,
+		&dsc->cmdq_reg, baddr,
+		DISP_REG_DSC_CON, DSC_EN);
+
+	pr_debug("dsc_start:0x%x\n", readl(baddr + DISP_REG_DSC_CON));
+}
+
+void mtk_dsc_stop(struct device *dev)
+{
+	struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
+	void __iomem *baddr = dsc->regs;
+	int ret = 0;
+
+	mtk_ddp_write_mask(NULL, 0x0, &dsc->cmdq_reg, baddr,
+		DISP_REG_DSC_CON, DSC_EN);
+
+	pr_debug("dsc_stop:0x%x\n", readl(baddr + DISP_REG_DSC_CON));
+
+	ret = pm_runtime_put(dev);
+	if (ret < 0)
+		DRM_ERROR("Failed to disable power domain: %d\n", ret);
+}
+
+int mtk_dsc_clk_enable(struct device *dev)
+{
+	struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
+
+	return clk_prepare_enable(dsc->clk);
+}
+
+void mtk_dsc_clk_disable(struct device *dev)
+{
+	struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
+
+	clk_disable_unprepare(dsc->clk);
+}
+
+static struct mtk_panel_dsc_params *mtk_dsc_default_setting(void)
+{
+	static struct mtk_panel_dsc_params dsc_params = {
+		.enable = 0, /* 0: bypass mode */
+		.ver = 2,
+		.slice_mode = 1,
+		.rgb_swap = 0,
+		.dsc_cfg = 0x12, /* flatness_det_thr, 8bit */
+		.rct_on = 1, // default
+		.bit_per_channel = 8,
+		.dsc_line_buf_depth = 13, /* 9, 11: for 10bit */
+		.bp_enable = 1, /* align vend */
+		.bit_per_pixel = 128, /* 16 x bpp */
+		.pic_height = 2160,
+		.pic_width = 3840, /* for dp port 4k scenario */
+		.slice_height = 8,
+		.slice_width = 1920, /* frame_width/slice mode */
+		.chunk_size = 1920,
+		.xmit_delay = 512,
+		.dec_delay = 1216,
+		.scale_value = 32,
+		.increment_interval = 286,
+		.decrement_interval = 26,
+		.line_bpg_offset = 12,
+		.nfl_bpg_offset = 3511,
+		.slice_bpg_offset = 916,
+		.initial_offset = 6144,
+		.final_offset = 4336,
+		.flatness_minqp = 3,
+		.flatness_maxqp = 12,
+		.rc_model_size = 8192,
+		.rc_edge_factor = 6,
+		.rc_quant_incr_limit0 = 11,
+		.rc_quant_incr_limit1 = 11,
+		.rc_tgt_offset_hi = 3,
+		.rc_tgt_offset_lo = 3,
+	};
+
+	return &dsc_params;
+}
+
+void mtk_dsc_config(struct device *dev, unsigned int w,
+				unsigned int h, unsigned int vrefresh,
+				unsigned int bpc, struct cmdq_pkt *handle)
+{
+	struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
+	struct mtk_ddp_comp *comp = &dsc->ddp_comp;
+	struct mtk_panel_dsc_params *dsc_params;
+
+	dsc_params = mtk_dsc_default_setting();
+
+	if (dsc_params->enable == 1) {
+		/* dsc enable mode not support yet */
+		pr_debug("comp_id:%d, w:%d, h:%d\n",
+			comp->id, w, h);
+		pr_debug("slice_mode:%d, slice(%d,%d), bpp:%d\n",
+			dsc_params->slice_mode, dsc_params->slice_width,
+			dsc_params->slice_height, dsc_params->bit_per_pixel);
+	} else {
+		/* dsc bypass mode */
+		mtk_ddp_write_mask(handle, DSC_BYPASS,
+			&dsc->cmdq_reg, dsc->regs,
+			DISP_REG_DSC_CON, DSC_BYPASS);
+		mtk_ddp_write_mask(handle, DSC_UFOE_SEL,
+			&dsc->cmdq_reg, dsc->regs,
+			DISP_REG_DSC_CON, DSC_UFOE_SEL);
+		mtk_ddp_write_mask(handle, DSC_DUAL_INOUT,
+			&dsc->cmdq_reg, dsc->regs,
+			DISP_REG_DSC_CON, DSC_DUAL_INOUT);
+		dsc->enable = false;
+	}
+}
+
+static int mtk_disp_dsc_bind(struct device *dev, struct device *master,
+				  void *data)
+{
+	return 0;
+}
+
+static void mtk_disp_dsc_unbind(struct device *dev, struct device *master,
+				 void *data)
+{
+}
+
+static const struct component_ops mtk_disp_dsc_component_ops = {
+	.bind = mtk_disp_dsc_bind,
+	.unbind = mtk_disp_dsc_unbind,
+};
+
+static int mtk_disp_dsc_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct resource *res;
+	struct mtk_disp_dsc *priv;
+	int irq;
+	int ret;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0)
+		return irq;
+
+	priv->clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(priv->clk)) {
+		dev_err(dev, "failed to get dsc clk\n");
+		return PTR_ERR(priv->clk);
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	priv->regs = devm_ioremap_resource(dev, res);
+	if (IS_ERR(priv->regs)) {
+		dev_err(dev, "failed to ioremap dsc\n");
+		return PTR_ERR(priv->regs);
+	}
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+	ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
+	if (ret)
+		dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+
+	priv->data = of_device_get_match_data(dev);
+	platform_set_drvdata(pdev, priv);
+
+	pm_runtime_enable(dev);
+
+	ret = component_add(dev, &mtk_disp_dsc_component_ops);
+	if (ret != 0) {
+		dev_err(dev, "Failed to add component: %d\n", ret);
+		pm_runtime_disable(dev);
+	}
+
+	return ret;
+}
+
+static int mtk_disp_dsc_remove(struct platform_device *pdev)
+{
+	component_del(&pdev->dev, &mtk_disp_dsc_component_ops);
+
+	pm_runtime_disable(&pdev->dev);
+
+	return 0;
+}
+
+static const struct mtk_disp_dsc_data mt8195_dsc_driver_data = {
+	.support_shadow = false,
+};
+
+static const struct of_device_id mtk_disp_dsc_driver_dt_match[] = {
+	{
+		.compatible = "mediatek,mt8195-disp-dsc",
+		.data = &mt8195_dsc_driver_data
+	},
+	{},
+};
+
+MODULE_DEVICE_TABLE(of, mtk_disp_dsc_driver_dt_match);
+
+struct platform_driver mtk_disp_dsc_driver = {
+	.probe = mtk_disp_dsc_probe,
+	.remove = mtk_disp_dsc_remove,
+	.driver = {
+		.name = "mediatek-disp-dsc",
+		.owner = THIS_MODULE,
+		.of_match_table = mtk_disp_dsc_driver_dt_match,
+	},
+};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
index 7419cd0fb424..7b8f9cb96d44 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
@@ -9,6 +9,7 @@
 #include <drm/drm_crtc.h>
 #include "mtk_drm_ddp_comp.h"
 #include "mtk_drm_plane.h"
+#include "mtk_panel_ext.h"
 
 #define MTK_LUT_SIZE	512
 #define MTK_MAX_BPC	10
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 2ccf3db1950d..b68bde6eb6ed 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -347,6 +347,14 @@ static const struct mtk_ddp_comp_funcs ddp_merge = {
 	.config = mtk_merge_config,
 };
 
+static const struct mtk_ddp_comp_funcs ddp_dsc = {
+	.config = mtk_dsc_config,
+	.start = mtk_dsc_start,
+	.stop = mtk_dsc_stop,
+	.clk_enable = mtk_dsc_clk_enable,
+	.clk_disable = mtk_dsc_clk_disable,
+};
+
 static const struct mtk_ddp_comp_funcs ddp_ufoe = {
 	.clk_enable = mtk_ddp_clk_enable,
 	.clk_disable = mtk_ddp_clk_disable,
@@ -371,6 +379,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
 	[MTK_DISP_OD] = "od",
 	[MTK_DISP_BLS] = "bls",
 	[MTK_DISP_MERGE] = "merge",
+	[MTK_DISP_DSC] = "dsc",
 };
 
 struct mtk_ddp_comp_match {
@@ -412,6 +421,9 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_MERGE3]	= { MTK_DISP_MERGE,	3, &ddp_merge },
 	[DDP_COMPONENT_MERGE4]	= { MTK_DISP_MERGE,	4, &ddp_merge },
 	[DDP_COMPONENT_MERGE5]	= { MTK_DISP_MERGE,	5, &ddp_merge },
+	[DDP_COMPONENT_DSC0]	= { MTK_DISP_DSC,	0, &ddp_dsc },
+	[DDP_COMPONENT_DSC1]	= { MTK_DISP_DSC,	1, &ddp_dsc },
+	[DDP_COMPONENT_DSC1_VIRTUAL0]	= { MTK_DISP_DSC,	-1, &ddp_dsc },
 	[DDP_COMPONENT_UFOE]	= { MTK_DISP_UFOE,	0, &ddp_ufoe },
 	[DDP_COMPONENT_WDMA0]	= { MTK_DISP_WDMA,	0, NULL },
 	[DDP_COMPONENT_WDMA1]	= { MTK_DISP_WDMA,	1, NULL },
@@ -531,6 +543,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
 	    type == MTK_DISP_COLOR ||
 	    type == MTK_DISP_GAMMA ||
 	    type == MTK_DISP_MERGE ||
+	    type == MTK_DISP_DSC ||
 	    type == MTK_DPI ||
 	    type == MTK_DSI ||
 	    type == MTK_DISP_OVL ||
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 038775b4531b..b4f6b52dac69 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -35,6 +35,7 @@ enum mtk_ddp_comp_type {
 	MTK_DISP_OD,
 	MTK_DISP_BLS,
 	MTK_DISP_MERGE,
+	MTK_DISP_DSC,
 	MTK_DDP_COMP_TYPE_MAX,
 };
 
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index f891316008aa..af3e69e0edbe 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -464,6 +464,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_DITHER },
 	{ .compatible = "mediatek,mt8195-disp-merge",
 	  .data = (void *)MTK_DISP_MERGE },
+	{ .compatible = "mediatek,mt8195-disp-dsc",
+	  .data = (void *)MTK_DISP_DSC },
 	{ .compatible = "mediatek,mt8173-disp-ufoe",
 	  .data = (void *)MTK_DISP_UFOE },
 	{ .compatible = "mediatek,mt2701-dsi",
@@ -582,6 +584,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
 		    comp_type == MTK_DISP_COLOR ||
 		    comp_type == MTK_DISP_GAMMA ||
 		    comp_type == MTK_DISP_MERGE ||
+		    comp_type == MTK_DISP_DSC ||
 		    comp_type == MTK_DISP_OVL ||
 		    comp_type == MTK_DISP_OVL_2L ||
 		    comp_type == MTK_DISP_RDMA ||
@@ -687,6 +690,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
 	&mtk_dpi_driver,
 	&mtk_drm_platform_driver,
 	&mtk_disp_merge_driver,
+	&mtk_disp_dsc_driver,
 	&mtk_dsi_driver,
 };
 
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 18548a373626..7f821b96aac3 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -52,6 +52,7 @@ extern struct platform_driver mtk_disp_gamma_driver;
 extern struct platform_driver mtk_disp_ovl_driver;
 extern struct platform_driver mtk_disp_rdma_driver;
 extern struct platform_driver mtk_disp_merge_driver;
+extern struct platform_driver mtk_disp_dsc_driver;
 extern struct platform_driver mtk_dpi_driver;
 extern struct platform_driver mtk_dsi_driver;
 
diff --git a/drivers/gpu/drm/mediatek/mtk_panel_ext.c b/drivers/gpu/drm/mediatek/mtk_panel_ext.c
new file mode 100644
index 000000000000..5887a1cd08bc
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_panel_ext.c
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#include <linux/err.h>
+#include <linux/module.h>
+
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_mipi_dsi.h>
+
+#include <drm/drm_panel.h>
+
+#include "mtk_panel_ext.h"
+
+struct _panel_rst_ctx {
+	struct drm_panel *panel;
+	panel_tch_rst rst_cb;
+};
+
+static DEFINE_MUTEX(panel_ext_lock);
+static LIST_HEAD(panel_ext_list);
+static struct _panel_rst_ctx panel_rst_ctx;
+
+void mtk_panel_init(struct mtk_panel_ctx *ctx)
+{
+	INIT_LIST_HEAD(&ctx->list);
+}
+
+void mtk_panel_add(struct mtk_panel_ctx *ctx)
+{
+	mutex_lock(&panel_ext_lock);
+	list_add_tail(&ctx->list, &panel_ext_list);
+	mutex_unlock(&panel_ext_lock);
+}
+
+void mtk_panel_remove(struct mtk_panel_ctx *ctx)
+{
+	mutex_lock(&panel_ext_lock);
+	list_del_init(&ctx->list);
+	mutex_unlock(&panel_ext_lock);
+}
+
+int mtk_panel_attach(struct mtk_panel_ctx *ctx, struct drm_panel *panel)
+{
+	if (ctx->panel)
+		return -EBUSY;
+
+	ctx->panel = panel;
+
+	return 0;
+}
+
+int mtk_panel_tch_handle_reg(struct drm_panel *panel)
+{
+	mutex_lock(&panel_ext_lock);
+	if (panel_rst_ctx.panel) {
+		mutex_unlock(&panel_ext_lock);
+		return -EEXIST;
+	}
+	panel_rst_ctx.panel = panel;
+	mutex_unlock(&panel_ext_lock);
+
+	return 0;
+}
+
+void **mtk_panel_tch_handle_init(void)
+{
+	return (void **)&panel_rst_ctx.rst_cb;
+}
+
+int mtk_panel_tch_rst(struct drm_panel *panel)
+{
+	int ret = 0;
+
+	mutex_lock(&panel_ext_lock);
+	if (panel_rst_ctx.rst_cb && panel_rst_ctx.panel == panel)
+		panel_rst_ctx.rst_cb();
+	else
+		ret = -EEXIST;
+	mutex_unlock(&panel_ext_lock);
+
+	return ret;
+}
+
+int mtk_panel_detach(struct mtk_panel_ctx *ctx)
+{
+	ctx->panel = NULL;
+
+	return 0;
+}
+
+int mtk_panel_ext_create(struct device *dev,
+			 struct mtk_panel_params *ext_params,
+			 struct mtk_panel_funcs *ext_funcs,
+			 struct drm_panel *panel)
+{
+	struct mtk_panel_ctx *ext_ctx;
+	struct mtk_panel_ext *ext;
+
+	ext_ctx = devm_kzalloc(dev, sizeof(struct mtk_panel_ctx), GFP_KERNEL);
+	if (!ext_ctx)
+		return -ENOMEM;
+
+	ext = devm_kzalloc(dev, sizeof(struct mtk_panel_ext), GFP_KERNEL);
+	if (!ext)
+		return -ENOMEM;
+
+	mtk_panel_init(ext_ctx);
+	ext->params = ext_params;
+	ext->funcs = ext_funcs;
+	ext_ctx->ext = ext;
+
+	mtk_panel_add(ext_ctx);
+	mtk_panel_attach(ext_ctx, panel);
+
+	return 0;
+}
+
+struct mtk_panel_ext *find_panel_ext(struct drm_panel *panel)
+{
+	struct mtk_panel_ctx *ctx;
+
+	mutex_lock(&panel_ext_lock);
+
+	list_for_each_entry(ctx, &panel_ext_list, list) {
+		if (ctx->panel == panel) {
+			mutex_unlock(&panel_ext_lock);
+			return ctx->ext;
+		}
+	}
+
+	mutex_unlock(&panel_ext_lock);
+	return NULL;
+}
diff --git a/drivers/gpu/drm/mediatek/mtk_panel_ext.h b/drivers/gpu/drm/mediatek/mtk_panel_ext.h
new file mode 100644
index 000000000000..f828d468817d
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_panel_ext.h
@@ -0,0 +1,344 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef __MTK_PANEL_EXT_H__
+#define __MTK_PANEL_EXT_H__
+
+#include <drm/drm_panel.h>
+
+#define RT_MAX_NUM 10
+#define ESD_CHECK_NUM 3
+#define MAX_TX_CMD_NUM 20
+#define MAX_RX_CMD_NUM 20
+#define READ_DDIC_SLOT_NUM 4
+#define MAX_DYN_CMD_NUM 20
+
+struct mtk_dsi;
+struct cmdq_pkt;
+struct mtk_panel_para_table {
+	u8 count;
+	u8 para_list[64];
+};
+
+/*
+ *	DSI data type:
+ *	DSI_DCS_WRITE_SHORT_PACKET_NO_PARAM		0x05
+ *	DSI_DCS_WRITE_SHORT_PACKET_1_PARAM		0x15
+ *	DSI_DCS_WRITE_LONG_PACKET				0x39
+ *	DSI_DCS_READ_NO_PARAM					0x06
+
+ *	DSI_GERNERIC_WRITE_SHORT_NO_PARAM		0x03
+ *	DSI_GERNERIC_WRITE_SHORT_1_PARAM		0x13
+ *	DSI_GERNERIC_WRITE_SHORT_1_PARAM		0x23
+ *	DSI_GERNERIC_WRITE_LONG_PACKET			0x29
+ *	DSI_GERNERIC_READ_NO_PARAM				0x04
+ *	DSI_GERNERIC_READ_1_PARAM				0x14
+ *	DSI_GERNERIC_READ_2_PARAM				0x24
+ */
+
+/**
+ * struct mtk_ddic_dsi_msg - MTK write/read DDIC RG cmd buffer
+ * @channel: virtual channel id
+ * @flags: flags controlling this message transmission
+ * @type: payload data type array
+ * @tx_len: length of @tx_buf
+ * @tx_buf: data array to be written
+ * @tx_cmd_num: tx cmd number
+ * @rx_len: length of @rx_buf
+ * @rx_buf: data array to be read, or NULL
+ * @rx_cmd_num: rx cmd number
+ */
+struct mtk_ddic_dsi_msg {
+	u8 channel;
+	u16 flags;
+
+	u8 type[MAX_TX_CMD_NUM];
+	size_t tx_len[MAX_TX_CMD_NUM];
+	const void *tx_buf[MAX_TX_CMD_NUM];
+	size_t tx_cmd_num;
+
+	size_t rx_len[MAX_RX_CMD_NUM];
+	void *rx_buf[MAX_RX_CMD_NUM];
+	size_t rx_cmd_num;
+};
+
+struct DSI_RX_DATA_REG {
+	unsigned char byte0;
+	unsigned char byte1;
+	unsigned char byte2;
+	unsigned char byte3;
+};
+
+typedef void (*dcs_write_gce) (struct mtk_dsi *dsi, struct cmdq_pkt *handle,
+				const void *data, size_t len);
+typedef void (*dcs_grp_write_gce) (struct mtk_dsi *dsi, struct cmdq_pkt *handle,
+				struct mtk_panel_para_table *para_table,
+				unsigned int para_size);
+typedef int (*panel_tch_rst) (void);
+
+enum MTK_PANEL_OUTPUT_MODE {
+	MTK_PANEL_SINGLE_PORT = 0x0,
+	MTK_PANEL_DSC_SINGLE_PORT,
+	MTK_PANEL_DUAL_PORT,
+};
+
+struct esd_check_item {
+	unsigned char cmd;
+	unsigned char count;
+	unsigned char para_list[RT_MAX_NUM];
+	unsigned char mask_list[RT_MAX_NUM];
+};
+
+enum MTK_PANEL_MODE_SWITCH_STAGE {
+	BEFORE_DSI_POWERDOWN,
+	AFTER_DSI_POWERON,
+};
+
+enum MIPITX_PHY_PORT {
+	MIPITX_PHY_PORT_0 = 0,
+	MIPITX_PHY_PORT_1,
+	MIPITX_PHY_PORT_NUM
+};
+
+enum MIPITX_PHY_LANE_SWAP {
+	MIPITX_PHY_LANE_0 = 0,
+	MIPITX_PHY_LANE_1,
+	MIPITX_PHY_LANE_2,
+	MIPITX_PHY_LANE_3,
+	MIPITX_PHY_LANE_CK,
+	MIPITX_PHY_LANE_RX,
+	MIPITX_PHY_LANE_NUM
+};
+
+enum FPS_CHANGE_INDEX {
+	DYNFPS_NOT_DEFINED = 0,
+	DYNFPS_DSI_VFP = 1,
+	DYNFPS_DSI_HFP = 2,
+	DYNFPS_DSI_MIPI_CLK = 4,
+};
+
+struct mtk_panel_dsc_params {
+	unsigned int enable;
+	unsigned int ver; /* [7:4] major [3:0] minor */
+	unsigned int slice_mode;
+	unsigned int rgb_swap;
+	unsigned int dsc_cfg;
+	unsigned int rct_on;
+	unsigned int bit_per_channel;
+	unsigned int dsc_line_buf_depth;
+	unsigned int bp_enable;
+	unsigned int bit_per_pixel;
+	unsigned int pic_height; /* need to check */
+	unsigned int pic_width;  /* need to check */
+	unsigned int slice_height;
+	unsigned int slice_width;
+	unsigned int chunk_size;
+	unsigned int xmit_delay;
+	unsigned int dec_delay;
+	unsigned int scale_value;
+	unsigned int increment_interval;
+	unsigned int decrement_interval;
+	unsigned int line_bpg_offset;
+	unsigned int nfl_bpg_offset;
+	unsigned int slice_bpg_offset;
+	unsigned int initial_offset;
+	unsigned int final_offset;
+	unsigned int flatness_minqp;
+	unsigned int flatness_maxqp;
+	unsigned int rc_model_size;
+	unsigned int rc_edge_factor;
+	unsigned int rc_quant_incr_limit0;
+	unsigned int rc_quant_incr_limit1;
+	unsigned int rc_tgt_offset_hi;
+	unsigned int rc_tgt_offset_lo;
+};
+
+struct mtk_dsi_phy_timcon {
+	unsigned int hs_trail;
+	unsigned int hs_prpr;
+	unsigned int hs_zero;
+	unsigned int lpx;
+	unsigned int ta_get;
+	unsigned int ta_sure;
+	unsigned int ta_go;
+	unsigned int da_hs_exit;
+	unsigned int clk_trail;
+	unsigned int cont_det;
+	unsigned int da_hs_sync;
+	unsigned int clk_zero;
+	unsigned int clk_hs_prpr;
+	unsigned int clk_hs_exit;
+	unsigned int clk_hs_post;
+};
+
+struct dynamic_mipi_params {
+	unsigned int switch_en;
+	unsigned int pll_clk;
+	unsigned int data_rate;
+
+	unsigned int vsa;
+	unsigned int vbp;
+	unsigned int vfp;
+	unsigned int vfp_lp_dyn;
+
+	unsigned int hsa;
+	unsigned int hbp;
+	unsigned int hfp;
+};
+
+struct dfps_switch_cmd {
+	unsigned int src_fps;
+	unsigned int cmd_num;
+	unsigned char para_list[64];
+};
+
+struct dynamic_fps_params {
+	unsigned int switch_en;
+	unsigned int vact_timing_fps;
+	struct dfps_switch_cmd dfps_cmd_table[MAX_DYN_CMD_NUM];
+
+	unsigned int lfr_enable;
+	unsigned int lfr_minimum_fps;
+};
+
+struct mtk_panel_params {
+	unsigned int pll_clk;
+	unsigned int data_rate;
+	struct mtk_dsi_phy_timcon phy_timcon;
+	unsigned int vfp_low_power;
+	struct dynamic_mipi_params dyn;
+	struct dynamic_fps_params dyn_fps;
+	unsigned int cust_esd_check;
+	unsigned int esd_check_enable;
+	struct esd_check_item lcm_esd_check_table[ESD_CHECK_NUM];
+	unsigned int ssc_disable;
+	unsigned int ssc_range;
+	int lcm_color_mode;
+	unsigned int min_luminance;
+	unsigned int average_luminance;
+	unsigned int max_luminance;
+	unsigned int round_corner_en;
+	unsigned int corner_pattern_height;
+	unsigned int corner_pattern_height_bot;
+	unsigned int corner_pattern_tp_size;
+	void *corner_pattern_lt_addr;
+	unsigned int physical_width_um;
+	unsigned int physical_height_um;
+	unsigned int lane_swap_en;
+	unsigned int is_cphy;
+	enum MIPITX_PHY_LANE_SWAP
+		lane_swap[MIPITX_PHY_PORT_NUM][MIPITX_PHY_LANE_NUM];
+	struct mtk_panel_dsc_params dsc_params;
+	unsigned int output_mode;
+	unsigned int hbm_en_time;
+	unsigned int hbm_dis_time;
+	unsigned int lcm_index;
+	unsigned int wait_sof_before_dec_vfp;
+	unsigned int doze_delay;
+};
+
+struct mtk_panel_ext {
+	struct mtk_panel_funcs *funcs;
+	struct mtk_panel_params *params;
+};
+
+struct mtk_panel_ctx {
+	struct drm_panel *panel;
+	struct mtk_panel_ext *ext;
+
+	struct list_head list;
+};
+
+struct mtk_panel_funcs {
+	int (*set_backlight_cmdq)(void *dsi_drv, dcs_write_gce cb,
+		 void *handle, unsigned int level);
+	int (*set_aod_light_mode)(void *dsi_drv, dcs_write_gce cb,
+		 void *handle, unsigned int mode);
+	int (*set_backlight_grp_cmdq)(void *dsi_drv, dcs_grp_write_gce cb,
+		 void *handle, unsigned int level);
+	int (*reset)(struct drm_panel *panel, int on);
+	int (*ata_check)(struct drm_panel *panel);
+	int (*ext_param_set)(struct drm_panel *panel, unsigned int mode);
+	int (*ext_param_get)(struct mtk_panel_params *ext_para,
+		 unsigned int mode);
+	int (*mode_switch)(struct drm_panel *panel, unsigned int cur_mode,
+		 unsigned int dst_mode, enum MTK_PANEL_MODE_SWITCH_STAGE stage);
+	int (*get_virtual_heigh)(void);
+	int (*get_virtual_width)(void);
+	/**
+	 * @doze_enable_start:
+	 *
+	 * Call the @doze_enable_start before starting AOD mode.
+	 * The LCM off may add here to avoid panel show unexpected
+	 * content when switching to specific panel low power mode.
+	 */
+	int (*doze_enable_start)(struct drm_panel *panel,
+		 void *dsi_drv, dcs_write_gce cb, void *handle);
+
+	/**
+	 * @doze_enable:
+	 *
+	 * Call the @doze_enable starts AOD mode.
+	 */
+	int (*doze_enable)(struct drm_panel *panel,
+		 void *dsi_drv, dcs_write_gce cb, void *handle);
+
+	/**
+	 * @doze_disable:
+	 *
+	 * Call the @doze_disable before ending AOD mode.
+	 */
+	int (*doze_disable)(struct drm_panel *panel,
+		 void *dsi_drv, dcs_write_gce cb, void *handle);
+
+	/**
+	 * @doze_post_disp_on:
+	 *
+	 * In some situation, the LCM off may set in @doze_enable & @disable.
+	 * After LCM switch to the new mode stable, system call
+	 * @doze_post_disp_on to turn on panel.
+	 */
+	int (*doze_post_disp_on)(struct drm_panel *panel,
+		 void *dsi_drv, dcs_write_gce cb, void *handle);
+
+	/**
+	 * @doze_area:
+	 *
+	 * Send the panel area in command here.
+	 */
+	int (*doze_area)(struct drm_panel *panel,
+		 void *dsi_drv, dcs_write_gce cb, void *handle);
+
+	/**
+	 * @doze_get_mode_flags:
+	 *
+	 * If CV switch is needed for doze mode, fill the mode_flags in this
+	 * function for both CMD and VDO mode.
+	 */
+	unsigned long (*doze_get_mode_flags)(struct drm_panel *panel,
+				   int aod_en);
+
+	int (*hbm_set_cmdq)(struct drm_panel *panel, void *dsi_drv,
+		 dcs_write_gce cb, void *handle, bool en);
+	void (*hbm_get_state)(struct drm_panel *panel, bool *state);
+	void (*hbm_get_wait_state)(struct drm_panel *panel, bool *wait);
+	bool (*hbm_set_wait_state)(struct drm_panel *panel, bool wait);
+};
+
+void mtk_panel_init(struct mtk_panel_ctx *ctx);
+void mtk_panel_add(struct mtk_panel_ctx *ctx);
+void mtk_panel_remove(struct mtk_panel_ctx *ctx);
+int mtk_panel_attach(struct mtk_panel_ctx *ctx, struct drm_panel *panel);
+int mtk_panel_detach(struct mtk_panel_ctx *ctx);
+struct mtk_panel_ext *find_panel_ext(struct drm_panel *panel);
+int mtk_panel_ext_create(struct device *dev,
+			 struct mtk_panel_params *ext_params,
+			 struct mtk_panel_funcs *ext_funcs,
+			 struct drm_panel *panel);
+int mtk_panel_tch_handle_reg(struct drm_panel *panel);
+void **mtk_panel_tch_handle_init(void);
+int mtk_panel_tch_rst(struct drm_panel *panel);
+
+#endif
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index 47f3d0ea3c6c..73e9e8286d50 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -161,12 +161,30 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
 	}, {
 		DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
 		MT8195_VDO0_OVL_MOUT_EN, MOUT_DISP_OVL1_TO_DISP_RDMA1
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
+		MT8195_VDO0_SEL_IN, SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
+	}, {
+		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+		MT8195_VDO0_SEL_IN, SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
+		MT8195_VDO0_SEL_IN, SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
 	}, {
 		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
 		MT8195_VDO0_SEL_IN, SEL_IN_DSI0_FROM_DISP_DITHER0
+	}, {
+		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+		MT8195_VDO0_SEL_OUT, SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
 	}, {
 		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
 		MT8195_VDO0_SEL_OUT, DDP_COMPONENT_DSI0
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
+		MT8195_VDO0_SEL_OUT, SOUT_DSC_WRAP0_OUT_TO_DSI0
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
+		MT8195_VDO0_SEL_OUT, SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
 	}
 };
 
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 84ece5486902..d74eb3f97f1d 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -285,6 +285,7 @@ static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
 	[DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
 	[DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
+	[DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
 	[DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
 	[DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
 };
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 3135ce82a7f7..89a625743737 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -45,6 +45,9 @@ enum mtk_ddp_comp_id {
 	DDP_COMPONENT_MERGE3,
 	DDP_COMPONENT_MERGE4,
 	DDP_COMPONENT_MERGE5,
+	DDP_COMPONENT_DSC0,
+	DDP_COMPONENT_DSC1,
+	DDP_COMPONENT_DSC1_VIRTUAL0,
 	DDP_COMPONENT_ID_MAX,
 };
 
-- 
2.18.0
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^ permalink raw reply related	[flat|nested] 42+ messages in thread

* Re: [PATCH v1 01/17] dt-bindings: mediatek: add definition for mt8195 display
  2021-07-07  4:12 ` [PATCH v1 01/17] dt-bindings: mediatek: add definition for mt8195 display jason-jh.lin
@ 2021-07-07  4:33   ` CK Hu
  2021-07-10  6:57     ` Jason-JH Lin
  0 siblings, 1 reply; 42+ messages in thread
From: CK Hu @ 2021-07-07  4:33 UTC (permalink / raw)
  To: jason-jh.lin
  Cc: chunkuang.hu, matthias.bgg, linux-arm-kernel, linux-mediatek,
	linux-kernel, devicetree, Project_Global_Chrome_Upstream_Group,
	fshao, nancy.lin, singo.chang

Hi, Jason:


On Wed, 2021-07-07 at 12:12 +0800, jason-jh.lin wrote:
> Add definition for mt8195 display and add DSC module description.

Break this patch to two patch. One is mt8195 display, another one is DSC
and describe more about what is DSC.

Regards,
CK

> 
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
>  .../bindings/display/mediatek/mediatek,disp.txt     | 13 +++++++++++--
>  1 file changed, 11 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> index fbb59c9ddda6..a5859e7883d5 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> @@ -37,6 +37,7 @@ Required properties (all function blocks):
>  	"mediatek,<chip>-disp-aal"   		- adaptive ambient light controller
>  	"mediatek,<chip>-disp-gamma" 		- gamma correction
>  	"mediatek,<chip>-disp-merge" 		- merge streams from two RDMA sources
> +	"mediatek,<chip>-disp-dsc"		- compressing / decompressing image display streams
>  	"mediatek,<chip>-disp-postmask" 	- control round corner for display frame
>  	"mediatek,<chip>-disp-split" 		- split stream to two encoders
>  	"mediatek,<chip>-disp-ufoe"  		- data compression engine
> @@ -44,7 +45,7 @@ Required properties (all function blocks):
>  	"mediatek,<chip>-dpi"        		- DPI controller, see mediatek,dpi.txt
>  	"mediatek,<chip>-disp-mutex" 		- display mutex
>  	"mediatek,<chip>-disp-od"    		- overdrive
> -  the supported chips are mt2701, mt7623, mt2712, mt8167, mt8173, mt8183 and mt8192.
> +  the supported chips are mt2701, mt7623, mt2712, mt8167, mt8173, mt8183, mt8192 and mt8195.
>  - reg: Physical base address and length of the function block register space
>  - interrupts: The interrupt signal from the function block (required, except for
>    merge and split function blocks).
> @@ -60,7 +61,7 @@ Required properties (DMA function blocks):
>  	"mediatek,<chip>-disp-ovl"
>  	"mediatek,<chip>-disp-rdma"
>  	"mediatek,<chip>-disp-wdma"
> -  the supported chips are mt2701, mt8167 and mt8173.
> +  the supported chips are mt2701, mt8167, mt8173 and mt8195.
>  - larb: Should contain a phandle pointing to the local arbiter device as defined
>    in Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
>  - iommus: Should point to the respective IOMMU block with master port as
> @@ -195,6 +196,14 @@ ufoe@1401a000 {
>  	clocks = <&mmsys CLK_MM_DISP_UFOE>;
>  };
>  
> +dsc0@1c009000 {
> +	compatible = "mediatek,mt8195-disp-dsc";
> +	reg = <0 0x1c009000 0 0x1000>;
> +	interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH>;
> +	power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> +	clocks = <&mmsys CLK_VDO0_DSC_WRAP0>;
> +};
> +
>  dsi0: dsi@1401b000 {
>  	/* See mediatek,dsi.txt for details */
>  };

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^ permalink raw reply	[flat|nested] 42+ messages in thread

* Re: [PATCH v1 04/17] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
  2021-07-07  4:12 ` [PATCH v1 04/17] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0 jason-jh.lin
@ 2021-07-07  4:44   ` CK Hu
  2021-07-10  6:58     ` Jason-JH Lin
  0 siblings, 1 reply; 42+ messages in thread
From: CK Hu @ 2021-07-07  4:44 UTC (permalink / raw)
  To: jason-jh.lin
  Cc: chunkuang.hu, matthias.bgg, linux-arm-kernel, linux-mediatek,
	linux-kernel, devicetree, Project_Global_Chrome_Upstream_Group,
	fshao, nancy.lin, singo.chang

Hi, Jason:

On Wed, 2021-07-07 at 12:12 +0800, jason-jh.lin wrote:
> 1. Add mtk-mmsys support for mt8195 vodsys0.
> 2. Change the clock driver of vdosys0 is probed
>    from the probe of mtk-mmsys.

Move clock driver part out of this patch. And ask chun-jie to squash
clock driver modification to his patch [1].

[1]
https://patchwork.kernel.org/project/linux-mediatek/patch/20210616224743.5109-16-chun-jie.chen@mediatek.com/

Regards,
CK

> 
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
>  drivers/clk/mediatek/clk-mt8195-vdo0.c |  24 ++--
>  drivers/soc/mediatek/mt8195-mmsys.h    | 173 +++++++++++++++++++++++++
>  drivers/soc/mediatek/mtk-mmsys.c       |  11 ++
>  3 files changed, 198 insertions(+), 10 deletions(-)
>  create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
> 
> diff --git a/drivers/clk/mediatek/clk-mt8195-vdo0.c b/drivers/clk/mediatek/clk-mt8195-vdo0.c
> index 8e23f267a1e6..940be5377f70 100644
> --- a/drivers/clk/mediatek/clk-mt8195-vdo0.c
> +++ b/drivers/clk/mediatek/clk-mt8195-vdo0.c
> @@ -94,20 +94,24 @@ static const struct mtk_clk_desc vdo0_desc = {
>  	.num_clks = ARRAY_SIZE(vdo0_clks),
>  };
>  
> -static const struct of_device_id of_match_clk_mt8195_vdo0[] = {
> -	{
> -		.compatible = "mediatek,mt8195-vdosys0",
> -		.data = &vdo0_desc,
> -	}, {
> -		/* sentinel */
> -	}
> -};
> +static int clk_mt8195_vdo0_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct device_node *node = dev->parent->of_node;
> +	struct clk_onecell_data *clk_data;
> +
> +	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(vdo0_clks));
> +
> +	mtk_clk_register_gates(node, vdo0_clks, ARRAY_SIZE(vdo0_clks),
> +			clk_data);
> +
> +	return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> +}
>  
>  static struct platform_driver clk_mt8195_vdo0_drv = {
> -	.probe = mtk_clk_simple_probe,
> +	.probe = clk_mt8195_vdo0_probe,
>  	.driver = {
>  		.name = "clk-mt8195-vdo0",
> -		.of_match_table = of_match_clk_mt8195_vdo0,
>  	},
>  };
>  
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> new file mode 100644
> index 000000000000..47f3d0ea3c6c
> --- /dev/null
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -0,0 +1,173 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
> +#define __SOC_MEDIATEK_MT8195_MMSYS_H
> +
> +#define MT8195_VDO0_OVL_MOUT_EN					0xf14
> +#define MOUT_DISP_OVL0_TO_DISP_RDMA0				BIT(0)
> +#define MOUT_DISP_OVL0_TO_DISP_WDMA0				BIT(1)
> +#define MOUT_DISP_OVL0_TO_DISP_OVL1				BIT(2)
> +#define MOUT_DISP_OVL1_TO_DISP_RDMA1				BIT(4)
> +#define MOUT_DISP_OVL1_TO_DISP_WDMA1				BIT(5)
> +#define MOUT_DISP_OVL1_TO_DISP_OVL0				BIT(6)
> +
> +#define MT8195_VDO0_SEL_IN					0xf34
> +#define SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT			(0 << 0)
> +#define SEL_IN_VPP_MERGE_FROM_DISP_DITHER1			(1 << 0)
> +#define SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0			(2 << 0)
> +#define SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0			(0 << 4)
> +#define SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE			(1 << 4)
> +#define SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1			(0 << 5)
> +#define SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE			(1 << 5)
> +#define SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE			(0 << 8)
> +#define SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT			(1 << 8)
> +#define SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT			(0 << 9)
> +#define SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT			(0 << 12)
> +#define SEL_IN_DP_INTF0_FROM_VPP_MERGE				(1 << 12)
> +#define SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0			(2 << 12)
> +#define SEL_IN_DSI0_FROM_DSC_WRAP0_OUT				(0 << 16)
> +#define SEL_IN_DSI0_FROM_DISP_DITHER0				(1 << 16)
> +#define SEL_IN_DSI1_FROM_DSC_WRAP1_OUT				(0 << 17)
> +#define SEL_IN_DSI1_FROM_VPP_MERGE				(1 << 17)
> +#define SEL_IN_DISP_WDMA1_FROM_DISP_OVL1			(0 << 20)
> +#define SEL_IN_DISP_WDMA1_FROM_VPP_MERGE			(1 << 20)
> +#define SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN			(0 << 21)
> +#define SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1			(1 << 21)
> +#define SEL_IN_DISP_WDMA0_FROM_DISP_OVL0			(0 << 22)
> +#define SEL_IN_DISP_WDMA0_FROM_VPP_MERGE			(1 << 22)
> +
> +#define MT8195_VDO0_SEL_OUT					0xf38
> +#define SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN			(0 << 0)
> +#define SOUT_DISP_DITHER0_TO_DSI0				(1 << 0)
> +#define SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN			(0 << 1)
> +#define SOUT_DISP_DITHER1_TO_VPP_MERGE				(1 << 1)
> +#define SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT			(2 << 1)
> +#define SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE				(0 << 4)
> +#define SOUT_VDO1_VIRTUAL0_TO_DP_INTF0				(1 << 4)
> +#define SOUT_VPP_MERGE_TO_DSI1					(0 << 8)
> +#define SOUT_VPP_MERGE_TO_DP_INTF0				(1 << 8)
> +#define SOUT_VPP_MERGE_TO_SINA_VIRTUAL0				(2 << 8)
> +#define SOUT_VPP_MERGE_TO_DISP_WDMA1				(3 << 8)
> +#define SOUT_VPP_MERGE_TO_DSC_WRAP0_IN				(4 << 8)
> +#define SOUT_VPP_MERGE_TO_DSC_WRAP1_IN				(0 << 11)
> +#define SOUT_VPP_MERGE_TO_DISP_WDMA0				(1 << 11)
> +#define SOUT_DSC_WRAP0_OUT_TO_DSI0				(0 << 12)
> +#define SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0			(1 << 12)
> +#define SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE				(2 << 12)
> +#define SOUT_DSC_WRAP1_OUT_TO_DSI1				(0 << 16)
> +#define SOUT_DSC_WRAP1_OUT_TO_DP_INTF0				(1 << 16)
> +#define SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0			(2 << 16)
> +#define SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE				(3 << 16)
> +
> +#define MT8195_VDO1_VPP3_ASYNC_SOUT				0xf54
> +#define SOUT_TO_VPP_MERGE0_P0_SEL				(0 << 0)
> +#define SOUT_TO_VPP_MERGE0_P1_SEL				(1 << 0)
> +
> +#define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL			0xf40
> +#define SOUT_TO_HDR_VDO_FE0					(0 << 0)
> +
> +#define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL			0xf44
> +#define SOUT_TO_HDR_VDO_FE1					(0 << 0)
> +
> +#define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL			0xf48
> +#define SOUT_TO_HDR_GFX_FE0					(0 << 0)
> +
> +#define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL			0xf4c
> +#define SOUT_TO_HDR_GFX_FE1					(0 << 0)
> +
> +#define MT8195_VDO1_MIXER_IN1_SOUT_SEL				0xf58
> +#define MIXER_IN1_SOUT_TO_DISP_MIXER				(0 << 0)
> +
> +#define MT8195_VDO1_MIXER_IN2_SOUT_SEL				0xf5c
> +#define MIXER_IN2_SOUT_TO_DISP_MIXER				(0 << 0)
> +
> +#define MT8195_VDO1_MIXER_IN3_SOUT_SEL				0xf60
> +#define MIXER_IN3_SOUT_TO_DISP_MIXER				(0 << 0)
> +
> +#define MT8195_VDO1_MIXER_IN4_SOUT_SEL				0xf64
> +#define MIXER_IN4_SOUT_TO_DISP_MIXER				(0 << 0)
> +
> +#define MT8195_VDO1_MIXER_OUT_SOUT_SEL				0xf34
> +#define MIXER_SOUT_TO_HDR_VDO_BE0				(0 << 0)
> +
> +#define MT8195_VDO1_MERGE4_SOUT_SEL				0xf18
> +#define MERGE4_SOUT_TO_VDOSYS0					(0 << 0)
> +#define MERGE4_SOUT_TO_DPI0_SEL					(1 << 0)
> +#define MERGE4_SOUT_TO_DPI1_SEL					(2 << 0)
> +#define MERGE4_SOUT_TO_DP_INTF0_SEL				(3 << 0)
> +
> +#define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN			0xf04
> +#define VPP_MERGE0_P0_SEL_IN_FROM_SVPP2				(0 << 0)
> +#define VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0			(1 << 0)
> +
> +#define MT8195_VDO1_VPP_MERGE0_P1_SEL_IN			0xf08
> +#define VPP_MERGE0_P1_SEL_IN_FROM_SVPP3				(0 << 0)
> +#define VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1			(1 << 0)
> +
> +#define MT8195_VDO1_VPP_MERGE1_P0_SEL_IN			0xf3c
> +#define VPP_MERGE1_P0_SEL_IN_FROM_VPP3_ASYNC_SOUT		(0 << 0)
> +#define VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2			(1 << 0)
> +
> +#define MT8195_VDO1_MIXER_IN1_SEL_IN				0xf24
> +#define MIXER_IN1_SEL_IN_FROM_HDR_VDO_FE0			(0 << 0)
> +#define MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT			(1 << 0)
> +
> +#define MT8195_VDO1_MIXER_IN2_SEL_IN				0xf28
> +#define MIXER_IN2_SEL_IN_FROM_HDR_VDO_FE1			(0 << 0)
> +#define MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT			(1 << 0)
> +
> +#define MT8195_VDO1_MIXER_IN3_SEL_IN				0xf2c
> +#define MIXER_IN3_SEL_IN_FROM_HDR_GFX_FE0			(0 << 0)
> +#define MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT			(1 << 0)
> +
> +#define MT8195_VDO1_MIXER_IN4_SEL_IN				0xf30
> +#define MIXER_IN4_SEL_IN_FROM_HDR_GFX_FE1			(0 << 0)
> +#define MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT			(1 << 0)
> +
> +#define MT8195_VDO1_MIXER_SOUT_SEL_IN				0xf68
> +#define MIXER_SOUT_SEL_IN_FROM_DISP_MIXER			(0 << 0)
> +#define MIXER_SOUT_SEL_IN_FROM_MIXER_IN1_SOUT			(1 << 0)
> +#define MIXER_SOUT_SEL_IN_FROM_MIXER_IN2_SOUT			(2 << 0)
> +#define MIXER_SOUT_SEL_IN_FROM_MIXER_IN3_SOUTR			(3 << 0)
> +#define MIXER_SOUT_SEL_IN_FROM_MIXER_IN4_SOUTR			(4 << 0)
> +
> +#define MT8195_VDO1_MERGE4_ASYNC_SEL_IN				0xf50
> +#define MERGE4_ASYNC_SEL_IN_FROM_HDR_VDO_BE0			(0 << 0)
> +#define MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT			(1 << 0)
> +#define MERGE4_ASYNC_SEL_IN_FROM_MERGE0_ASYNC_SOUT		(2 << 0)
> +#define MERGE4_ASYNC_SEL_IN_FROM_MERGE1_ASYNC_SOUT		(3 << 0)
> +#define MERGE4_ASYNC_SEL_IN_FROM_MERGE2_ASYNC_SOUT		(4 << 0)
> +#define MERGE4_ASYNC_SEL_IN_FROM_MERGE3_ASYNC_SOUT		(5 << 0)
> +
> +#define MT8195_VDO1_DISP_DPI0_SEL_IN				0xf0c
> +#define DISP_DPI0_SEL_IN_FROM_VPP_MERGE4_MOUT			(0 << 0)
> +#define DISP_DPI0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT		(1 << 0)
> +#define DISP_DPI0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT		(2 << 0)
> +
> +#define MT8195_VDO1_DISP_DPI1_SEL_IN				0xf10
> +#define DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT			(0 << 0)
> +#define DISP_DPI1_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT		(1 << 0)
> +#define DISP_DPI1_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT		(2 << 0)
> +
> +#define MT8195_VDO1_DISP_DP_INTF0_SEL_IN			0xf14
> +#define DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT		(0 << 0)
> +#define DISP_DP_INTF0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT	(1 << 0)
> +#define DISP_DP_INTF0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT	(2 << 0)
> +
> +static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
> +	{
> +		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> +		MT8195_VDO0_OVL_MOUT_EN, MOUT_DISP_OVL0_TO_DISP_RDMA0
> +	}, {
> +		DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
> +		MT8195_VDO0_OVL_MOUT_EN, MOUT_DISP_OVL1_TO_DISP_RDMA1
> +	}, {
> +		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> +		MT8195_VDO0_SEL_IN, SEL_IN_DSI0_FROM_DISP_DITHER0
> +	}, {
> +		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> +		MT8195_VDO0_SEL_OUT, DDP_COMPONENT_DSI0
> +	}
> +};
> +
> +#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index 080660ef11bf..1fb241750897 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -13,6 +13,7 @@
>  #include "mtk-mmsys.h"
>  #include "mt8167-mmsys.h"
>  #include "mt8183-mmsys.h"
> +#include "mt8195-mmsys.h"
>  
>  static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
>  	.clk_driver = "clk-mt2701-mm",
> @@ -52,6 +53,12 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
>  	.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
>  };
>  
> +static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
> +	.clk_driver = "clk-mt8195-vdo0",
> +	.routes = mmsys_mt8195_routing_table,
> +	.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> +};
> +
>  struct mtk_mmsys {
>  	void __iomem *regs;
>  	const struct mtk_mmsys_driver_data *data;
> @@ -157,6 +164,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
>  		.compatible = "mediatek,mt8183-mmsys",
>  		.data = &mt8183_mmsys_driver_data,
>  	},
> +	{
> +		.compatible = "mediatek,mt8195-vdosys0",
> +		.data = &mt8195_vdosys0_driver_data,
> +	},
>  	{ }
>  };
>  

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^ permalink raw reply	[flat|nested] 42+ messages in thread

* Re: [PATCH v1 05/17] drm/mediatek: add mediatek-drm of vdosys0 support for MT8195
  2021-07-07  4:12 ` [PATCH v1 05/17] drm/mediatek: add mediatek-drm of vdosys0 support for MT8195 jason-jh.lin
@ 2021-07-07  4:48   ` CK Hu
  2021-07-10  6:59     ` Jason-JH Lin
  0 siblings, 1 reply; 42+ messages in thread
From: CK Hu @ 2021-07-07  4:48 UTC (permalink / raw)
  To: jason-jh.lin
  Cc: chunkuang.hu, matthias.bgg, linux-arm-kernel, linux-mediatek,
	linux-kernel, devicetree, Project_Global_Chrome_Upstream_Group,
	fshao, nancy.lin, singo.chang

Hi, Jason:

On Wed, 2021-07-07 at 12:12 +0800, jason-jh.lin wrote:
> Add mediatek-drm of vdosys0 support for MT8195.
> 
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c | 24 ++++++++++++++++++++++++
>  1 file changed, 24 insertions(+)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index b46bdb8985da..9074ce32912c 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -147,6 +147,23 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = {
>  	DDP_COMPONENT_DPI0,
>  };
>  
> +static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
> +	DDP_COMPONENT_OVL0,
> +	DDP_COMPONENT_RDMA0,
> +	DDP_COMPONENT_COLOR0,
> +	DDP_COMPONENT_CCORR,
> +	DDP_COMPONENT_AAL0,
> +	DDP_COMPONENT_GAMMA,
> +	DDP_COMPONENT_DITHER,
> +#ifdef CONFIG_MTK_DPTX_SUPPORT
> +	DDP_COMPONENT_DSC0,
> +	DDP_COMPONENT_MERGE0,
> +	DDP_COMPONENT_DP_INTF0,
> +#else

CONFIG_MTK_DPTX_SUPPORT is not defined, so remove this part.

Regards,
CK

> +	DDP_COMPONENT_DSI0,
> +#endif
> +};
> +
>  static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
>  	.main_path = mt2701_mtk_ddp_main,
>  	.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
> @@ -186,6 +203,11 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
>  	.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
>  };
>  
> +static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
> +	.main_path = mt8195_mtk_ddp_main,
> +	.main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
> +};
> +
>  static int mtk_drm_kms_init(struct drm_device *drm)
>  {
>  	struct mtk_drm_private *private = drm->dev_private;
> @@ -468,6 +490,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
>  	  .data = &mt8173_mmsys_driver_data},
>  	{ .compatible = "mediatek,mt8183-mmsys",
>  	  .data = &mt8183_mmsys_driver_data},
> +	{.compatible = "mediatek,mt8195-vdosys0",
> +	  .data = &mt8195_vdosys0_driver_data},
>  	{ }
>  };
>  MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);

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^ permalink raw reply	[flat|nested] 42+ messages in thread

* Re: [PATCH v1 06/17] soc: mediatek: add mtk-mutex support for mt8195
  2021-07-07  4:12 ` [PATCH v1 06/17] soc: mediatek: add mtk-mutex support for mt8195 jason-jh.lin
@ 2021-07-07  4:52   ` CK Hu
  2021-07-10  7:01     ` Jason-JH Lin
  0 siblings, 1 reply; 42+ messages in thread
From: CK Hu @ 2021-07-07  4:52 UTC (permalink / raw)
  To: jason-jh.lin
  Cc: chunkuang.hu, matthias.bgg, linux-arm-kernel, linux-mediatek,
	linux-kernel, devicetree, Project_Global_Chrome_Upstream_Group,
	fshao, nancy.lin, singo.chang

Hi, Jason:

On Wed, 2021-07-07 at 12:12 +0800, jason-jh.lin wrote:
> Add mtk-mutex support for mt8195.

Separate DRM part and SoC part into different patch.

Regards,
CK

> 
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c |   2 +
>  drivers/soc/mediatek/mtk-mutex.c       | 105 +++++++++++++++++++++++--
>  2 files changed, 102 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 9074ce32912c..5b7ead493487 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -470,6 +470,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
>  	  .data = (void *)MTK_DISP_MUTEX },
>  	{ .compatible = "mediatek,mt8183-disp-mutex",
>  	  .data = (void *)MTK_DISP_MUTEX },
> +	{ .compatible = "mediatek,mt8195-disp-mutex",
> +	  .data = (void *)MTK_DISP_MUTEX },
>  	{ .compatible = "mediatek,mt2701-disp-pwm",
>  	  .data = (void *)MTK_DISP_BLS },
>  	{ .compatible = "mediatek,mt8173-disp-pwm",
> diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
> index 2e4bcc300576..080bdabfb024 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -17,6 +17,9 @@
>  #define MT8183_MUTEX0_MOD0			0x30
>  #define MT8183_MUTEX0_SOF0			0x2c
>  
> +#define MT8195_DISP_MUTEX0_MOD0			0x30
> +#define MT8195_DISP_MUTEX0_SOF			0x2c
> +
>  #define DISP_REG_MUTEX_EN(n)			(0x20 + 0x20 * (n))
>  #define DISP_REG_MUTEX(n)			(0x24 + 0x20 * (n))
>  #define DISP_REG_MUTEX_RST(n)			(0x28 + 0x20 * (n))
> @@ -67,6 +70,36 @@
>  #define MT8173_MUTEX_MOD_DISP_PWM1		24
>  #define MT8173_MUTEX_MOD_DISP_OD		25
>  
> +#define MT8195_MUTEX_MOD_DISP_OVL0		0
> +#define MT8195_MUTEX_MOD_DISP_WDMA0		1
> +#define MT8195_MUTEX_MOD_DISP_RDMA0		2
> +#define MT8195_MUTEX_MOD_DISP_COLOR0		3
> +#define MT8195_MUTEX_MOD_DISP_CCORR0		4
> +#define MT8195_MUTEX_MOD_DISP_AAL0		5
> +#define MT8195_MUTEX_MOD_DISP_GAMMA0		6
> +#define MT8195_MUTEX_MOD_DISP_DITHER0		7
> +#define MT8195_MUTEX_MOD_DISP_DSI0		8
> +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0	9
> +#define MT8195_MUTEX_MOD_DISP_OVL1		10
> +#define MT8195_MUTEX_MOD_DISP_WDMA1		11
> +#define MT8195_MUTEX_MOD_DISP_RDMA1		12
> +#define MT8195_MUTEX_MOD_DISP_COLOR1		13
> +#define MT8195_MUTEX_MOD_DISP_CCORR1		14
> +#define MT8195_MUTEX_MOD_DISP_AAL1		15
> +#define MT8195_MUTEX_MOD_DISP_GAMMA1		16
> +#define MT8195_MUTEX_MOD_DISP_DITHER1		17
> +#define MT8195_MUTEX_MOD_DISP_DSI1		18
> +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1	19
> +#define MT8195_MUTEX_MOD_DISP_VPP_MERGE		20
> +#define MT8195_MUTEX_MOD_DISP_DP_INTF0		21
> +#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0	22
> +#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1	23
> +#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2	24
> +#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3	25
> +#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4	26
> +#define MT8195_MUTEX_MOD_DISP_PWM0		27
> +#define MT8195_MUTEX_MOD_DISP_PWM1		28
> +
>  #define MT2712_MUTEX_MOD_DISP_PWM2		10
>  #define MT2712_MUTEX_MOD_DISP_OVL0		11
>  #define MT2712_MUTEX_MOD_DISP_OVL1		12
> @@ -101,11 +134,36 @@
>  #define MT2712_MUTEX_SOF_DSI3			6
>  #define MT8167_MUTEX_SOF_DPI0			2
>  #define MT8167_MUTEX_SOF_DPI1			3
> +
>  #define MT8183_MUTEX_SOF_DSI0			1
>  #define MT8183_MUTEX_SOF_DPI0			2
>  
> -#define MT8183_MUTEX_EOF_DSI0			(MT8183_MUTEX_SOF_DSI0 << 6)
> -#define MT8183_MUTEX_EOF_DPI0			(MT8183_MUTEX_SOF_DPI0 << 6)
> +#define MT8183_MUTEX_EOF_CONVERT(sof)	((sof) << 6)
> +#define MT8183_MUTEX_EOF_DSI0 \
> +	MT8183_MUTEX_EOF_CONVERT(MT8183_MUTEX_SOF_DSI0)
> +#define MT8183_MUTEX_EOF_DPI0 \
> +	MT8183_MUTEX_EOF_CONVERT(MT8183_MUTEX_SOF_DPI0)
> +
> +#define MT8195_MUTEX_SOF_DSI0			1
> +#define MT8195_MUTEX_SOF_DSI1			2
> +#define MT8195_MUTEX_SOF_DP_INTF0		3
> +#define MT8195_MUTEX_SOF_DP_INTF1		4
> +#define MT8195_MUTEX_SOF_DPI0			6 /* for HDMI_TX */
> +#define MT8195_MUTEX_SOF_DPI1			5 /* for digital video out */
> +
> +#define MT8195_MUTEX_EOF_CONVERT(sof)	((sof) << 7)
> +#define MT8195_MUTEX_EOF_DSI0 \
> +	MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DSI0)
> +#define MT8195_MUTEX_EOF_DSI1 \
> +	MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DSI1)
> +#define MT8195_MUTEX_EOF_DP_INTF0 \
> +	MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DP_INTF0)
> +#define MT8195_MUTEX_EOF_DP_INTF1 \
> +	MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DP_INTF1)
> +#define MT8195_MUTEX_EOF_DPI0 \
> +	MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DPI0)
> +#define MT8195_MUTEX_EOF_DPI1 \
> +	MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DPI1)
>  
>  struct mtk_mutex {
>  	int id;
> @@ -120,6 +178,9 @@ enum mtk_mutex_sof_id {
>  	MUTEX_SOF_DPI1,
>  	MUTEX_SOF_DSI2,
>  	MUTEX_SOF_DSI3,
> +	MUTEX_SOF_DP_INTF0,
> +	MUTEX_SOF_DP_INTF1,
> +	DDP_MUTEX_SOF_MAX,
>  };
>  
>  struct mtk_mutex_data {
> @@ -214,7 +275,20 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
>  	[DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
>  };
>  
> -static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> +static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> +	[DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
> +	[DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
> +	[DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
> +	[DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0,
> +	[DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
> +	[DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
> +	[DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
> +	[DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
> +	[DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
> +	[DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
> +};
> +
> +static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
>  	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
>  	[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
>  	[MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
> @@ -224,7 +298,7 @@ static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
>  	[MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
>  };
>  
> -static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> +static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = {
>  	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
>  	[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
>  	[MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
> @@ -232,12 +306,24 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
>  };
>  
>  /* Add EOF setting so overlay hardware can receive frame done irq */
> -static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = {
>  	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
>  	[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
>  	[MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
>  };
>  
> +static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> +	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> +	[MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0,
> +	[MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1,
> +	[MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0,
> +	[MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1,
> +	[MUTEX_SOF_DP_INTF0] =
> +		MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0,
> +	[MUTEX_SOF_DP_INTF1] =
> +		MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1,
> +};
> +
>  static const struct mtk_mutex_data mt2701_mutex_driver_data = {
>  	.mutex_mod = mt2701_mutex_mod,
>  	.mutex_sof = mt2712_mutex_sof,
> @@ -275,6 +361,13 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = {
>  	.no_clk = true,
>  };
>  
> +static const struct mtk_mutex_data mt8195_mutex_driver_data = {
> +	.mutex_mod = mt8195_mutex_mod,
> +	.mutex_sof = mt8195_mutex_sof,
> +	.mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
> +	.mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
> +};
> +
>  struct mtk_mutex *mtk_mutex_get(struct device *dev)
>  {
>  	struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
> @@ -507,6 +600,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
>  	  .data = &mt8173_mutex_driver_data},
>  	{ .compatible = "mediatek,mt8183-disp-mutex",
>  	  .data = &mt8183_mutex_driver_data},
> +	{ .compatible = "mediatek,mt8195-disp-mutex",
> +	  .data = &mt8195_mutex_driver_data},
>  	{},
>  };
>  MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);

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^ permalink raw reply	[flat|nested] 42+ messages in thread

* Re: [PATCH v1 07/17] drm/mediatek: add OVL support for MT8195
  2021-07-07  4:12 ` [PATCH v1 07/17] drm/mediatek: add OVL support for MT8195 jason-jh.lin
@ 2021-07-07  5:03   ` CK Hu
  2021-07-10  7:05     ` Jason-JH Lin
  0 siblings, 1 reply; 42+ messages in thread
From: CK Hu @ 2021-07-07  5:03 UTC (permalink / raw)
  To: jason-jh.lin
  Cc: chunkuang.hu, matthias.bgg, linux-arm-kernel, linux-mediatek,
	linux-kernel, devicetree, Project_Global_Chrome_Upstream_Group,
	fshao, nancy.lin, singo.chang

Hi, Jason:

On Wed, 2021-07-07 at 12:12 +0800, jason-jh.lin wrote:
> Add OVL support for MT8195.
> 
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 9 +++++++++
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c  | 2 ++
>  2 files changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index 961f87f8d4d1..99c39487026d 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -455,6 +455,13 @@ static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = {
>  	.fmt_rgb565_is_0 = true,
>  };
>  
> +static const struct mtk_disp_ovl_data mt8195_ovl_driver_data = {
> +	.addr = DISP_REG_OVL_ADDR_MT8173,
> +	.gmc_bits = 10,
> +	.layer_nr = 4,
> +	.fmt_rgb565_is_0 = true,
> +};

mt8195_ovl_driver_data is identical to mt8183_ovl_driver_data, so remove
mt8195_ovl_driver_data and use mt8183_ovl_driver_data.

> +
>  static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
>  	{ .compatible = "mediatek,mt2701-disp-ovl",
>  	  .data = &mt2701_ovl_driver_data},
> @@ -464,6 +471,8 @@ static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
>  	  .data = &mt8183_ovl_driver_data},
>  	{ .compatible = "mediatek,mt8183-disp-ovl-2l",
>  	  .data = &mt8183_ovl_2l_driver_data},
> +	{ .compatible = "mediatek,mt8195-disp-ovl",
> +	  .data = &mt8195_ovl_driver_data},

One question, is mediatek,mt8195-disp-ovl identical to
mediatek,mt8183-disp-ovl in hardware function? If so, use the compatible
as

compatible = "mediatek,mt8195-disp-ovl", "mediatek,mt8183-disp-ovl";

And driver just keep "mediatek,mt8183-disp-ovl" and remove
"mediatek,mt8195-disp-ovl".

If the hardware function has some different, just forget this.

Regards,
CK

>  	{},
>  };
>  MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match);
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 5b7ead493487..65038d5b19cb 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -424,6 +424,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
>  	  .data = (void *)MTK_DISP_OVL },
>  	{ .compatible = "mediatek,mt8183-disp-ovl",
>  	  .data = (void *)MTK_DISP_OVL },
> +	{ .compatible = "mediatek,mt8195-disp-ovl",
> +	  .data = (void *)MTK_DISP_OVL },
>  	{ .compatible = "mediatek,mt8183-disp-ovl-2l",
>  	  .data = (void *)MTK_DISP_OVL_2L },
>  	{ .compatible = "mediatek,mt2701-disp-rdma",

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^ permalink raw reply	[flat|nested] 42+ messages in thread

* Re: [PATCH v1 08/17] drm/mediatek: Add component_del in OVL remove function
  2021-07-07  4:12 ` [PATCH v1 08/17] drm/mediatek: Add component_del in OVL remove function jason-jh.lin
@ 2021-07-07  5:12   ` CK Hu
  2021-07-10  7:06     ` Jason-JH Lin
  0 siblings, 1 reply; 42+ messages in thread
From: CK Hu @ 2021-07-07  5:12 UTC (permalink / raw)
  To: jason-jh.lin
  Cc: chunkuang.hu, matthias.bgg, linux-arm-kernel, linux-mediatek,
	linux-kernel, devicetree, Project_Global_Chrome_Upstream_Group,
	fshao, nancy.lin, singo.chang

Hi, Jason:

On Wed, 2021-07-07 at 12:12 +0800, jason-jh.lin wrote:
> Add component_del in OVL remove function.
> 
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index 99c39487026d..7504e86b167a 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -158,7 +158,6 @@ void mtk_ovl_stop(struct device *dev)
>  		reg = reg & ~OVL_LAYER_SMI_ID_EN;
>  		writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
>  	}
> -

This modification is not related to this patch, so move out of this
patch.

>  }
>  
>  void mtk_ovl_config(struct device *dev, unsigned int w,
> @@ -424,6 +423,8 @@ static int mtk_disp_ovl_probe(struct platform_device *pdev)
>  
>  static int mtk_disp_ovl_remove(struct platform_device *pdev)
>  {
> +	component_del(&pdev->dev, &mtk_disp_ovl_component_ops);
> +

This is a fix-up of patch [1]. Change this patch to fix all sub drivers,
add Fixes tag, and move this patch out of this series. (This fix-up is
not related to mt8195, so send this patch independently).

[1]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?h=v5.13&id=ff1395609e20c1cd98b3ec65d16dc18f0471dca3

Regards,
CK

>  	return 0;
>  }
>  

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^ permalink raw reply	[flat|nested] 42+ messages in thread

* Re: [PATCH v1 09/17] drm/mediatek: add OVL support multi-layer
  2021-07-07  4:12 ` [PATCH v1 09/17] drm/mediatek: add OVL support multi-layer jason-jh.lin
@ 2021-07-07  5:43   ` CK Hu
  2021-07-10  7:17     ` Jason-JH Lin
  0 siblings, 1 reply; 42+ messages in thread
From: CK Hu @ 2021-07-07  5:43 UTC (permalink / raw)
  To: jason-jh.lin
  Cc: chunkuang.hu, matthias.bgg, linux-arm-kernel, linux-mediatek,
	linux-kernel, devicetree, Project_Global_Chrome_Upstream_Group,
	fshao, nancy.lin, singo.chang

Hi, Jason:

On Wed, 2021-07-07 at 12:12 +0800, jason-jh.lin wrote:
> Add datapath_con settings to support multi-layer output.


What is multi-layer output? Why we need this?

> 
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 15 ++++++++++++---
>  1 file changed, 12 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index 7504e86b167a..95fd5e00eb91 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -18,14 +18,17 @@
>  #include "mtk_drm_ddp_comp.h"
>  
>  #define DISP_REG_OVL_INTEN			0x0004
> -#define OVL_FME_CPL_INT					BIT(1)
> +#define OVL_FME_CPL_INT				BIT(1)
>  #define DISP_REG_OVL_INTSTA			0x0008
>  #define DISP_REG_OVL_EN				0x000c
>  #define DISP_REG_OVL_RST			0x0014
>  #define DISP_REG_OVL_ROI_SIZE			0x0020
>  #define DISP_REG_OVL_DATAPATH_CON		0x0024
> -#define OVL_LAYER_SMI_ID_EN				BIT(0)
> -#define OVL_BGCLR_SEL_IN				BIT(2)
> +#define OVL_LAYER_SMI_ID_EN			BIT(0)
> +#define OVL_BGCLR_SEL_IN			BIT(2)
> +#define OVL_GCLAST_EN				BIT(24)
> +#define OVL_HDR_GCLAST_EN			BIT(25)
> +#define OVL_OUTPUT_CLAMP			BIT(26)
>  #define DISP_REG_OVL_ROI_BGCLR			0x0028
>  #define DISP_REG_OVL_SRC_CON			0x002c
>  #define DISP_REG_OVL_CON(n)			(0x0030 + 0x20 * (n))
> @@ -222,6 +225,7 @@ void mtk_ovl_layer_on(struct device *dev, unsigned int idx,
>  	unsigned int gmc_thrshd_l;
>  	unsigned int gmc_thrshd_h;
>  	unsigned int gmc_value;
> +	unsigned int datapatch_con;
>  	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
>  
>  	mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs,
> @@ -237,6 +241,11 @@ void mtk_ovl_layer_on(struct device *dev, unsigned int idx,
>  			    gmc_thrshd_h << 16 | gmc_thrshd_h << 24;
>  	mtk_ddp_write(cmdq_pkt, gmc_value,
>  		      &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RDMA_GMC(idx));
> +
> +	datapatch_con = OVL_GCLAST_EN | OVL_HDR_GCLAST_EN | OVL_OUTPUT_CLAMP;
> +	mtk_ddp_write_mask(cmdq_pkt, datapatch_con, &ovl->cmdq_reg, ovl->regs,
> +				 DISP_REG_OVL_DATAPATH_CON, datapatch_con);

For mt8173 or other SoC, this does not turn on. Now you turn on this,
would this influence other SoC?

Regards,
CK

> +
>  	mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &ovl->cmdq_reg, ovl->regs,
>  			   DISP_REG_OVL_SRC_CON, BIT(idx));
>  }

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^ permalink raw reply	[flat|nested] 42+ messages in thread

* Re: [PATCH v1 11/17] drm/mediatek: add COLOR support for MT8195
  2021-07-07  4:12 ` [PATCH v1 11/17] drm/mediatek: add COLOR " jason-jh.lin
@ 2021-07-07  6:01   ` CK Hu
  2021-07-10  7:21     ` Jason-JH Lin
  0 siblings, 1 reply; 42+ messages in thread
From: CK Hu @ 2021-07-07  6:01 UTC (permalink / raw)
  To: jason-jh.lin
  Cc: chunkuang.hu, matthias.bgg, linux-arm-kernel, linux-mediatek,
	linux-kernel, devicetree, Project_Global_Chrome_Upstream_Group,
	fshao, nancy.lin, singo.chang

Hi, Jason:

On Wed, 2021-07-07 at 12:12 +0800, jason-jh.lin wrote:
> Add COLOR support for MT8195.
> 
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_disp_color.c | 6 ++++++
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c    | 2 ++
>  2 files changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_color.c b/drivers/gpu/drm/mediatek/mtk_disp_color.c
> index 63f411ab393b..ce2cf9f504cc 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_color.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_color.c
> @@ -149,6 +149,10 @@ static const struct mtk_disp_color_data mt8173_color_driver_data = {
>  	.color_offset = DISP_COLOR_START_MT8173,
>  };
>  
> +static const struct mtk_disp_color_data mt8195_color_driver_data = {
> +	.color_offset = DISP_COLOR_START_MT8173,
> +};

mt8195_color_driver_data is identical to mt8173_color_driver_data, so
use mt8173_color_driver_data and remove mt8195_color_driver_data.

> +
>  static const struct of_device_id mtk_disp_color_driver_dt_match[] = {
>  	{ .compatible = "mediatek,mt2701-disp-color",
>  	  .data = &mt2701_color_driver_data},
> @@ -156,6 +160,8 @@ static const struct of_device_id mtk_disp_color_driver_dt_match[] = {
>  	  .data = &mt8167_color_driver_data},
>  	{ .compatible = "mediatek,mt8173-disp-color",
>  	  .data = &mt8173_color_driver_data},
> +	{ .compatible = "mediatek,mt8195-disp-color",
> +	  .data = &mt8195_color_driver_data},
>  	{},
>  };
>  MODULE_DEVICE_TABLE(of, mtk_disp_color_driver_dt_match);
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 8b24623dcd91..28bf4a11efb0 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -444,6 +444,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
>  	  .data = (void *)MTK_DISP_COLOR },
>  	{ .compatible = "mediatek,mt8173-disp-color",
>  	  .data = (void *)MTK_DISP_COLOR },
> +	{ .compatible = "mediatek,mt8195-disp-color",
> +	  .data = (void *)MTK_DISP_COLOR },

Is mediatek,mt8195-disp-color identical to
mediatek,mt8173-disp-color in hardware function? If so, use the
compatible
as

compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color";

And driver just keep "mediatek,mt8173-disp-color" and remove
"mediatek,mt8195-disp-color".

If the hardware function has some different, just forget this.

Regards,
CK

>  	{ .compatible = "mediatek,mt8173-disp-aal",
>  	  .data = (void *)MTK_DISP_AAL},
>  	{ .compatible = "mediatek,mt8173-disp-gamma",

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^ permalink raw reply	[flat|nested] 42+ messages in thread

* Re: [PATCH v1 12/17] drm/mediatek: add CCORR support for MT8195
  2021-07-07  4:12 ` [PATCH v1 12/17] drm/mediatek: add CCORR " jason-jh.lin
@ 2021-07-07  6:02   ` CK Hu
  2021-07-10  7:22     ` Jason-JH Lin
  0 siblings, 1 reply; 42+ messages in thread
From: CK Hu @ 2021-07-07  6:02 UTC (permalink / raw)
  To: jason-jh.lin
  Cc: chunkuang.hu, matthias.bgg, linux-arm-kernel, linux-mediatek,
	linux-kernel, devicetree, Project_Global_Chrome_Upstream_Group,
	fshao, nancy.lin, singo.chang

Hi, Jason:

On Wed, 2021-07-07 at 12:12 +0800, jason-jh.lin wrote:
> Add CCORR support for MT8195.
> 
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 2 ++
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c    | 2 ++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> index 141cb36b9c07..8188b220cc6d 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> @@ -208,6 +208,8 @@ static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = {
>  static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = {
>  	{ .compatible = "mediatek,mt8183-disp-ccorr",
>  	  .data = &mt8183_ccorr_driver_data},
> +	{ .compatible = "mediatek,mt8195-disp-ccorr",
> +	  .data = &mt8183_ccorr_driver_data},
>  	{},
>  };
>  MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match);
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 28bf4a11efb0..058b50d0e64b 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -440,6 +440,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
>  	  .data = (void *)MTK_DISP_WDMA },
>  	{ .compatible = "mediatek,mt8183-disp-ccorr",
>  	  .data = (void *)MTK_DISP_CCORR },
> +	{ .compatible = "mediatek,mt8195-disp-ccorr",
> +	  .data = (void *)MTK_DISP_CCORR },

The same question as OVL and COLOR.

Regards,
CK

>  	{ .compatible = "mediatek,mt2701-disp-color",
>  	  .data = (void *)MTK_DISP_COLOR },
>  	{ .compatible = "mediatek,mt8173-disp-color",

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^ permalink raw reply	[flat|nested] 42+ messages in thread

* Re: [PATCH v1 13/17] drm/mediatek: Add AAL support for MT8195
  2021-07-07  4:12 ` [PATCH v1 13/17] drm/mediatek: Add AAL " jason-jh.lin
@ 2021-07-07  6:14   ` CK Hu
  2021-07-10  7:35     ` Jason-JH Lin
  0 siblings, 1 reply; 42+ messages in thread
From: CK Hu @ 2021-07-07  6:14 UTC (permalink / raw)
  To: jason-jh.lin
  Cc: chunkuang.hu, matthias.bgg, linux-arm-kernel, linux-mediatek,
	linux-kernel, devicetree, Project_Global_Chrome_Upstream_Group,
	fshao, nancy.lin, singo.chang

Hi, Jason:

On Wed, 2021-07-07 at 12:12 +0800, jason-jh.lin wrote:
> 1. Add AAL support for MT8195.
> 2. Add AAL_OUTPUT_SIZE configuration.
> 
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 8 +++++++-
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c      | 2 ++
>  2 files changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 75bc00e17fc4..f154f7c0cd11 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -34,6 +34,7 @@
>  
>  #define DISP_AAL_EN				0x0000
>  #define DISP_AAL_SIZE				0x0030
> +#define DISP_AAL_OUTPUT_SIZE			0x04d8
>  
>  #define DISP_DITHER_EN				0x0000
>  #define DITHER_EN				BIT(0)
> @@ -196,7 +197,12 @@ static void mtk_aal_config(struct device *dev, unsigned int w,
>  {
>  	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>  
> -	mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_AAL_SIZE);
> +	mtk_ddp_write(cmdq_pkt, w << 16 | h,
> +				&priv->cmdq_reg, priv->regs,
> +				DISP_AAL_SIZE);

Why do you change this?

> +	mtk_ddp_write(cmdq_pkt, w << 16 | h,
> +				&priv->cmdq_reg, priv->regs,
> +				DISP_AAL_OUTPUT_SIZE);

This seems not related to mt8195, so move this modification to another
patch.

>  }
>  
>  static void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state)
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 058b50d0e64b..459bb1e53f2e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -450,6 +450,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
>  	  .data = (void *)MTK_DISP_COLOR },
>  	{ .compatible = "mediatek,mt8173-disp-aal",
>  	  .data = (void *)MTK_DISP_AAL},
> +	{ .compatible = "mediatek,mt8195-disp-aal",
> +	  .data = (void *)MTK_DISP_AAL},

The same question for OVL, COLOR, CCORR.

Regards,
CK

>  	{ .compatible = "mediatek,mt8173-disp-gamma",
>  	  .data = (void *)MTK_DISP_GAMMA, },
>  	{ .compatible = "mediatek,mt8183-disp-gamma",

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^ permalink raw reply	[flat|nested] 42+ messages in thread

* Re: [PATCH v1 16/17] drm/mediatek: add MERGE support for MT8195
  2021-07-07  4:12 ` [PATCH v1 16/17] drm/mediatek: add MERGE " jason-jh.lin
@ 2021-07-07  7:02   ` CK Hu
  2021-07-10  7:52     ` Jason-JH Lin
  0 siblings, 1 reply; 42+ messages in thread
From: CK Hu @ 2021-07-07  7:02 UTC (permalink / raw)
  To: jason-jh.lin
  Cc: chunkuang.hu, matthias.bgg, linux-arm-kernel, linux-mediatek,
	linux-kernel, devicetree, Project_Global_Chrome_Upstream_Group,
	fshao, nancy.lin, singo.chang

Hi, Jason:

On Wed, 2021-07-07 at 12:12 +0800, jason-jh.lin wrote:
> 1. Add MERGE module file.
> 2. Add REG_FLD macro in mtk_dem_crtc header to support
>    bitwise register settings.
> 
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/Makefile           |   1 +
>  drivers/gpu/drm/mediatek/mtk_disp_drv.h     |  11 +
>  drivers/gpu/drm/mediatek/mtk_disp_merge.c   | 623 ++++++++++++++++++++
>  drivers/gpu/drm/mediatek/mtk_drm_crtc.h     |  31 +
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |  16 +
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |   1 +
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c      |   4 +
>  drivers/gpu/drm/mediatek/mtk_drm_drv.h      |   1 +
>  drivers/soc/mediatek/mtk-mutex.c            |   1 +
>  include/linux/soc/mediatek/mtk-mmsys.h      |   6 +
>  10 files changed, 695 insertions(+)
>  create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
> 
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index dc54a7a69005..5fd95b9d5aae 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -5,6 +5,7 @@ mediatek-drm-y := mtk_disp_ccorr.o \
>  		  mtk_disp_gamma.o \
>  		  mtk_disp_ovl.o \
>  		  mtk_disp_rdma.o \
> +		  mtk_disp_merge.o \
>  		  mtk_drm_crtc.o \
>  		  mtk_drm_ddp_comp.o \
>  		  mtk_drm_drv.o \
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index cafd9df2d63b..7fd5260e2a72 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -89,4 +89,15 @@ void mtk_rdma_enable_vblank(struct device *dev,
>  			    void *vblank_cb_data);
>  void mtk_rdma_disable_vblank(struct device *dev);
>  
> +int mtk_merge_clk_enable(struct device *dev);
> +void mtk_merge_clk_disable(struct device *dev);
> +void mtk_merge_enable_vblank(struct device *dev,
> +		    void (*vblank_cb)(void *), void *vblank_cb_data);
> +void mtk_merge_disable_vblank(struct device *dev);
> +void mtk_merge_config(struct device *dev, unsigned int width,
> +		     unsigned int height, unsigned int vrefresh,
> +		     unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> +void mtk_merge_start(struct device *dev);
> +void mtk_merge_stop(struct device *dev);
> +
>  #endif
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> new file mode 100644
> index 000000000000..4867fe3fb93f
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> @@ -0,0 +1,623 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2019 MediaTek Inc.

2021

> + */
> +
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/of_device.h>
> +#include <linux/of_irq.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +#include "mtk_drm_drv.h"
> +#include "mtk_disp_drv.h"
> +
> +#define DISP_REG_MERGE_CTRL (0x000)
> +#define FLD_MERGE_EN REG_FLD_MSB_LSB(0, 0)

#define FLD_MERGE_EN   BIT(0)

> +#define FLD_MERGE_RST REG_FLD_MSB_LSB(4, 4)
> +#define FLD_MERGE_LR_SWAP REG_FLD_MSB_LSB(8, 8)
> +#define FLD_MERGE_DCM_DIS REG_FLD_MSB_LSB(12, 12)
> +
> +#define DISP_REG_MERGE_WIDTH (0x004)
> +#define FLD_IN_WIDHT_L REG_FLD_MSB_LSB(15, 0)

#define FLD_IN_WIDHT_L GENMASK(15, 0)

> +#define FLD_IN_WIDHT_R REG_FLD_MSB_LSB(31, 16)
> +
> +#define DISP_REG_MERGE_HEIGHT (0x008)
> +#define FLD_IN_HEIGHT REG_FLD_MSB_LSB(15, 0)
> +
> +#define DISP_REG_MERGE_SHADOW_CRTL (0x00c)
> +
> +#define DISP_REG_MERGE_DGB0 (0x010)
> +#define FLD_PIXEL_CNT REG_FLD_MSB_LSB(15, 0)
> +#define FLD_MERGE_STATE REG_FLD_MSB_LSB(17, 16)
> +
> +#define DISP_REG_MERGE_DGB1 (0x014)
> +#define FLD_LINE_CNT REG_FLD_MSB_LSB(15, 0)
> +
> +#define DISP_REG_MERGE_CFG2_0 (0x160)
> +
> +#define DISP_REG_MERGE_CFG2_2 (0x168)
> +
> +#define MT8195_DISP_MERGE_RESET		0x004

MT8195_DISP_MERGE_RESET is useless, so remove.

> +#define MT8195_DISP_MERGE_CFG_0		0x010
> +#define MT8195_DISP_MERGE_CFG_1		0x014
> +#define MT8195_DISP_MERGE_CFG_4		0x020
> +#define MT8195_DISP_MERGE_CFG_5		0x024
> +#define MT8195_DISP_MERGE_CFG_8		0x030
> +#define MT8195_DISP_MERGE_CFG_9		0x034
> +#define MT8195_DISP_MERGE_CFG_10	0x038
> +#define MT8195_DISP_MERGE_CFG_11	0x03c
> +#define MT8195_DISP_MERGE_CFG_12	0x040
> +#define CFG_11_11_1PI_1PO_BYPASS	1
> +#define CFG_11_11_2PI_2PO_BYPASS	2
> +#define CFG_10_10_2PI_1PO_BYPASS	3
> +#define CFG_10_10_2PI_2PO_BYPASS	4
> +#define CFG_10_10_1PI_1PO_BUF_MODE	5
> +#define CFG_10_10_1PI_2PO_BUF_MODE	6
> +#define CFG_10_10_2PI_1PO_BUF_MODE	7
> +#define CFG_10_10_2PI_2PO_BUF_MODE	8
> +#define CFG_10_01_1PI_1PO_BUF_MODE	9
> +#define CFG_10_01_2PI_1PO_BUF_MODE	10
> +#define CFG_01_10_1PI_1PO_BUF_MODE	11
> +#define CFG_01_10_1PI_2PO_BUF_MODE	12
> +#define CFG_01_01_1PI_1PO_BUF_MODE	13
> +#define CFG_10_11_1PI_1PO_SPLIT		14
> +#define CFG_10_11_2PI_1PO_SPLIT		15
> +#define CFG_01_11_1PI_1PO_SPLIT		16
> +#define CFG_11_10_1PI_1PO_MERGE		17
> +#define CFG_11_10_1PI_2PO_MERGE		18
> +#define CFG_10_10_1PI_1PO_TO422		19
> +#define CFG_10_10_1PI_2PO_TO444		20
> +#define CFG_10_10_2PI_2PO_TO444		21
> +#define MT8195_DISP_MERGE_CFG_13	0x044
> +#define MT8195_DISP_MERGE_CFG_14	0x048
> +#define MT8195_DISP_MERGE_CFG_15	0x04c
> +#define MT8195_DISP_MERGE_CFG_17	0x054
> +#define MT8195_DISP_MERGE_CFG_18	0x058
> +#define MT8195_DISP_MERGE_CFG_19	0x05c
> +#define MT8195_DISP_MERGE_CFG_20	0x060
> +#define MT8195_DISP_MERGE_CFG_21	0x064
> +#define MT8195_DISP_MERGE_CFG_22	0x068
> +#define MT8195_DISP_MERGE_CFG_23	0x06c
> +#define MT8195_DISP_MERGE_CFG_24	0x070
> +#define MT8195_DISP_MERGE_CFG_25	0x074
> +#define MT8195_DISP_MERGE_CFG_26	0x078
> +#define MT8195_DISP_MERGE_CFG_27	0x07c
> +#define MT8195_DISP_MERGE_CFG_28	0x080
> +#define MT8195_DISP_MERGE_CFG_29	0x084
> +#define MT8195_DISP_MERGE_CFG_36	0x0a0
> +#define MT8195_DISP_MERGE_CFG_36_FLD_ULTRA_EN \
> +	REG_FLD(1, 0)
> +#define MT8195_DISP_MERGE_CFG_36_FLD_PREULTRA_EN \
> +	REG_FLD(1, 4)
> +#define MT8195_DISP_MERGE_CFG_36_FLD_HALT_FOR_DVFS_EN \
> +	REG_FLD(1, 8)
> +#define MT8195_DISP_MERGE_CFG_36_VAL_ULTRA_EN(val) \
> +	REG_FLD_VAL(MT8195_DISP_MERGE_CFG_36_FLD_ULTRA_EN, val)
> +#define MT8195_DISP_MERGE_CFG_36_VAL_PREULTRA_EN(val) \
> +	REG_FLD_VAL(MT8195_DISP_MERGE_CFG_36_FLD_PREULTRA_EN, val)
> +#define MT8195_DISP_MERGE_CFG_36_VAL_HALT_FOR_DVFS_EN(val) \
> +	REG_FLD_VAL(MT8195_DISP_MERGE_CFG_36_FLD_HALT_FOR_DVFS_EN, val)
> +#define MT8195_DISP_MERGE_CFG_37	0x0a4
> +#define MT8195_DISP_MERGE_CFG_37_FLD_BUFFER_MODE \
> +	REG_FLD(2, 0)
> +#define MT8195_DISP_MERGE_CFG_37_VAL_BUFFER_MODE(val) \
> +	REG_FLD_VAL(MT8195_DISP_MERGE_CFG_37_FLD_BUFFER_MODE, val)
> +#define MT8195_DISP_MERGE_CFG_38	0x0a8
> +#define MT8195_DISP_MERGE_CFG_38_FLD_VDE_BLOCK_ULTRA \
> +	REG_FLD(1, 0)
> +#define MT8195_DISP_MERGE_CFG_38_FLD_VALID_TH_BLOCK_ULTRA \
> +	REG_FLD(1, 4)
> +#define MT8195_DISP_MERGE_CFG_38_FLD_ULTRA_FIFO_VALID_TH \
> +	REG_FLD(16, 16)
> +#define MT8195_DISP_MERGE_CFG_38_VAL_VDE_BLOCK_ULTRA(val) \
> +	REG_FLD_VAL(MT8195_DISP_MERGE_CFG_38_FLD_VDE_BLOCK_ULTRA, val)
> +#define MT8195_DISP_MERGE_CFG_38_VAL_VALID_TH_BLOCK_ULTRA(val) \
> +	REG_FLD_VAL(MT8195_DISP_MERGE_CFG_38_FLD_VALID_TH_BLOCK_ULTRA, val)
> +#define MT8195_DISP_MERGE_CFG_38_VAL_ULTRA_FIFO_VALID_TH(val) \
> +	REG_FLD_VAL(MT8195_DISP_MERGE_CFG_38_FLD_ULTRA_FIFO_VALID_TH, val)
> +#define MT8195_DISP_MERGE_CFG_39	0x0ac
> +#define MT8195_DISP_MERGE_CFG_39_FLD_NVDE_FORCE_PREULTRA \
> +	REG_FLD(1, 8)
> +#define MT8195_DISP_MERGE_CFG_39_FLD_NVALID_TH_FORCE_PREULTRA \
> +	REG_FLD(1, 12)
> +#define MT8195_DISP_MERGE_CFG_39_FLD_PREULTRA_FIFO_VALID_TH \
> +	REG_FLD(16, 16)
> +#define MT8195_DISP_MERGE_CFG_39_VAL_NVDE_FORCE_PREULTRA(val) \
> +	REG_FLD_VAL(MT8195_DISP_MERGE_CFG_39_FLD_NVDE_FORCE_PREULTRA, val)
> +#define MT8195_DISP_MERGE_CFG_39_VAL_NVALID_TH_FORCE_PREULTRA(val) \
> +	REG_FLD_VAL(MT8195_DISP_MERGE_CFG_39_FLD_NVALID_TH_FORCE_PREULTRA, val)
> +#define MT8195_DISP_MERGE_CFG_39_VAL_PREULTRA_FIFO_VALID_TH(val) \
> +	REG_FLD_VAL(MT8195_DISP_MERGE_CFG_39_FLD_PREULTRA_FIFO_VALID_TH, val)
> +#define MT8195_DISP_MERGE_CFG_40	0x0b0
> +#define MT8195_DISP_MERGE_CFG_40_FLD_ULTRA_TH_LOW \
> +	REG_FLD(16, 0)
> +#define MT8195_DISP_MERGE_CFG_40_FLD_ULTRA_TH_HIGH \
> +	REG_FLD(16, 16)
> +#define MT8195_DISP_MERGE_CFG_40_VAL_ULTRA_TH_LOW(val) \
> +	REG_FLD_VAL(MT8195_DISP_MERGE_CFG_40_FLD_ULTRA_TH_LOW, (val))
> +#define MT8195_DISP_MERGE_CFG_40_VAL_ULTRA_TH_HIGH(val) \
> +	REG_FLD_VAL(MT8195_DISP_MERGE_CFG_40_FLD_ULTRA_TH_HIGH, val)
> +#define MT8195_DISP_MERGE_CFG_41	0x0b4
> +#define MT8195_DISP_MERGE_CFG_41_FLD_PREULTRA_TH_LOW \
> +	REG_FLD(16, 0)
> +#define MT8195_DISP_MERGE_CFG_41_FLD_PREULTRA_TH_HIGH \
> +	REG_FLD(16, 16)
> +#define MT8195_DISP_MERGE_CFG_41_VAL_PREULTRA_TH_LOW(val) \
> +	REG_FLD_VAL(MT8195_DISP_MERGE_CFG_41_FLD_PREULTRA_TH_LOW, val)
> +#define MT8195_DISP_MERGE_CFG_41_VAL_PREULTRA_TH_HIGH(val) \
> +	REG_FLD_VAL(MT8195_DISP_MERGE_CFG_41_FLD_PREULTRA_TH_HIGH, val)
> +
> +struct mtk_disp_merge_data {
> +	bool need_golden_setting;
> +	enum mtk_ddp_comp_id gs_comp_id;
> +};

Now only support mt8195-merge, so remove mtk_disp_merge_data.

> +
> +struct mtk_merge_config_struct {
> +	unsigned short width_right;
> +	unsigned short width_left;
> +	unsigned int height;
> +	unsigned int fmt;
> +	unsigned int mode;
> +	unsigned int swap;

Could you explain this parameter?

> +};
> +
> +struct mtk_disp_merge {
> +	struct mtk_ddp_comp ddp_comp;
> +	struct drm_crtc *crtc;

I think sub driver should get rid of ddp_comp and crtc.

> +	struct clk *clk;
> +	struct clk *async_clk;
> +	void __iomem *regs;
> +	struct cmdq_client_reg		cmdq_reg;
> +	int irq;
> +	void (*vblank_cb)(void *data);

Why implement vblank_cb? For the first patch of one driver, just keep
the basic function.

> +	void *vblank_cb_data;
> +	const struct mtk_disp_merge_data *data;
> +};
> +
> +static struct mtk_ddp_comp *merge_5_comp;

Useless, so remove.

> +
> +static inline struct mtk_disp_merge *comp_to_merge(struct mtk_ddp_comp *comp)
> +{
> +	return container_of(comp, struct mtk_disp_merge, ddp_comp);
> +}

Useless, so remove.

> +
> +void mtk_merge_start(struct device *dev)
> +{
> +	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +
> +	mtk_ddp_write_mask(NULL, 0x1, &priv->cmdq_reg, priv->regs,
> +		DISP_REG_MERGE_CTRL, ~0);

Your mask is 0xffffffff, use mtk_ddp_write().

> +}
> +
> +void mtk_merge_stop(struct device *dev)
> +{
> +	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +
> +	mtk_ddp_write_mask(NULL, 0x0, &priv->cmdq_reg, priv->regs,
> +		DISP_REG_MERGE_CTRL, ~0);

Your mask is 0xffffffff, use mtk_ddp_write().

> +}
> +
> +static int mtk_merge_check_params(struct mtk_merge_config_struct *merge_config)
> +{
> +	if (!merge_config->height ||
> +		!merge_config->width_left || !merge_config->width_right) {
> +		pr_err("%s:merge input width l(%u) w(%u) h(%u)\n",
> +			  __func__, merge_config->width_left,
> +			  merge_config->width_right, merge_config->height);
> +		return -EINVAL;
> +	}
> +	pr_debug("%s:merge input width l(%u) r(%u) height(%u)\n",
> +			  __func__, merge_config->width_left,
> +			  merge_config->width_right, merge_config->height);
> +	return 0;
> +}
> +
> +static int mtk_merge_golden_setting(struct mtk_disp_merge *priv,
> +				  struct cmdq_pkt *handle)
> +{
> +	int ultra_en = 1;
> +	int preultra_en = 1;
> +	int halt_for_dvfs_en = 0;
> +	int buffer_mode = 3;
> +	int vde_block_ultra = 0;
> +	int valid_th_block_ultra = 0;
> +	int ultra_fifo_valid_th = 0;
> +	int nvde_force_preultra = 0;
> +	int nvalid_th_force_preultra = 0;
> +	int preultra_fifo_valid_th = 0;
> +	int ultra_th_low = 0xe10;
> +	int ultra_th_high = 0x12c0;
> +	int preultra_th_low = 0x12c0;
> +	int preultra_th_high = 0x1518;
> +
> +	mtk_ddp_write_mask(handle,
> +		MT8195_DISP_MERGE_CFG_36_VAL_ULTRA_EN(ultra_en) |
> +		MT8195_DISP_MERGE_CFG_36_VAL_PREULTRA_EN(preultra_en) |
> +		MT8195_DISP_MERGE_CFG_36_VAL_HALT_FOR_DVFS_EN(halt_for_dvfs_en),
> +		&priv->cmdq_reg, priv->regs,
> +		MT8195_DISP_MERGE_CFG_36,
> +		REG_FLD_MASK(MT8195_DISP_MERGE_CFG_36_FLD_ULTRA_EN) |
> +		REG_FLD_MASK(MT8195_DISP_MERGE_CFG_36_FLD_PREULTRA_EN) |
> +		REG_FLD_MASK(MT8195_DISP_MERGE_CFG_36_FLD_HALT_FOR_DVFS_EN));
> +
> +	mtk_ddp_write_mask(handle,
> +		MT8195_DISP_MERGE_CFG_37_VAL_BUFFER_MODE(buffer_mode),
> +		&priv->cmdq_reg, priv->regs,
> +		MT8195_DISP_MERGE_CFG_37,
> +		REG_FLD_MASK(MT8195_DISP_MERGE_CFG_37_FLD_BUFFER_MODE));
> +
> +	mtk_ddp_write_mask(handle,
> +		MT8195_DISP_MERGE_CFG_38_VAL_VDE_BLOCK_ULTRA
> +		(vde_block_ultra) |
> +		MT8195_DISP_MERGE_CFG_38_VAL_VALID_TH_BLOCK_ULTRA
> +		(valid_th_block_ultra) |
> +		MT8195_DISP_MERGE_CFG_38_VAL_ULTRA_FIFO_VALID_TH
> +		(ultra_fifo_valid_th),
> +		&priv->cmdq_reg, priv->regs,
> +		MT8195_DISP_MERGE_CFG_38,
> +		REG_FLD_MASK
> +		(MT8195_DISP_MERGE_CFG_38_FLD_VDE_BLOCK_ULTRA) |
> +		REG_FLD_MASK
> +		(MT8195_DISP_MERGE_CFG_38_FLD_VALID_TH_BLOCK_ULTRA) |
> +		REG_FLD_MASK
> +		(MT8195_DISP_MERGE_CFG_38_FLD_ULTRA_FIFO_VALID_TH));
> +
> +	mtk_ddp_write_mask(handle,
> +		MT8195_DISP_MERGE_CFG_39_VAL_NVDE_FORCE_PREULTRA
> +		(nvde_force_preultra) |
> +		MT8195_DISP_MERGE_CFG_39_VAL_NVALID_TH_FORCE_PREULTRA
> +		(nvalid_th_force_preultra) |
> +		MT8195_DISP_MERGE_CFG_39_VAL_PREULTRA_FIFO_VALID_TH
> +		(preultra_fifo_valid_th),
> +		&priv->cmdq_reg, priv->regs,
> +		MT8195_DISP_MERGE_CFG_39,
> +		REG_FLD_MASK
> +		(MT8195_DISP_MERGE_CFG_39_FLD_NVDE_FORCE_PREULTRA) |
> +		REG_FLD_MASK
> +		(MT8195_DISP_MERGE_CFG_39_FLD_NVALID_TH_FORCE_PREULTRA) |
> +		REG_FLD_MASK
> +		(MT8195_DISP_MERGE_CFG_39_FLD_PREULTRA_FIFO_VALID_TH));
> +
> +	mtk_ddp_write_mask(handle,
> +		MT8195_DISP_MERGE_CFG_40_VAL_ULTRA_TH_LOW(ultra_th_low) |
> +		MT8195_DISP_MERGE_CFG_40_VAL_ULTRA_TH_HIGH(ultra_th_high),
> +		&priv->cmdq_reg, priv->regs,
> +		MT8195_DISP_MERGE_CFG_40,
> +		REG_FLD_MASK(MT8195_DISP_MERGE_CFG_40_FLD_ULTRA_TH_LOW) |
> +		REG_FLD_MASK(MT8195_DISP_MERGE_CFG_40_FLD_ULTRA_TH_HIGH));
> +
> +	mtk_ddp_write_mask(handle,
> +		MT8195_DISP_MERGE_CFG_41_VAL_PREULTRA_TH_LOW(preultra_th_low) |
> +		MT8195_DISP_MERGE_CFG_41_VAL_PREULTRA_TH_HIGH(preultra_th_high),
> +		&priv->cmdq_reg, priv->regs,
> +		MT8195_DISP_MERGE_CFG_41,
> +		REG_FLD_MASK(MT8195_DISP_MERGE_CFG_41_FLD_PREULTRA_TH_LOW) |
> +		REG_FLD_MASK(MT8195_DISP_MERGE_CFG_41_FLD_PREULTRA_TH_HIGH));
> +
> +	return 0;
> +}
> +
> +void mtk_merge_config(struct device *dev, unsigned int w,
> +				  unsigned int h, unsigned int vrefresh,
> +				  unsigned int bpc, struct cmdq_pkt *handle)
> +{
> +	struct mtk_merge_config_struct merge_config;
> +	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +	struct mtk_ddp_comp *comp = &priv->ddp_comp;
> +
> +	/*golden setting*/
> +	if (priv->data) {
> +		if (priv->data->need_golden_setting &&
> +			priv->data->gs_comp_id == comp->id)
> +			mtk_merge_golden_setting(priv, handle);
> +	}
> +
> +	switch (comp->id) {
> +	case DDP_COMPONENT_MERGE0:
> +		merge_config.mode = CFG_10_10_1PI_2PO_BUF_MODE;
> +		merge_config.width_left = w;
> +		merge_config.width_right = w;
> +		merge_config.height = h;
> +		merge_config.swap = 0;
> +		break;
> +	case DDP_COMPONENT_MERGE5:
> +		merge_config.mode = CFG_10_10_2PI_2PO_BUF_MODE;
> +		merge_config.width_left = w;
> +		merge_config.width_right = w;
> +		merge_config.height = h;
> +		merge_config.swap = 0;
> +		break;
> +	default:
> +		pr_err("No find component merge %d\n", comp->id);
> +		return;
> +	}
> +
> +	mtk_merge_check_params(&merge_config);
> +
> +	switch (merge_config.mode) {
> +	case CFG_10_10_1PI_1PO_BUF_MODE:

CFG_10_10_1PI_1PO_BUF_MODE is useless, so remove.

> +	case CFG_10_10_1PI_2PO_BUF_MODE:
> +	case CFG_10_10_2PI_2PO_BUF_MODE:
> +		mtk_ddp_write_mask(handle,
> +			(merge_config.height << 16 | merge_config.width_left),
> +			&priv->cmdq_reg, priv->regs,
> +			MT8195_DISP_MERGE_CFG_0, ~0);
> +
> +		mtk_ddp_write_mask(handle,
> +			(merge_config.height << 16 | merge_config.width_left),
> +			&priv->cmdq_reg, priv->regs,
> +			MT8195_DISP_MERGE_CFG_4, ~0);
> +
> +		mtk_ddp_write_mask(handle,
> +			(merge_config.height << 16 | merge_config.width_left),
> +			&priv->cmdq_reg, priv->regs,
> +			MT8195_DISP_MERGE_CFG_24, ~0);
> +
> +		mtk_ddp_write_mask(handle,
> +			(merge_config.height << 16 | merge_config.width_left),
> +			&priv->cmdq_reg, priv->regs,
> +			MT8195_DISP_MERGE_CFG_25, ~0);
> +
> +		mtk_ddp_write_mask(handle,
> +			merge_config.swap,
> +			&priv->cmdq_reg, priv->regs,
> +			MT8195_DISP_MERGE_CFG_10, 0x1f);
> +	break;
> +	case CFG_11_10_1PI_2PO_MERGE:

CFG_11_10_1PI_2PO_MERGE is useless, so remove.

> +		mtk_ddp_write_mask(handle,
> +			(merge_config.height << 16 | merge_config.width_left),
> +			&priv->cmdq_reg, priv->regs,
> +			MT8195_DISP_MERGE_CFG_0, ~0);
> +
> +		mtk_ddp_write_mask(handle,
> +			(merge_config.height << 16 | merge_config.width_right),
> +			&priv->cmdq_reg, priv->regs,
> +			MT8195_DISP_MERGE_CFG_1, ~0);
> +
> +		mtk_ddp_write_mask(handle,
> +			(merge_config.height << 16 | w),
> +			&priv->cmdq_reg, priv->regs,
> +			MT8195_DISP_MERGE_CFG_4, ~0);
> +
> +		mtk_ddp_write_mask(handle,
> +			(merge_config.height << 16 | merge_config.width_left),
> +			&priv->cmdq_reg, priv->regs,
> +			MT8195_DISP_MERGE_CFG_24, ~0);
> +
> +		mtk_ddp_write_mask(handle,
> +			(merge_config.height << 16 | merge_config.width_right),
> +			&priv->cmdq_reg, priv->regs,
> +			MT8195_DISP_MERGE_CFG_25, ~0);
> +
> +		mtk_ddp_write_mask(handle,
> +			(merge_config.height << 16 | merge_config.width_left),
> +			&priv->cmdq_reg, priv->regs,
> +			MT8195_DISP_MERGE_CFG_26, ~0);
> +
> +		mtk_ddp_write_mask(handle,
> +			(merge_config.height << 16 | merge_config.width_right),
> +			&priv->cmdq_reg, priv->regs,
> +			MT8195_DISP_MERGE_CFG_27, ~0);
> +
> +		mtk_ddp_write_mask(handle,
> +			merge_config.swap,
> +			&priv->cmdq_reg, priv->regs,
> +			MT8195_DISP_MERGE_CFG_10, 0x1f);
> +	break;
> +	default:
> +	break;
> +	}
> +	mtk_ddp_write_mask(handle, merge_config.mode,
> +		&priv->cmdq_reg, priv->regs, MT8195_DISP_MERGE_CFG_12, 0x1f);
> +	mtk_ddp_write_mask(handle, 0x1,
> +		&priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CTRL, 0x1);
> +}
> +
> +int mtk_merge_clk_enable(struct device *dev)
> +{
> +	int ret = 0;
> +	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +
> +	ret = pm_runtime_get_sync(dev);
> +
> +	if (priv->clk) {
> +		ret = clk_prepare_enable(priv->clk);
> +		if (ret)
> +			pr_err("merge clk prepare enable failed\n");
> +	}
> +
> +	if (priv->async_clk) {
> +		ret = clk_prepare_enable(priv->async_clk);
> +		if (ret)
> +			pr_err("async clk prepare enable failed\n");
> +	}
> +
> +	return ret;
> +}
> +
> +void mtk_merge_clk_disable(struct device *dev)
> +{
> +	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +
> +	if (priv->async_clk)
> +		clk_disable_unprepare(priv->async_clk);
> +
> +	if (priv->clk)
> +		clk_disable_unprepare(priv->clk);
> +
> +	pm_runtime_put_sync(dev);
> +}
> +
> +void mtk_merge_enable_vblank(struct device *dev,
> +			    void (*vblank_cb)(void *),
> +			    void *vblank_cb_data)
> +{
> +	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +	int irq_frame_done_en = BIT(16);
> +
> +	priv->vblank_cb = vblank_cb;
> +	priv->vblank_cb_data = vblank_cb_data;
> +
> +	writel(irq_frame_done_en, priv->regs + DISP_REG_MERGE_CFG2_0);
> +}

Useless, so remove.

> +
> +void mtk_merge_disable_vblank(struct device *dev)
> +{
> +	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +
> +	priv->vblank_cb = NULL;
> +	priv->vblank_cb_data = NULL;
> +
> +	writel(0x0, priv->regs + DISP_REG_MERGE_CFG2_0);
> +}

Useless, so remove.

> +
> +static int mtk_disp_merge_bind(struct device *dev, struct device *master,
> +			       void *data)
> +{
> +	return 0;
> +}
> +
> +static void mtk_disp_merge_unbind(struct device *dev, struct device *master,
> +				  void *data)
> +{
> +}
> +
> +static irqreturn_t mtk_disp_merge_irq_handler(int irq, void *dev_id)
> +{
> +	struct mtk_disp_merge *priv = dev_id;
> +
> +	/* Clear frame completion interrupt */
> +	writel(0x1, priv->regs + DISP_REG_MERGE_CFG2_2);
> +	writel(0x0, priv->regs + DISP_REG_MERGE_CFG2_2);
> +
> +	if (!priv->vblank_cb)
> +		return IRQ_NONE;
> +
> +	priv->vblank_cb(priv->vblank_cb_data);
> +
> +	return IRQ_HANDLED;
> +}

Useless, so remove.

> +
> +static const struct component_ops mtk_disp_merge_component_ops = {
> +	.bind	= mtk_disp_merge_bind,
> +	.unbind = mtk_disp_merge_unbind,
> +};
> +
> +static int mtk_disp_merge_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct resource *res;
> +	struct mtk_disp_merge *priv;
> +	enum mtk_ddp_comp_id comp_id;
> +	int ret;
> +
> +	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> +	if (!priv)
> +		return -ENOMEM;
> +
> +	comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_MERGE);
> +	if ((int)comp_id < 0) {
> +		dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
> +		return comp_id;
> +	}
> +
> +	priv->ddp_comp.id = comp_id;
> +
> +	if (comp_id == DDP_COMPONENT_MERGE5)
> +		merge_5_comp = &priv->ddp_comp;
> +
> +	priv->clk = devm_clk_get(dev, NULL);
> +	if (IS_ERR(priv->clk)) {
> +		dev_err(dev, "failed to get merge clk\n");
> +		return PTR_ERR(priv->clk);
> +	}
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	priv->regs = devm_ioremap_resource(dev, res);
> +	if (IS_ERR(priv->regs)) {
> +		dev_err(dev, "failed to ioremap merge\n");
> +		return PTR_ERR(priv->regs);
> +	}
> +
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> +	ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
> +	if (ret)
> +		dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
> +#endif
> +
> +	priv->irq = platform_get_irq(pdev, 0);
> +	if (priv->irq < 0)
> +		priv->irq = 0;
> +
> +	priv->async_clk = of_clk_get(dev->of_node, 1);

From binding document and device tree, there is no async clk, would you
modify binding document?

Regards,
CK

> +	if (IS_ERR(priv->async_clk)) {
> +		ret = PTR_ERR(priv->async_clk);
> +		dev_dbg(dev, "No merge async clock: %d\n", ret);
> +		priv->async_clk = NULL;
> +	}
> +
> +	priv->data = of_device_get_match_data(dev);
> +
> +	if (priv->irq) {
> +		ret = devm_request_irq(dev, priv->irq,
> +					mtk_disp_merge_irq_handler,
> +					IRQF_TRIGGER_NONE, dev_name(dev), priv);
> +		if (ret < 0) {
> +			dev_err(dev, "Failed to request irq %d: %d\n",
> +					priv->irq, ret);
> +			return ret;
> +		}
> +	}
> +
> +	platform_set_drvdata(pdev, priv);
> +
> +	pm_runtime_enable(dev);
> +
> +	ret = component_add(dev, &mtk_disp_merge_component_ops);
> +	if (ret != 0) {
> +		dev_err(dev, "Failed to add component: %d\n", ret);
> +		pm_runtime_disable(dev);
> +	}
> +
> +	return ret;
> +}
> +
> +static int mtk_disp_merge_remove(struct platform_device *pdev)
> +{
> +	component_del(&pdev->dev, &mtk_disp_merge_component_ops);
> +
> +	pm_runtime_disable(&pdev->dev);
> +
> +	return 0;
> +}
> +
> +static const struct mtk_disp_merge_data mt8195_merge_driver_data = {
> +	.need_golden_setting = true,
> +	.gs_comp_id = DDP_COMPONENT_MERGE5,
> +};
> +
> +static const struct of_device_id mtk_disp_merge_driver_dt_match[] = {
> +	{
> +		.compatible = "mediatek,mt8195-disp-merge",
> +		.data = &mt8195_merge_driver_data
> +	},
> +	{},
> +};
> +
> +MODULE_DEVICE_TABLE(of, mtk_disp_merge_driver_dt_match);
> +
> +struct platform_driver mtk_disp_merge_driver = {
> +	.probe = mtk_disp_merge_probe,
> +	.remove = mtk_disp_merge_remove,
> +	.driver = {
> +		.name = "mediatek-disp-merge",
> +		.owner = THIS_MODULE,
> +		.of_match_table = mtk_disp_merge_driver_dt_match,
> +	},
> +};
> +
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> index cb9a36c48d4f..7419cd0fb424 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> @@ -14,6 +14,37 @@
>  #define MTK_MAX_BPC	10
>  #define MTK_MIN_BPC	3
>  
> +#define _MASK_SHIFT(val, width, shift) \
> +	(((val) >> (shift)) & ((1 << (width)) - 1))
> +
> +#define REG_FLD(width, shift) \
> +	((unsigned int)((((width) & 0xff) << 16) | ((shift) & 0xff)))
> +
> +#define REG_FLD_MSB_LSB(msb, lsb) REG_FLD((msb) - (lsb) + 1, (lsb))
> +
> +#define REG_FLD_WIDTH(field) ((unsigned int)(((field) >> 16) & 0xff))
> +
> +#define REG_FLD_SHIFT(field) ((unsigned int)((field) & 0xff))
> +
> +#define REG_FLD_MASK(field) \
> +	((unsigned int)((1ULL << REG_FLD_WIDTH(field)) - 1) \
> +	 << REG_FLD_SHIFT(field))
> +
> +#define REG_FLD_VAL(field, val) \
> +	(((val) << REG_FLD_SHIFT(field)) & REG_FLD_MASK(field))
> +
> +#define REG_FLD_VAL_GET(field, regval) \
> +	(((regval) & REG_FLD_MASK(field)) >> REG_FLD_SHIFT(field))
> +
> +#define DISP_REG_GET_FIELD(field, reg32) \
> +	REG_FLD_VAL_GET(field, __raw_readl((unsigned long *)(reg32)))
> +
> +#define SET_VAL_MASK(o_val, o_mask, i_val, i_fld) \
> +	do { \
> +		(o_val) |= ((i_val) << REG_FLD_SHIFT(i_fld)); \
> +		(o_mask) |= (REG_FLD_MASK(i_fld)); \
> +	} while (0)
> +
>  void mtk_drm_crtc_commit(struct drm_crtc *crtc);
>  int mtk_drm_crtc_create(struct drm_device *drm_dev,
>  			const enum mtk_ddp_comp_id *path,
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index f154f7c0cd11..2ccf3db1950d 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -339,6 +339,14 @@ static const struct mtk_ddp_comp_funcs ddp_rdma = {
>  	.layer_config = mtk_rdma_layer_config,
>  };
>  
> +static const struct mtk_ddp_comp_funcs ddp_merge = {
> +	.clk_enable = mtk_merge_clk_enable,
> +	.clk_disable = mtk_merge_clk_disable,
> +	.start = mtk_merge_start,
> +	.stop = mtk_merge_stop,
> +	.config = mtk_merge_config,
> +};
> +
>  static const struct mtk_ddp_comp_funcs ddp_ufoe = {
>  	.clk_enable = mtk_ddp_clk_enable,
>  	.clk_disable = mtk_ddp_clk_disable,
> @@ -362,6 +370,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
>  	[MTK_DISP_MUTEX] = "mutex",
>  	[MTK_DISP_OD] = "od",
>  	[MTK_DISP_BLS] = "bls",
> +	[MTK_DISP_MERGE] = "merge",
>  };
>  
>  struct mtk_ddp_comp_match {
> @@ -397,6 +406,12 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
>  	[DDP_COMPONENT_RDMA0]	= { MTK_DISP_RDMA,	0, &ddp_rdma },
>  	[DDP_COMPONENT_RDMA1]	= { MTK_DISP_RDMA,	1, &ddp_rdma },
>  	[DDP_COMPONENT_RDMA2]	= { MTK_DISP_RDMA,	2, &ddp_rdma },
> +	[DDP_COMPONENT_MERGE0]	= { MTK_DISP_MERGE,	0, &ddp_merge },
> +	[DDP_COMPONENT_MERGE1]	= { MTK_DISP_MERGE,	1, &ddp_merge },
> +	[DDP_COMPONENT_MERGE2]	= { MTK_DISP_MERGE,	2, &ddp_merge },
> +	[DDP_COMPONENT_MERGE3]	= { MTK_DISP_MERGE,	3, &ddp_merge },
> +	[DDP_COMPONENT_MERGE4]	= { MTK_DISP_MERGE,	4, &ddp_merge },
> +	[DDP_COMPONENT_MERGE5]	= { MTK_DISP_MERGE,	5, &ddp_merge },
>  	[DDP_COMPONENT_UFOE]	= { MTK_DISP_UFOE,	0, &ddp_ufoe },
>  	[DDP_COMPONENT_WDMA0]	= { MTK_DISP_WDMA,	0, NULL },
>  	[DDP_COMPONENT_WDMA1]	= { MTK_DISP_WDMA,	1, NULL },
> @@ -515,6 +530,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
>  	    type == MTK_DISP_CCORR ||
>  	    type == MTK_DISP_COLOR ||
>  	    type == MTK_DISP_GAMMA ||
> +	    type == MTK_DISP_MERGE ||
>  	    type == MTK_DPI ||
>  	    type == MTK_DSI ||
>  	    type == MTK_DISP_OVL ||
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index bb914d976cf5..038775b4531b 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -34,6 +34,7 @@ enum mtk_ddp_comp_type {
>  	MTK_DISP_MUTEX,
>  	MTK_DISP_OD,
>  	MTK_DISP_BLS,
> +	MTK_DISP_MERGE,
>  	MTK_DDP_COMP_TYPE_MAX,
>  };
>  
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 635cebf9ff0f..f891316008aa 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -462,6 +462,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
>  	  .data = (void *)MTK_DISP_DITHER },
>  	{ .compatible = "mediatek,mt8195-disp-dither",
>  	  .data = (void *)MTK_DISP_DITHER },
> +	{ .compatible = "mediatek,mt8195-disp-merge",
> +	  .data = (void *)MTK_DISP_MERGE },
>  	{ .compatible = "mediatek,mt8173-disp-ufoe",
>  	  .data = (void *)MTK_DISP_UFOE },
>  	{ .compatible = "mediatek,mt2701-dsi",
> @@ -579,6 +581,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
>  		if (comp_type == MTK_DISP_CCORR ||
>  		    comp_type == MTK_DISP_COLOR ||
>  		    comp_type == MTK_DISP_GAMMA ||
> +		    comp_type == MTK_DISP_MERGE ||
>  		    comp_type == MTK_DISP_OVL ||
>  		    comp_type == MTK_DISP_OVL_2L ||
>  		    comp_type == MTK_DISP_RDMA ||
> @@ -683,6 +686,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
>  	&mtk_disp_rdma_driver,
>  	&mtk_dpi_driver,
>  	&mtk_drm_platform_driver,
> +	&mtk_disp_merge_driver,
>  	&mtk_dsi_driver,
>  };
>  
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index 637f5669e895..18548a373626 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -51,6 +51,7 @@ extern struct platform_driver mtk_disp_color_driver;
>  extern struct platform_driver mtk_disp_gamma_driver;
>  extern struct platform_driver mtk_disp_ovl_driver;
>  extern struct platform_driver mtk_disp_rdma_driver;
> +extern struct platform_driver mtk_disp_merge_driver;
>  extern struct platform_driver mtk_dpi_driver;
>  extern struct platform_driver mtk_dsi_driver;
>  
> diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
> index 080bdabfb024..84ece5486902 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -284,6 +284,7 @@ static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
>  	[DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
>  	[DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
>  	[DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
> +	[DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
>  	[DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
>  	[DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
>  };
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index 2228bf6133da..3135ce82a7f7 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -39,6 +39,12 @@ enum mtk_ddp_comp_id {
>  	DDP_COMPONENT_UFOE,
>  	DDP_COMPONENT_WDMA0,
>  	DDP_COMPONENT_WDMA1,
> +	DDP_COMPONENT_MERGE0,
> +	DDP_COMPONENT_MERGE1,
> +	DDP_COMPONENT_MERGE2,
> +	DDP_COMPONENT_MERGE3,
> +	DDP_COMPONENT_MERGE4,
> +	DDP_COMPONENT_MERGE5,
>  	DDP_COMPONENT_ID_MAX,
>  };
>  

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^ permalink raw reply	[flat|nested] 42+ messages in thread

* Re: [PATCH v1 17/17] drm/mediatek: add DSC support for MT8195
  2021-07-07  4:12 ` [PATCH v1 17/17] drm/mediatek: add DSC " jason-jh.lin
@ 2021-07-07  7:35   ` CK Hu
  2021-07-10  7:55     ` Jason-JH Lin
  0 siblings, 1 reply; 42+ messages in thread
From: CK Hu @ 2021-07-07  7:35 UTC (permalink / raw)
  To: jason-jh.lin
  Cc: chunkuang.hu, matthias.bgg, linux-arm-kernel, linux-mediatek,
	linux-kernel, devicetree, Project_Global_Chrome_Upstream_Group,
	fshao, nancy.lin, singo.chang

Hi, Jason:

On Wed, 2021-07-07 at 12:12 +0800, jason-jh.lin wrote:
> 1. Add DSC module file.
> 2. Add mtk_panel_ext source file to get the mtk_panel_dsc_params
>    from panel.
> 3. Add DSC related path to mtk-mmsys routing table.
> 
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/Makefile           |   4 +-
>  drivers/gpu/drm/mediatek/mtk_disp_drv.h     |   8 +
>  drivers/gpu/drm/mediatek/mtk_disp_dsc.c     | 286 ++++++++++++++++
>  drivers/gpu/drm/mediatek/mtk_drm_crtc.h     |   1 +
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |  13 +
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |   1 +
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c      |   4 +
>  drivers/gpu/drm/mediatek/mtk_drm_drv.h      |   1 +
>  drivers/gpu/drm/mediatek/mtk_panel_ext.c    | 136 ++++++++
>  drivers/gpu/drm/mediatek/mtk_panel_ext.h    | 344 ++++++++++++++++++++
>  drivers/soc/mediatek/mt8195-mmsys.h         |  18 +
>  drivers/soc/mediatek/mtk-mutex.c            |   1 +
>  include/linux/soc/mediatek/mtk-mmsys.h      |   3 +
>  13 files changed, 819 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_dsc.c
>  create mode 100644 drivers/gpu/drm/mediatek/mtk_panel_ext.c
>  create mode 100644 drivers/gpu/drm/mediatek/mtk_panel_ext.h
> 
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index 5fd95b9d5aae..4dc0b2901a22 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -6,13 +6,15 @@ mediatek-drm-y := mtk_disp_ccorr.o \
>  		  mtk_disp_ovl.o \
>  		  mtk_disp_rdma.o \
>  		  mtk_disp_merge.o \
> +		  mtk_disp_dsc.o \
>  		  mtk_drm_crtc.o \
>  		  mtk_drm_ddp_comp.o \
>  		  mtk_drm_drv.o \
>  		  mtk_drm_gem.o \
>  		  mtk_drm_plane.o \
>  		  mtk_dsi.o \
> -		  mtk_dpi.o
> +		  mtk_dpi.o \
> +		  mtk_panel_ext.o
>  
>  obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
>  
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index 7fd5260e2a72..11a6c9d6cff3 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -100,4 +100,12 @@ void mtk_merge_config(struct device *dev, unsigned int width,
>  void mtk_merge_start(struct device *dev);
>  void mtk_merge_stop(struct device *dev);
>  
> +int mtk_dsc_clk_enable(struct device *dev);
> +void mtk_dsc_clk_disable(struct device *dev);
> +void mtk_dsc_config(struct device *dev, unsigned int width,
> +		     unsigned int height, unsigned int vrefresh,
> +		     unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> +void mtk_dsc_start(struct device *dev);
> +void mtk_dsc_stop(struct device *dev);
> +
>  #endif
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_dsc.c b/drivers/gpu/drm/mediatek/mtk_disp_dsc.c
> new file mode 100644
> index 000000000000..5da820feead5
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_dsc.c
> @@ -0,0 +1,286 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2019 MediaTek Inc.

2021

> + */
> +
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/of_device.h>
> +#include <linux/of_irq.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +#include "mtk_drm_gem.h"
> +#include "mtk_disp_drv.h"
> +#ifdef CONFIG_MTK_DPTX_SUPPORT
> +#include "mtk_dp_api.h"
> +#endif
> +
> +#define DISP_REG_DSC_CON			0x0000
> +#define DSC_EN						BIT(0)
> +#define DSC_DUAL_INOUT				BIT(2)
> +#define DSC_IN_SRC_SEL				BIT(3)
> +#define DSC_BYPASS					BIT(4)
> +#define DSC_RELAY					BIT(5)
> +#define DSC_EMPTY_FLAG_SEL			0xc000
> +#define DSC_UFOE_SEL				BIT(16)
> +#define DISP_REG_DSC_OBUF			0x0070
> +
> +struct mtk_disp_dsc_data {
> +	bool support_shadow;
> +};

Now just support mt8195-dsc, so remove this.

> +
> +/**
> + * struct mtk_disp_dsc - DISP_DSC driver structure
> + * @clk - clk of dsc hardware
> + * @regs - hardware register address of dsc
> + * @ddp_comp - structure containing type enum and hardware resources
> + * @cmdq_reg - structure containing cmdq hardware resource
> + * @data - dsc driver data
> + * @enable - enable dsc hardward
> + */
> +struct mtk_disp_dsc {
> +	struct clk *clk;
> +	void __iomem *regs;
> +	struct mtk_ddp_comp	ddp_comp;

Sub driver should get rid of ddp_comp.

> +	struct cmdq_client_reg		cmdq_reg;
> +	const struct mtk_disp_dsc_data *data;
> +	int enable;

enable is always false, so remove it.

> +};
> +
> +void mtk_dsc_start(struct device *dev)
> +{
> +	struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
> +	void __iomem *baddr = dsc->regs;
> +	int ret = 0;
> +
> +	ret = pm_runtime_get_sync(dev);
> +	if (ret < 0)
> +		DRM_ERROR("Failed to enable power domain: %d\n", ret);
> +
> +	if (dsc->enable) {
> +		int high = BIT(14);
> +		int obud_sw = BIT(31);
> +		int obud_size = 706; /* unit is 6 byte */
> +
> +		/* DSC Empty flag always high */
> +		mtk_ddp_write_mask(NULL, high,
> +			&dsc->cmdq_reg, baddr,
> +			DISP_REG_DSC_CON, DSC_EMPTY_FLAG_SEL);
> +
> +		/* DSC output buffer as FHD(plus) */
> +		mtk_ddp_write_mask(NULL, (obud_sw | obud_size),
> +			&dsc->cmdq_reg, baddr,
> +			DISP_REG_DSC_OBUF, ~0);
> +	}
> +
> +	mtk_ddp_write_mask(NULL, DSC_EN,
> +		&dsc->cmdq_reg, baddr,
> +		DISP_REG_DSC_CON, DSC_EN);
> +
> +	pr_debug("dsc_start:0x%x\n", readl(baddr + DISP_REG_DSC_CON));
> +}
> +
> +void mtk_dsc_stop(struct device *dev)
> +{
> +	struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
> +	void __iomem *baddr = dsc->regs;
> +	int ret = 0;
> +
> +	mtk_ddp_write_mask(NULL, 0x0, &dsc->cmdq_reg, baddr,
> +		DISP_REG_DSC_CON, DSC_EN);
> +
> +	pr_debug("dsc_stop:0x%x\n", readl(baddr + DISP_REG_DSC_CON));
> +
> +	ret = pm_runtime_put(dev);
> +	if (ret < 0)
> +		DRM_ERROR("Failed to disable power domain: %d\n", ret);
> +}
> +
> +int mtk_dsc_clk_enable(struct device *dev)
> +{
> +	struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
> +
> +	return clk_prepare_enable(dsc->clk);
> +}
> +
> +void mtk_dsc_clk_disable(struct device *dev)
> +{
> +	struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
> +
> +	clk_disable_unprepare(dsc->clk);
> +}
> +
> +static struct mtk_panel_dsc_params *mtk_dsc_default_setting(void)
> +{
> +	static struct mtk_panel_dsc_params dsc_params = {
> +		.enable = 0, /* 0: bypass mode */
> +		.ver = 2,
> +		.slice_mode = 1,
> +		.rgb_swap = 0,
> +		.dsc_cfg = 0x12, /* flatness_det_thr, 8bit */
> +		.rct_on = 1, // default
> +		.bit_per_channel = 8,
> +		.dsc_line_buf_depth = 13, /* 9, 11: for 10bit */
> +		.bp_enable = 1, /* align vend */
> +		.bit_per_pixel = 128, /* 16 x bpp */
> +		.pic_height = 2160,
> +		.pic_width = 3840, /* for dp port 4k scenario */
> +		.slice_height = 8,
> +		.slice_width = 1920, /* frame_width/slice mode */
> +		.chunk_size = 1920,
> +		.xmit_delay = 512,
> +		.dec_delay = 1216,
> +		.scale_value = 32,
> +		.increment_interval = 286,
> +		.decrement_interval = 26,
> +		.line_bpg_offset = 12,
> +		.nfl_bpg_offset = 3511,
> +		.slice_bpg_offset = 916,
> +		.initial_offset = 6144,
> +		.final_offset = 4336,
> +		.flatness_minqp = 3,
> +		.flatness_maxqp = 12,
> +		.rc_model_size = 8192,
> +		.rc_edge_factor = 6,
> +		.rc_quant_incr_limit0 = 11,
> +		.rc_quant_incr_limit1 = 11,
> +		.rc_tgt_offset_hi = 3,
> +		.rc_tgt_offset_lo = 3,
> +	};
> +
> +	return &dsc_params;
> +}

Useless, so remove.

> +
> +void mtk_dsc_config(struct device *dev, unsigned int w,
> +				unsigned int h, unsigned int vrefresh,
> +				unsigned int bpc, struct cmdq_pkt *handle)
> +{
> +	struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
> +	struct mtk_ddp_comp *comp = &dsc->ddp_comp;
> +	struct mtk_panel_dsc_params *dsc_params;
> +
> +	dsc_params = mtk_dsc_default_setting();
> +
> +	if (dsc_params->enable == 1) {
> +		/* dsc enable mode not support yet */
> +		pr_debug("comp_id:%d, w:%d, h:%d\n",
> +			comp->id, w, h);
> +		pr_debug("slice_mode:%d, slice(%d,%d), bpp:%d\n",
> +			dsc_params->slice_mode, dsc_params->slice_width,
> +			dsc_params->slice_height, dsc_params->bit_per_pixel);
> +	} else {
> +		/* dsc bypass mode */
> +		mtk_ddp_write_mask(handle, DSC_BYPASS,
> +			&dsc->cmdq_reg, dsc->regs,
> +			DISP_REG_DSC_CON, DSC_BYPASS);
> +		mtk_ddp_write_mask(handle, DSC_UFOE_SEL,
> +			&dsc->cmdq_reg, dsc->regs,
> +			DISP_REG_DSC_CON, DSC_UFOE_SEL);
> +		mtk_ddp_write_mask(handle, DSC_DUAL_INOUT,
> +			&dsc->cmdq_reg, dsc->regs,
> +			DISP_REG_DSC_CON, DSC_DUAL_INOUT);
> +		dsc->enable = false;
> +	}

Keep only bypass mode.

> +}
> +
> +static int mtk_disp_dsc_bind(struct device *dev, struct device *master,
> +				  void *data)
> +{
> +	return 0;
> +}
> +
> +static void mtk_disp_dsc_unbind(struct device *dev, struct device *master,
> +				 void *data)
> +{
> +}
> +
> +static const struct component_ops mtk_disp_dsc_component_ops = {
> +	.bind = mtk_disp_dsc_bind,
> +	.unbind = mtk_disp_dsc_unbind,
> +};
> +
> +static int mtk_disp_dsc_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct resource *res;
> +	struct mtk_disp_dsc *priv;
> +	int irq;
> +	int ret;
> +
> +	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> +	if (!priv)
> +		return -ENOMEM;
> +
> +	irq = platform_get_irq(pdev, 0);
> +	if (irq < 0)
> +		return irq;
> +
> +	priv->clk = devm_clk_get(dev, NULL);
> +	if (IS_ERR(priv->clk)) {
> +		dev_err(dev, "failed to get dsc clk\n");
> +		return PTR_ERR(priv->clk);
> +	}
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	priv->regs = devm_ioremap_resource(dev, res);
> +	if (IS_ERR(priv->regs)) {
> +		dev_err(dev, "failed to ioremap dsc\n");
> +		return PTR_ERR(priv->regs);
> +	}
> +
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> +	ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
> +	if (ret)
> +		dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
> +#endif
> +
> +	priv->data = of_device_get_match_data(dev);
> +	platform_set_drvdata(pdev, priv);
> +
> +	pm_runtime_enable(dev);
> +
> +	ret = component_add(dev, &mtk_disp_dsc_component_ops);
> +	if (ret != 0) {
> +		dev_err(dev, "Failed to add component: %d\n", ret);
> +		pm_runtime_disable(dev);
> +	}
> +
> +	return ret;
> +}
> +
> +static int mtk_disp_dsc_remove(struct platform_device *pdev)
> +{
> +	component_del(&pdev->dev, &mtk_disp_dsc_component_ops);
> +
> +	pm_runtime_disable(&pdev->dev);
> +
> +	return 0;
> +}
> +
> +static const struct mtk_disp_dsc_data mt8195_dsc_driver_data = {
> +	.support_shadow = false,
> +};
> +
> +static const struct of_device_id mtk_disp_dsc_driver_dt_match[] = {
> +	{
> +		.compatible = "mediatek,mt8195-disp-dsc",
> +		.data = &mt8195_dsc_driver_data
> +	},
> +	{},
> +};
> +
> +MODULE_DEVICE_TABLE(of, mtk_disp_dsc_driver_dt_match);
> +
> +struct platform_driver mtk_disp_dsc_driver = {
> +	.probe = mtk_disp_dsc_probe,
> +	.remove = mtk_disp_dsc_remove,
> +	.driver = {
> +		.name = "mediatek-disp-dsc",
> +		.owner = THIS_MODULE,
> +		.of_match_table = mtk_disp_dsc_driver_dt_match,
> +	},
> +};
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> index 7419cd0fb424..7b8f9cb96d44 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> @@ -9,6 +9,7 @@
>  #include <drm/drm_crtc.h>
>  #include "mtk_drm_ddp_comp.h"
>  #include "mtk_drm_plane.h"
> +#include "mtk_panel_ext.h"
>  
>  #define MTK_LUT_SIZE	512
>  #define MTK_MAX_BPC	10
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 2ccf3db1950d..b68bde6eb6ed 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -347,6 +347,14 @@ static const struct mtk_ddp_comp_funcs ddp_merge = {
>  	.config = mtk_merge_config,
>  };
>  
> +static const struct mtk_ddp_comp_funcs ddp_dsc = {
> +	.config = mtk_dsc_config,
> +	.start = mtk_dsc_start,
> +	.stop = mtk_dsc_stop,
> +	.clk_enable = mtk_dsc_clk_enable,
> +	.clk_disable = mtk_dsc_clk_disable,
> +};
> +
>  static const struct mtk_ddp_comp_funcs ddp_ufoe = {
>  	.clk_enable = mtk_ddp_clk_enable,
>  	.clk_disable = mtk_ddp_clk_disable,
> @@ -371,6 +379,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
>  	[MTK_DISP_OD] = "od",
>  	[MTK_DISP_BLS] = "bls",
>  	[MTK_DISP_MERGE] = "merge",
> +	[MTK_DISP_DSC] = "dsc",
>  };
>  
>  struct mtk_ddp_comp_match {
> @@ -412,6 +421,9 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
>  	[DDP_COMPONENT_MERGE3]	= { MTK_DISP_MERGE,	3, &ddp_merge },
>  	[DDP_COMPONENT_MERGE4]	= { MTK_DISP_MERGE,	4, &ddp_merge },
>  	[DDP_COMPONENT_MERGE5]	= { MTK_DISP_MERGE,	5, &ddp_merge },
> +	[DDP_COMPONENT_DSC0]	= { MTK_DISP_DSC,	0, &ddp_dsc },
> +	[DDP_COMPONENT_DSC1]	= { MTK_DISP_DSC,	1, &ddp_dsc },
> +	[DDP_COMPONENT_DSC1_VIRTUAL0]	= { MTK_DISP_DSC,	-1, &ddp_dsc },
>  	[DDP_COMPONENT_UFOE]	= { MTK_DISP_UFOE,	0, &ddp_ufoe },
>  	[DDP_COMPONENT_WDMA0]	= { MTK_DISP_WDMA,	0, NULL },
>  	[DDP_COMPONENT_WDMA1]	= { MTK_DISP_WDMA,	1, NULL },
> @@ -531,6 +543,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
>  	    type == MTK_DISP_COLOR ||
>  	    type == MTK_DISP_GAMMA ||
>  	    type == MTK_DISP_MERGE ||
> +	    type == MTK_DISP_DSC ||
>  	    type == MTK_DPI ||
>  	    type == MTK_DSI ||
>  	    type == MTK_DISP_OVL ||
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index 038775b4531b..b4f6b52dac69 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -35,6 +35,7 @@ enum mtk_ddp_comp_type {
>  	MTK_DISP_OD,
>  	MTK_DISP_BLS,
>  	MTK_DISP_MERGE,
> +	MTK_DISP_DSC,
>  	MTK_DDP_COMP_TYPE_MAX,
>  };
>  
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index f891316008aa..af3e69e0edbe 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -464,6 +464,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
>  	  .data = (void *)MTK_DISP_DITHER },
>  	{ .compatible = "mediatek,mt8195-disp-merge",
>  	  .data = (void *)MTK_DISP_MERGE },
> +	{ .compatible = "mediatek,mt8195-disp-dsc",
> +	  .data = (void *)MTK_DISP_DSC },
>  	{ .compatible = "mediatek,mt8173-disp-ufoe",
>  	  .data = (void *)MTK_DISP_UFOE },
>  	{ .compatible = "mediatek,mt2701-dsi",
> @@ -582,6 +584,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
>  		    comp_type == MTK_DISP_COLOR ||
>  		    comp_type == MTK_DISP_GAMMA ||
>  		    comp_type == MTK_DISP_MERGE ||
> +		    comp_type == MTK_DISP_DSC ||
>  		    comp_type == MTK_DISP_OVL ||
>  		    comp_type == MTK_DISP_OVL_2L ||
>  		    comp_type == MTK_DISP_RDMA ||
> @@ -687,6 +690,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
>  	&mtk_dpi_driver,
>  	&mtk_drm_platform_driver,
>  	&mtk_disp_merge_driver,
> +	&mtk_disp_dsc_driver,
>  	&mtk_dsi_driver,
>  };
>  
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index 18548a373626..7f821b96aac3 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -52,6 +52,7 @@ extern struct platform_driver mtk_disp_gamma_driver;
>  extern struct platform_driver mtk_disp_ovl_driver;
>  extern struct platform_driver mtk_disp_rdma_driver;
>  extern struct platform_driver mtk_disp_merge_driver;
> +extern struct platform_driver mtk_disp_dsc_driver;
>  extern struct platform_driver mtk_dpi_driver;
>  extern struct platform_driver mtk_dsi_driver;
>  
> diff --git a/drivers/gpu/drm/mediatek/mtk_panel_ext.c b/drivers/gpu/drm/mediatek/mtk_panel_ext.c
> new file mode 100644
> index 000000000000..5887a1cd08bc
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_panel_ext.c
> @@ -0,0 +1,136 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2019 MediaTek Inc.
> + */
> +
> +#include <linux/err.h>
> +#include <linux/module.h>
> +
> +#include <drm/drm_atomic_helper.h>
> +#include <drm/drm_crtc_helper.h>
> +#include <drm/drm_mipi_dsi.h>
> +
> +#include <drm/drm_panel.h>
> +
> +#include "mtk_panel_ext.h"
> +
> +struct _panel_rst_ctx {
> +	struct drm_panel *panel;
> +	panel_tch_rst rst_cb;
> +};
> +
> +static DEFINE_MUTEX(panel_ext_lock);
> +static LIST_HEAD(panel_ext_list);
> +static struct _panel_rst_ctx panel_rst_ctx;
> +
> +void mtk_panel_init(struct mtk_panel_ctx *ctx)
> +{
> +	INIT_LIST_HEAD(&ctx->list);
> +}
> +
> +void mtk_panel_add(struct mtk_panel_ctx *ctx)
> +{
> +	mutex_lock(&panel_ext_lock);
> +	list_add_tail(&ctx->list, &panel_ext_list);
> +	mutex_unlock(&panel_ext_lock);
> +}
> +
> +void mtk_panel_remove(struct mtk_panel_ctx *ctx)
> +{
> +	mutex_lock(&panel_ext_lock);
> +	list_del_init(&ctx->list);
> +	mutex_unlock(&panel_ext_lock);
> +}
> +
> +int mtk_panel_attach(struct mtk_panel_ctx *ctx, struct drm_panel *panel)
> +{
> +	if (ctx->panel)
> +		return -EBUSY;
> +
> +	ctx->panel = panel;
> +
> +	return 0;
> +}
> +
> +int mtk_panel_tch_handle_reg(struct drm_panel *panel)
> +{
> +	mutex_lock(&panel_ext_lock);
> +	if (panel_rst_ctx.panel) {
> +		mutex_unlock(&panel_ext_lock);
> +		return -EEXIST;
> +	}
> +	panel_rst_ctx.panel = panel;
> +	mutex_unlock(&panel_ext_lock);
> +
> +	return 0;
> +}
> +
> +void **mtk_panel_tch_handle_init(void)
> +{
> +	return (void **)&panel_rst_ctx.rst_cb;
> +}
> +
> +int mtk_panel_tch_rst(struct drm_panel *panel)
> +{
> +	int ret = 0;
> +
> +	mutex_lock(&panel_ext_lock);
> +	if (panel_rst_ctx.rst_cb && panel_rst_ctx.panel == panel)
> +		panel_rst_ctx.rst_cb();
> +	else
> +		ret = -EEXIST;
> +	mutex_unlock(&panel_ext_lock);
> +
> +	return ret;
> +}
> +
> +int mtk_panel_detach(struct mtk_panel_ctx *ctx)
> +{
> +	ctx->panel = NULL;
> +
> +	return 0;
> +}
> +
> +int mtk_panel_ext_create(struct device *dev,
> +			 struct mtk_panel_params *ext_params,
> +			 struct mtk_panel_funcs *ext_funcs,
> +			 struct drm_panel *panel)
> +{
> +	struct mtk_panel_ctx *ext_ctx;
> +	struct mtk_panel_ext *ext;
> +
> +	ext_ctx = devm_kzalloc(dev, sizeof(struct mtk_panel_ctx), GFP_KERNEL);
> +	if (!ext_ctx)
> +		return -ENOMEM;
> +
> +	ext = devm_kzalloc(dev, sizeof(struct mtk_panel_ext), GFP_KERNEL);
> +	if (!ext)
> +		return -ENOMEM;
> +
> +	mtk_panel_init(ext_ctx);
> +	ext->params = ext_params;
> +	ext->funcs = ext_funcs;
> +	ext_ctx->ext = ext;
> +
> +	mtk_panel_add(ext_ctx);
> +	mtk_panel_attach(ext_ctx, panel);
> +
> +	return 0;
> +}
> +
> +struct mtk_panel_ext *find_panel_ext(struct drm_panel *panel)
> +{
> +	struct mtk_panel_ctx *ctx;
> +
> +	mutex_lock(&panel_ext_lock);
> +
> +	list_for_each_entry(ctx, &panel_ext_list, list) {
> +		if (ctx->panel == panel) {
> +			mutex_unlock(&panel_ext_lock);
> +			return ctx->ext;
> +		}
> +	}
> +
> +	mutex_unlock(&panel_ext_lock);
> +	return NULL;
> +}
> diff --git a/drivers/gpu/drm/mediatek/mtk_panel_ext.h b/drivers/gpu/drm/mediatek/mtk_panel_ext.h
> new file mode 100644
> index 000000000000..f828d468817d
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_panel_ext.h
> @@ -0,0 +1,344 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2019 MediaTek Inc.
> + */
> +
> +#ifndef __MTK_PANEL_EXT_H__
> +#define __MTK_PANEL_EXT_H__
> +
> +#include <drm/drm_panel.h>
> +
> +#define RT_MAX_NUM 10
> +#define ESD_CHECK_NUM 3
> +#define MAX_TX_CMD_NUM 20
> +#define MAX_RX_CMD_NUM 20
> +#define READ_DDIC_SLOT_NUM 4
> +#define MAX_DYN_CMD_NUM 20
> +
> +struct mtk_dsi;
> +struct cmdq_pkt;
> +struct mtk_panel_para_table {
> +	u8 count;
> +	u8 para_list[64];
> +};
> +
> +/*
> + *	DSI data type:
> + *	DSI_DCS_WRITE_SHORT_PACKET_NO_PARAM		0x05
> + *	DSI_DCS_WRITE_SHORT_PACKET_1_PARAM		0x15
> + *	DSI_DCS_WRITE_LONG_PACKET				0x39
> + *	DSI_DCS_READ_NO_PARAM					0x06
> +
> + *	DSI_GERNERIC_WRITE_SHORT_NO_PARAM		0x03
> + *	DSI_GERNERIC_WRITE_SHORT_1_PARAM		0x13
> + *	DSI_GERNERIC_WRITE_SHORT_1_PARAM		0x23
> + *	DSI_GERNERIC_WRITE_LONG_PACKET			0x29
> + *	DSI_GERNERIC_READ_NO_PARAM				0x04
> + *	DSI_GERNERIC_READ_1_PARAM				0x14
> + *	DSI_GERNERIC_READ_2_PARAM				0x24
> + */
> +
> +/**
> + * struct mtk_ddic_dsi_msg - MTK write/read DDIC RG cmd buffer
> + * @channel: virtual channel id
> + * @flags: flags controlling this message transmission
> + * @type: payload data type array
> + * @tx_len: length of @tx_buf
> + * @tx_buf: data array to be written
> + * @tx_cmd_num: tx cmd number
> + * @rx_len: length of @rx_buf
> + * @rx_buf: data array to be read, or NULL
> + * @rx_cmd_num: rx cmd number
> + */
> +struct mtk_ddic_dsi_msg {
> +	u8 channel;
> +	u16 flags;
> +
> +	u8 type[MAX_TX_CMD_NUM];
> +	size_t tx_len[MAX_TX_CMD_NUM];
> +	const void *tx_buf[MAX_TX_CMD_NUM];
> +	size_t tx_cmd_num;
> +
> +	size_t rx_len[MAX_RX_CMD_NUM];
> +	void *rx_buf[MAX_RX_CMD_NUM];
> +	size_t rx_cmd_num;
> +};
> +
> +struct DSI_RX_DATA_REG {
> +	unsigned char byte0;
> +	unsigned char byte1;
> +	unsigned char byte2;
> +	unsigned char byte3;
> +};
> +
> +typedef void (*dcs_write_gce) (struct mtk_dsi *dsi, struct cmdq_pkt *handle,
> +				const void *data, size_t len);
> +typedef void (*dcs_grp_write_gce) (struct mtk_dsi *dsi, struct cmdq_pkt *handle,
> +				struct mtk_panel_para_table *para_table,
> +				unsigned int para_size);
> +typedef int (*panel_tch_rst) (void);
> +
> +enum MTK_PANEL_OUTPUT_MODE {
> +	MTK_PANEL_SINGLE_PORT = 0x0,
> +	MTK_PANEL_DSC_SINGLE_PORT,
> +	MTK_PANEL_DUAL_PORT,
> +};
> +
> +struct esd_check_item {
> +	unsigned char cmd;
> +	unsigned char count;
> +	unsigned char para_list[RT_MAX_NUM];
> +	unsigned char mask_list[RT_MAX_NUM];
> +};
> +
> +enum MTK_PANEL_MODE_SWITCH_STAGE {
> +	BEFORE_DSI_POWERDOWN,
> +	AFTER_DSI_POWERON,
> +};
> +
> +enum MIPITX_PHY_PORT {
> +	MIPITX_PHY_PORT_0 = 0,
> +	MIPITX_PHY_PORT_1,
> +	MIPITX_PHY_PORT_NUM
> +};
> +
> +enum MIPITX_PHY_LANE_SWAP {
> +	MIPITX_PHY_LANE_0 = 0,
> +	MIPITX_PHY_LANE_1,
> +	MIPITX_PHY_LANE_2,
> +	MIPITX_PHY_LANE_3,
> +	MIPITX_PHY_LANE_CK,
> +	MIPITX_PHY_LANE_RX,
> +	MIPITX_PHY_LANE_NUM
> +};
> +
> +enum FPS_CHANGE_INDEX {
> +	DYNFPS_NOT_DEFINED = 0,
> +	DYNFPS_DSI_VFP = 1,
> +	DYNFPS_DSI_HFP = 2,
> +	DYNFPS_DSI_MIPI_CLK = 4,
> +};
> +
> +struct mtk_panel_dsc_params {
> +	unsigned int enable;
> +	unsigned int ver; /* [7:4] major [3:0] minor */
> +	unsigned int slice_mode;
> +	unsigned int rgb_swap;
> +	unsigned int dsc_cfg;
> +	unsigned int rct_on;
> +	unsigned int bit_per_channel;
> +	unsigned int dsc_line_buf_depth;
> +	unsigned int bp_enable;
> +	unsigned int bit_per_pixel;
> +	unsigned int pic_height; /* need to check */
> +	unsigned int pic_width;  /* need to check */
> +	unsigned int slice_height;
> +	unsigned int slice_width;
> +	unsigned int chunk_size;
> +	unsigned int xmit_delay;
> +	unsigned int dec_delay;
> +	unsigned int scale_value;
> +	unsigned int increment_interval;
> +	unsigned int decrement_interval;
> +	unsigned int line_bpg_offset;
> +	unsigned int nfl_bpg_offset;
> +	unsigned int slice_bpg_offset;
> +	unsigned int initial_offset;
> +	unsigned int final_offset;
> +	unsigned int flatness_minqp;
> +	unsigned int flatness_maxqp;
> +	unsigned int rc_model_size;
> +	unsigned int rc_edge_factor;
> +	unsigned int rc_quant_incr_limit0;
> +	unsigned int rc_quant_incr_limit1;
> +	unsigned int rc_tgt_offset_hi;
> +	unsigned int rc_tgt_offset_lo;
> +};
> +
> +struct mtk_dsi_phy_timcon {
> +	unsigned int hs_trail;
> +	unsigned int hs_prpr;
> +	unsigned int hs_zero;
> +	unsigned int lpx;
> +	unsigned int ta_get;
> +	unsigned int ta_sure;
> +	unsigned int ta_go;
> +	unsigned int da_hs_exit;
> +	unsigned int clk_trail;
> +	unsigned int cont_det;
> +	unsigned int da_hs_sync;
> +	unsigned int clk_zero;
> +	unsigned int clk_hs_prpr;
> +	unsigned int clk_hs_exit;
> +	unsigned int clk_hs_post;
> +};
> +
> +struct dynamic_mipi_params {
> +	unsigned int switch_en;
> +	unsigned int pll_clk;
> +	unsigned int data_rate;
> +
> +	unsigned int vsa;
> +	unsigned int vbp;
> +	unsigned int vfp;
> +	unsigned int vfp_lp_dyn;
> +
> +	unsigned int hsa;
> +	unsigned int hbp;
> +	unsigned int hfp;
> +};
> +
> +struct dfps_switch_cmd {
> +	unsigned int src_fps;
> +	unsigned int cmd_num;
> +	unsigned char para_list[64];
> +};
> +
> +struct dynamic_fps_params {
> +	unsigned int switch_en;
> +	unsigned int vact_timing_fps;
> +	struct dfps_switch_cmd dfps_cmd_table[MAX_DYN_CMD_NUM];
> +
> +	unsigned int lfr_enable;
> +	unsigned int lfr_minimum_fps;
> +};
> +
> +struct mtk_panel_params {
> +	unsigned int pll_clk;
> +	unsigned int data_rate;
> +	struct mtk_dsi_phy_timcon phy_timcon;
> +	unsigned int vfp_low_power;
> +	struct dynamic_mipi_params dyn;
> +	struct dynamic_fps_params dyn_fps;
> +	unsigned int cust_esd_check;
> +	unsigned int esd_check_enable;
> +	struct esd_check_item lcm_esd_check_table[ESD_CHECK_NUM];
> +	unsigned int ssc_disable;
> +	unsigned int ssc_range;
> +	int lcm_color_mode;
> +	unsigned int min_luminance;
> +	unsigned int average_luminance;
> +	unsigned int max_luminance;
> +	unsigned int round_corner_en;
> +	unsigned int corner_pattern_height;
> +	unsigned int corner_pattern_height_bot;
> +	unsigned int corner_pattern_tp_size;
> +	void *corner_pattern_lt_addr;
> +	unsigned int physical_width_um;
> +	unsigned int physical_height_um;
> +	unsigned int lane_swap_en;
> +	unsigned int is_cphy;
> +	enum MIPITX_PHY_LANE_SWAP
> +		lane_swap[MIPITX_PHY_PORT_NUM][MIPITX_PHY_LANE_NUM];
> +	struct mtk_panel_dsc_params dsc_params;
> +	unsigned int output_mode;
> +	unsigned int hbm_en_time;
> +	unsigned int hbm_dis_time;
> +	unsigned int lcm_index;
> +	unsigned int wait_sof_before_dec_vfp;
> +	unsigned int doze_delay;
> +};
> +
> +struct mtk_panel_ext {
> +	struct mtk_panel_funcs *funcs;
> +	struct mtk_panel_params *params;
> +};
> +
> +struct mtk_panel_ctx {
> +	struct drm_panel *panel;
> +	struct mtk_panel_ext *ext;
> +
> +	struct list_head list;
> +};
> +
> +struct mtk_panel_funcs {
> +	int (*set_backlight_cmdq)(void *dsi_drv, dcs_write_gce cb,
> +		 void *handle, unsigned int level);
> +	int (*set_aod_light_mode)(void *dsi_drv, dcs_write_gce cb,
> +		 void *handle, unsigned int mode);
> +	int (*set_backlight_grp_cmdq)(void *dsi_drv, dcs_grp_write_gce cb,
> +		 void *handle, unsigned int level);
> +	int (*reset)(struct drm_panel *panel, int on);
> +	int (*ata_check)(struct drm_panel *panel);
> +	int (*ext_param_set)(struct drm_panel *panel, unsigned int mode);
> +	int (*ext_param_get)(struct mtk_panel_params *ext_para,
> +		 unsigned int mode);
> +	int (*mode_switch)(struct drm_panel *panel, unsigned int cur_mode,
> +		 unsigned int dst_mode, enum MTK_PANEL_MODE_SWITCH_STAGE stage);
> +	int (*get_virtual_heigh)(void);
> +	int (*get_virtual_width)(void);
> +	/**
> +	 * @doze_enable_start:
> +	 *
> +	 * Call the @doze_enable_start before starting AOD mode.
> +	 * The LCM off may add here to avoid panel show unexpected
> +	 * content when switching to specific panel low power mode.
> +	 */
> +	int (*doze_enable_start)(struct drm_panel *panel,
> +		 void *dsi_drv, dcs_write_gce cb, void *handle);
> +
> +	/**
> +	 * @doze_enable:
> +	 *
> +	 * Call the @doze_enable starts AOD mode.
> +	 */
> +	int (*doze_enable)(struct drm_panel *panel,
> +		 void *dsi_drv, dcs_write_gce cb, void *handle);
> +
> +	/**
> +	 * @doze_disable:
> +	 *
> +	 * Call the @doze_disable before ending AOD mode.
> +	 */
> +	int (*doze_disable)(struct drm_panel *panel,
> +		 void *dsi_drv, dcs_write_gce cb, void *handle);
> +
> +	/**
> +	 * @doze_post_disp_on:
> +	 *
> +	 * In some situation, the LCM off may set in @doze_enable & @disable.
> +	 * After LCM switch to the new mode stable, system call
> +	 * @doze_post_disp_on to turn on panel.
> +	 */
> +	int (*doze_post_disp_on)(struct drm_panel *panel,
> +		 void *dsi_drv, dcs_write_gce cb, void *handle);
> +
> +	/**
> +	 * @doze_area:
> +	 *
> +	 * Send the panel area in command here.
> +	 */
> +	int (*doze_area)(struct drm_panel *panel,
> +		 void *dsi_drv, dcs_write_gce cb, void *handle);
> +
> +	/**
> +	 * @doze_get_mode_flags:
> +	 *
> +	 * If CV switch is needed for doze mode, fill the mode_flags in this
> +	 * function for both CMD and VDO mode.
> +	 */
> +	unsigned long (*doze_get_mode_flags)(struct drm_panel *panel,
> +				   int aod_en);
> +
> +	int (*hbm_set_cmdq)(struct drm_panel *panel, void *dsi_drv,
> +		 dcs_write_gce cb, void *handle, bool en);
> +	void (*hbm_get_state)(struct drm_panel *panel, bool *state);
> +	void (*hbm_get_wait_state)(struct drm_panel *panel, bool *wait);
> +	bool (*hbm_set_wait_state)(struct drm_panel *panel, bool wait);
> +};
> +
> +void mtk_panel_init(struct mtk_panel_ctx *ctx);
> +void mtk_panel_add(struct mtk_panel_ctx *ctx);
> +void mtk_panel_remove(struct mtk_panel_ctx *ctx);
> +int mtk_panel_attach(struct mtk_panel_ctx *ctx, struct drm_panel *panel);
> +int mtk_panel_detach(struct mtk_panel_ctx *ctx);
> +struct mtk_panel_ext *find_panel_ext(struct drm_panel *panel);
> +int mtk_panel_ext_create(struct device *dev,
> +			 struct mtk_panel_params *ext_params,
> +			 struct mtk_panel_funcs *ext_funcs,
> +			 struct drm_panel *panel);
> +int mtk_panel_tch_handle_reg(struct drm_panel *panel);
> +void **mtk_panel_tch_handle_init(void);
> +int mtk_panel_tch_rst(struct drm_panel *panel);

All mtk_panel_ext is useless, so remove.

> +
> +#endif
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h

Move mmsys part to another patch.

Regards,
CK

> index 47f3d0ea3c6c..73e9e8286d50 100644
> --- a/drivers/soc/mediatek/mt8195-mmsys.h
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -161,12 +161,30 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
>  	}, {
>  		DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
>  		MT8195_VDO0_OVL_MOUT_EN, MOUT_DISP_OVL1_TO_DISP_RDMA1
> +	}, {
> +		DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
> +		MT8195_VDO0_SEL_IN, SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
> +	}, {
> +		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
> +		MT8195_VDO0_SEL_IN, SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
> +	}, {
> +		DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
> +		MT8195_VDO0_SEL_IN, SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
>  	}, {
>  		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
>  		MT8195_VDO0_SEL_IN, SEL_IN_DSI0_FROM_DISP_DITHER0
> +	}, {
> +		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
> +		MT8195_VDO0_SEL_OUT, SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
>  	}, {
>  		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
>  		MT8195_VDO0_SEL_OUT, DDP_COMPONENT_DSI0
> +	}, {
> +		DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
> +		MT8195_VDO0_SEL_OUT, SOUT_DSC_WRAP0_OUT_TO_DSI0
> +	}, {
> +		DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
> +		MT8195_VDO0_SEL_OUT, SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
>  	}
>  };
>  
> diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
> index 84ece5486902..d74eb3f97f1d 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -285,6 +285,7 @@ static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
>  	[DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
>  	[DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
>  	[DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
> +	[DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
>  	[DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
>  	[DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
>  };
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index 3135ce82a7f7..89a625743737 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -45,6 +45,9 @@ enum mtk_ddp_comp_id {
>  	DDP_COMPONENT_MERGE3,
>  	DDP_COMPONENT_MERGE4,
>  	DDP_COMPONENT_MERGE5,
> +	DDP_COMPONENT_DSC0,
> +	DDP_COMPONENT_DSC1,
> +	DDP_COMPONENT_DSC1_VIRTUAL0,
>  	DDP_COMPONENT_ID_MAX,
>  };
>  

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^ permalink raw reply	[flat|nested] 42+ messages in thread

* Re: [PATCH v1 01/17] dt-bindings: mediatek: add definition for mt8195 display
  2021-07-07  4:33   ` CK Hu
@ 2021-07-10  6:57     ` Jason-JH Lin
  0 siblings, 0 replies; 42+ messages in thread
From: Jason-JH Lin @ 2021-07-10  6:57 UTC (permalink / raw)
  To: CK Hu
  Cc: chunkuang.hu, matthias.bgg, linux-arm-kernel, linux-mediatek,
	linux-kernel, devicetree, Project_Global_Chrome_Upstream_Group,
	fshao, nancy.lin, singo.chang

Hi CK,

OK, I'll resend this at the next version.

Regard,
Jason-JH.Lin


On Wed, 2021-07-07 at 12:33 +0800, CK Hu wrote:
> Hi, Jason:
> 
> 
> On Wed, 2021-07-07 at 12:12 +0800, jason-jh.lin wrote:
> > Add definition for mt8195 display and add DSC module description.
> 
> Break this patch to two patch. One is mt8195 display, another one is
> DSC
> and describe more about what is DSC.
> 
> Regards,
> CK
> 
> > 
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> >  .../bindings/display/mediatek/mediatek,disp.txt     | 13
> > +++++++++++--
> >  1 file changed, 11 insertions(+), 2 deletions(-)
> > 
> > diff --git
> > a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.
> > txt
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.
> > txt
> > index fbb59c9ddda6..a5859e7883d5 100644
> > ---
> > a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.
> > txt
> > +++
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.
> > txt
> > @@ -37,6 +37,7 @@ Required properties (all function blocks):
> >  	"mediatek,<chip>-disp-aal"   		- adaptive ambient
> > light controller
> >  	"mediatek,<chip>-disp-gamma" 		- gamma correction
> >  	"mediatek,<chip>-disp-merge" 		- merge streams
> > from two RDMA sources
> > +	"mediatek,<chip>-disp-dsc"		- compressing /
> > decompressing image display streams
> >  	"mediatek,<chip>-disp-postmask" 	- control round corner for
> > display frame
> >  	"mediatek,<chip>-disp-split" 		- split stream to
> > two encoders
> >  	"mediatek,<chip>-disp-ufoe"  		- data compression
> > engine
> > @@ -44,7 +45,7 @@ Required properties (all function blocks):
> >  	"mediatek,<chip>-dpi"        		- DPI controller,
> > see mediatek,dpi.txt
> >  	"mediatek,<chip>-disp-mutex" 		- display mutex
> >  	"mediatek,<chip>-disp-od"    		- overdrive
> > -  the supported chips are mt2701, mt7623, mt2712, mt8167, mt8173,
> > mt8183 and mt8192.
> > +  the supported chips are mt2701, mt7623, mt2712, mt8167, mt8173,
> > mt8183, mt8192 and mt8195.
> >  - reg: Physical base address and length of the function block
> > register space
> >  - interrupts: The interrupt signal from the function block
> > (required, except for
> >    merge and split function blocks).
> > @@ -60,7 +61,7 @@ Required properties (DMA function blocks):
> >  	"mediatek,<chip>-disp-ovl"
> >  	"mediatek,<chip>-disp-rdma"
> >  	"mediatek,<chip>-disp-wdma"
> > -  the supported chips are mt2701, mt8167 and mt8173.
> > +  the supported chips are mt2701, mt8167, mt8173 and mt8195.
> >  - larb: Should contain a phandle pointing to the local arbiter
> > device as defined
> >    in Documentation/devicetree/bindings/memory-
> > controllers/mediatek,smi-larb.yaml
> >  - iommus: Should point to the respective IOMMU block with master
> > port as
> > @@ -195,6 +196,14 @@ ufoe@1401a000 {
> >  	clocks = <&mmsys CLK_MM_DISP_UFOE>;
> >  };
> >  
> > +dsc0@1c009000 {
> > +	compatible = "mediatek,mt8195-disp-dsc";
> > +	reg = <0 0x1c009000 0 0x1000>;
> > +	interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH>;
> > +	power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> > +	clocks = <&mmsys CLK_VDO0_DSC_WRAP0>;
> > +};
> > +
> >  dsi0: dsi@1401b000 {
> >  	/* See mediatek,dsi.txt for details */
> >  };
> 
> 
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^ permalink raw reply	[flat|nested] 42+ messages in thread

* Re: [PATCH v1 04/17] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
  2021-07-07  4:44   ` CK Hu
@ 2021-07-10  6:58     ` Jason-JH Lin
  0 siblings, 0 replies; 42+ messages in thread
From: Jason-JH Lin @ 2021-07-10  6:58 UTC (permalink / raw)
  To: CK Hu
  Cc: chunkuang.hu, matthias.bgg, linux-arm-kernel, linux-mediatek,
	linux-kernel, devicetree, Project_Global_Chrome_Upstream_Group,
	fshao, nancy.lin, singo.chang

Hi CK,

OK, I'll move clock driver part out of this patch at the next version.

Regard,
Jason-JH.Lin

On Wed, 2021-07-07 at 12:44 +0800, CK Hu wrote:
> Hi, Jason:
> 
> On Wed, 2021-07-07 at 12:12 +0800, jason-jh.lin wrote:
> > 1. Add mtk-mmsys support for mt8195 vodsys0.
> > 2. Change the clock driver of vdosys0 is probed
> >    from the probe of mtk-mmsys.
> 
> Move clock driver part out of this patch. And ask chun-jie to squash
> clock driver modification to his patch [1].
> 
> [1]
> 
https://patchwork.kernel.org/project/linux-mediatek/patch/20210616224743.5109-16-chun-jie.chen@mediatek.com/
> 
> Regards,
> CK
> 
> > 
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> >  drivers/clk/mediatek/clk-mt8195-vdo0.c |  24 ++--
> >  drivers/soc/mediatek/mt8195-mmsys.h    | 173
> > +++++++++++++++++++++++++
> >  drivers/soc/mediatek/mtk-mmsys.c       |  11 ++
> >  3 files changed, 198 insertions(+), 10 deletions(-)
> >  create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
> > 
> > diff --git a/drivers/clk/mediatek/clk-mt8195-vdo0.c
> > b/drivers/clk/mediatek/clk-mt8195-vdo0.c
> > index 8e23f267a1e6..940be5377f70 100644
> > --- a/drivers/clk/mediatek/clk-mt8195-vdo0.c
> > +++ b/drivers/clk/mediatek/clk-mt8195-vdo0.c
> > @@ -94,20 +94,24 @@ static const struct mtk_clk_desc vdo0_desc = {
> >  	.num_clks = ARRAY_SIZE(vdo0_clks),
> >  };
> >  
> > -static const struct of_device_id of_match_clk_mt8195_vdo0[] = {
> > -	{
> > -		.compatible = "mediatek,mt8195-vdosys0",
> > -		.data = &vdo0_desc,
> > -	}, {
> > -		/* sentinel */
> > -	}
> > -};
> > +static int clk_mt8195_vdo0_probe(struct platform_device *pdev)
> > +{
> > +	struct device *dev = &pdev->dev;
> > +	struct device_node *node = dev->parent->of_node;
> > +	struct clk_onecell_data *clk_data;
> > +
> > +	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(vdo0_clks));
> > +
> > +	mtk_clk_register_gates(node, vdo0_clks, ARRAY_SIZE(vdo0_clks),
> > +			clk_data);
> > +
> > +	return of_clk_add_provider(node, of_clk_src_onecell_get,
> > clk_data);
> > +}
> >  
> >  static struct platform_driver clk_mt8195_vdo0_drv = {
> > -	.probe = mtk_clk_simple_probe,
> > +	.probe = clk_mt8195_vdo0_probe,
> >  	.driver = {
> >  		.name = "clk-mt8195-vdo0",
> > -		.of_match_table = of_match_clk_mt8195_vdo0,
> >  	},
> >  };
> >  
> > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> > b/drivers/soc/mediatek/mt8195-mmsys.h
> > new file mode 100644
> > index 000000000000..47f3d0ea3c6c
> > --- /dev/null
> > +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> > @@ -0,0 +1,173 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +
> > +#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
> > +#define __SOC_MEDIATEK_MT8195_MMSYS_H
> > +
> > +#define MT8195_VDO0_OVL_MOUT_EN					
> > 0xf14
> > +#define MOUT_DISP_OVL0_TO_DISP_RDMA0				
> > BIT(0)
> > +#define MOUT_DISP_OVL0_TO_DISP_WDMA0				
> > BIT(1)
> > +#define MOUT_DISP_OVL0_TO_DISP_OVL1				
> > BIT(2)
> > +#define MOUT_DISP_OVL1_TO_DISP_RDMA1				
> > BIT(4)
> > +#define MOUT_DISP_OVL1_TO_DISP_WDMA1				
> > BIT(5)
> > +#define MOUT_DISP_OVL1_TO_DISP_OVL0				
> > BIT(6)
> > +
> > +#define MT8195_VDO0_SEL_IN					0xf34
> > +#define SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT			
> > (0 << 0)
> > +#define SEL_IN_VPP_MERGE_FROM_DISP_DITHER1			(1 <<
> > 0)
> > +#define SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0			
> > (2 << 0)
> > +#define SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0			
> > (0 << 4)
> > +#define SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE			(1 <<
> > 4)
> > +#define SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1			
> > (0 << 5)
> > +#define SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE			(1 <<
> > 5)
> > +#define SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE			
> > (0 << 8)
> > +#define SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT			
> > (1 << 8)
> > +#define SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT			
> > (0 << 9)
> > +#define SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT			(0 <<
> > 12)
> > +#define SEL_IN_DP_INTF0_FROM_VPP_MERGE				
> > (1 << 12)
> > +#define SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0			(2 <<
> > 12)
> > +#define SEL_IN_DSI0_FROM_DSC_WRAP0_OUT				
> > (0 << 16)
> > +#define SEL_IN_DSI0_FROM_DISP_DITHER0				
> > (1 << 16)
> > +#define SEL_IN_DSI1_FROM_DSC_WRAP1_OUT				
> > (0 << 17)
> > +#define SEL_IN_DSI1_FROM_VPP_MERGE				(1 <<
> > 17)
> > +#define SEL_IN_DISP_WDMA1_FROM_DISP_OVL1			(0 <<
> > 20)
> > +#define SEL_IN_DISP_WDMA1_FROM_VPP_MERGE			(1 <<
> > 20)
> > +#define SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN			
> > (0 << 21)
> > +#define SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1			
> > (1 << 21)
> > +#define SEL_IN_DISP_WDMA0_FROM_DISP_OVL0			(0 <<
> > 22)
> > +#define SEL_IN_DISP_WDMA0_FROM_VPP_MERGE			(1 <<
> > 22)
> > +
> > +#define MT8195_VDO0_SEL_OUT					
> > 0xf38
> > +#define SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN			(0 <<
> > 0)
> > +#define SOUT_DISP_DITHER0_TO_DSI0				(1 <<
> > 0)
> > +#define SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN			(0 <<
> > 1)
> > +#define SOUT_DISP_DITHER1_TO_VPP_MERGE				
> > (1 << 1)
> > +#define SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT			(2 <<
> > 1)
> > +#define SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE				
> > (0 << 4)
> > +#define SOUT_VDO1_VIRTUAL0_TO_DP_INTF0				
> > (1 << 4)
> > +#define SOUT_VPP_MERGE_TO_DSI1					
> > (0 << 8)
> > +#define SOUT_VPP_MERGE_TO_DP_INTF0				(1 <<
> > 8)
> > +#define SOUT_VPP_MERGE_TO_SINA_VIRTUAL0				
> > (2 << 8)
> > +#define SOUT_VPP_MERGE_TO_DISP_WDMA1				
> > (3 << 8)
> > +#define SOUT_VPP_MERGE_TO_DSC_WRAP0_IN				
> > (4 << 8)
> > +#define SOUT_VPP_MERGE_TO_DSC_WRAP1_IN				
> > (0 << 11)
> > +#define SOUT_VPP_MERGE_TO_DISP_WDMA0				
> > (1 << 11)
> > +#define SOUT_DSC_WRAP0_OUT_TO_DSI0				(0 <<
> > 12)
> > +#define SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0			
> > (1 << 12)
> > +#define SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE				
> > (2 << 12)
> > +#define SOUT_DSC_WRAP1_OUT_TO_DSI1				(0 <<
> > 16)
> > +#define SOUT_DSC_WRAP1_OUT_TO_DP_INTF0				
> > (1 << 16)
> > +#define SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0			
> > (2 << 16)
> > +#define SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE				
> > (3 << 16)
> > +
> > +#define MT8195_VDO1_VPP3_ASYNC_SOUT				
> > 0xf54
> > +#define SOUT_TO_VPP_MERGE0_P0_SEL				(0 <<
> > 0)
> > +#define SOUT_TO_VPP_MERGE0_P1_SEL				(1 <<
> > 0)
> > +
> > +#define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL			0xf40
> > +#define SOUT_TO_HDR_VDO_FE0					
> > (0 << 0)
> > +
> > +#define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL			0xf44
> > +#define SOUT_TO_HDR_VDO_FE1					
> > (0 << 0)
> > +
> > +#define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL			0xf48
> > +#define SOUT_TO_HDR_GFX_FE0					
> > (0 << 0)
> > +
> > +#define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL			0xf4c
> > +#define SOUT_TO_HDR_GFX_FE1					
> > (0 << 0)
> > +
> > +#define MT8195_VDO1_MIXER_IN1_SOUT_SEL				
> > 0xf58
> > +#define MIXER_IN1_SOUT_TO_DISP_MIXER				
> > (0 << 0)
> > +
> > +#define MT8195_VDO1_MIXER_IN2_SOUT_SEL				
> > 0xf5c
> > +#define MIXER_IN2_SOUT_TO_DISP_MIXER				
> > (0 << 0)
> > +
> > +#define MT8195_VDO1_MIXER_IN3_SOUT_SEL				
> > 0xf60
> > +#define MIXER_IN3_SOUT_TO_DISP_MIXER				
> > (0 << 0)
> > +
> > +#define MT8195_VDO1_MIXER_IN4_SOUT_SEL				
> > 0xf64
> > +#define MIXER_IN4_SOUT_TO_DISP_MIXER				
> > (0 << 0)
> > +
> > +#define MT8195_VDO1_MIXER_OUT_SOUT_SEL				
> > 0xf34
> > +#define MIXER_SOUT_TO_HDR_VDO_BE0				(0 <<
> > 0)
> > +
> > +#define MT8195_VDO1_MERGE4_SOUT_SEL				
> > 0xf18
> > +#define MERGE4_SOUT_TO_VDOSYS0					
> > (0 << 0)
> > +#define MERGE4_SOUT_TO_DPI0_SEL					
> > (1 << 0)
> > +#define MERGE4_SOUT_TO_DPI1_SEL					
> > (2 << 0)
> > +#define MERGE4_SOUT_TO_DP_INTF0_SEL				
> > (3 << 0)
> > +
> > +#define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN			0xf04
> > +#define VPP_MERGE0_P0_SEL_IN_FROM_SVPP2				
> > (0 << 0)
> > +#define VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0			
> > (1 << 0)
> > +
> > +#define MT8195_VDO1_VPP_MERGE0_P1_SEL_IN			0xf08
> > +#define VPP_MERGE0_P1_SEL_IN_FROM_SVPP3				
> > (0 << 0)
> > +#define VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1			
> > (1 << 0)
> > +
> > +#define MT8195_VDO1_VPP_MERGE1_P0_SEL_IN			0xf3c
> > +#define VPP_MERGE1_P0_SEL_IN_FROM_VPP3_ASYNC_SOUT		(0 <<
> > 0)
> > +#define VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2			
> > (1 << 0)
> > +
> > +#define MT8195_VDO1_MIXER_IN1_SEL_IN				
> > 0xf24
> > +#define MIXER_IN1_SEL_IN_FROM_HDR_VDO_FE0			(0 <<
> > 0)
> > +#define MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT			
> > (1 << 0)
> > +
> > +#define MT8195_VDO1_MIXER_IN2_SEL_IN				
> > 0xf28
> > +#define MIXER_IN2_SEL_IN_FROM_HDR_VDO_FE1			(0 <<
> > 0)
> > +#define MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT			
> > (1 << 0)
> > +
> > +#define MT8195_VDO1_MIXER_IN3_SEL_IN				
> > 0xf2c
> > +#define MIXER_IN3_SEL_IN_FROM_HDR_GFX_FE0			(0 <<
> > 0)
> > +#define MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT			
> > (1 << 0)
> > +
> > +#define MT8195_VDO1_MIXER_IN4_SEL_IN				
> > 0xf30
> > +#define MIXER_IN4_SEL_IN_FROM_HDR_GFX_FE1			(0 <<
> > 0)
> > +#define MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT			
> > (1 << 0)
> > +
> > +#define MT8195_VDO1_MIXER_SOUT_SEL_IN				
> > 0xf68
> > +#define MIXER_SOUT_SEL_IN_FROM_DISP_MIXER			(0 <<
> > 0)
> > +#define MIXER_SOUT_SEL_IN_FROM_MIXER_IN1_SOUT			
> > (1 << 0)
> > +#define MIXER_SOUT_SEL_IN_FROM_MIXER_IN2_SOUT			
> > (2 << 0)
> > +#define MIXER_SOUT_SEL_IN_FROM_MIXER_IN3_SOUTR			
> > (3 << 0)
> > +#define MIXER_SOUT_SEL_IN_FROM_MIXER_IN4_SOUTR			
> > (4 << 0)
> > +
> > +#define MT8195_VDO1_MERGE4_ASYNC_SEL_IN				
> > 0xf50
> > +#define MERGE4_ASYNC_SEL_IN_FROM_HDR_VDO_BE0			
> > (0 << 0)
> > +#define MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT			
> > (1 << 0)
> > +#define MERGE4_ASYNC_SEL_IN_FROM_MERGE0_ASYNC_SOUT		(2 <<
> > 0)
> > +#define MERGE4_ASYNC_SEL_IN_FROM_MERGE1_ASYNC_SOUT		(3 <<
> > 0)
> > +#define MERGE4_ASYNC_SEL_IN_FROM_MERGE2_ASYNC_SOUT		(4 <<
> > 0)
> > +#define MERGE4_ASYNC_SEL_IN_FROM_MERGE3_ASYNC_SOUT		(5 <<
> > 0)
> > +
> > +#define MT8195_VDO1_DISP_DPI0_SEL_IN				
> > 0xf0c
> > +#define DISP_DPI0_SEL_IN_FROM_VPP_MERGE4_MOUT			
> > (0 << 0)
> > +#define DISP_DPI0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT		
> > (1 << 0)
> > +#define DISP_DPI0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT		
> > (2 << 0)
> > +
> > +#define MT8195_VDO1_DISP_DPI1_SEL_IN				
> > 0xf10
> > +#define DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT			
> > (0 << 0)
> > +#define DISP_DPI1_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT		
> > (1 << 0)
> > +#define DISP_DPI1_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT		
> > (2 << 0)
> > +
> > +#define MT8195_VDO1_DISP_DP_INTF0_SEL_IN			0xf14
> > +#define DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT		(0 <<
> > 0)
> > +#define DISP_DP_INTF0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT	(1 <<
> > 0)
> > +#define DISP_DP_INTF0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT	(2 <<
> > 0)
> > +
> > +static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[]
> > = {
> > +	{
> > +		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> > +		MT8195_VDO0_OVL_MOUT_EN, MOUT_DISP_OVL0_TO_DISP_RDMA0
> > +	}, {
> > +		DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
> > +		MT8195_VDO0_OVL_MOUT_EN, MOUT_DISP_OVL1_TO_DISP_RDMA1
> > +	}, {
> > +		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> > +		MT8195_VDO0_SEL_IN, SEL_IN_DSI0_FROM_DISP_DITHER0
> > +	}, {
> > +		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> > +		MT8195_VDO0_SEL_OUT, DDP_COMPONENT_DSI0
> > +	}
> > +};
> > +
> > +#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > b/drivers/soc/mediatek/mtk-mmsys.c
> > index 080660ef11bf..1fb241750897 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > @@ -13,6 +13,7 @@
> >  #include "mtk-mmsys.h"
> >  #include "mt8167-mmsys.h"
> >  #include "mt8183-mmsys.h"
> > +#include "mt8195-mmsys.h"
> >  
> >  static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data
> > = {
> >  	.clk_driver = "clk-mt2701-mm",
> > @@ -52,6 +53,12 @@ static const struct mtk_mmsys_driver_data
> > mt8183_mmsys_driver_data = {
> >  	.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
> >  };
> >  
> > +static const struct mtk_mmsys_driver_data
> > mt8195_vdosys0_driver_data = {
> > +	.clk_driver = "clk-mt8195-vdo0",
> > +	.routes = mmsys_mt8195_routing_table,
> > +	.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > +};
> > +
> >  struct mtk_mmsys {
> >  	void __iomem *regs;
> >  	const struct mtk_mmsys_driver_data *data;
> > @@ -157,6 +164,10 @@ static const struct of_device_id
> > of_match_mtk_mmsys[] = {
> >  		.compatible = "mediatek,mt8183-mmsys",
> >  		.data = &mt8183_mmsys_driver_data,
> >  	},
> > +	{
> > +		.compatible = "mediatek,mt8195-vdosys0",
> > +		.data = &mt8195_vdosys0_driver_data,
> > +	},
> >  	{ }
> >  };
> >  
> 
> 
-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 42+ messages in thread

* Re: [PATCH v1 05/17] drm/mediatek: add mediatek-drm of vdosys0 support for MT8195
  2021-07-07  4:48   ` CK Hu
@ 2021-07-10  6:59     ` Jason-JH Lin
  0 siblings, 0 replies; 42+ messages in thread
From: Jason-JH Lin @ 2021-07-10  6:59 UTC (permalink / raw)
  To: CK Hu
  Cc: chunkuang.hu, matthias.bgg, linux-arm-kernel, linux-mediatek,
	linux-kernel, devicetree, Project_Global_Chrome_Upstream_Group,
	fshao, nancy.lin, singo.chang

On Wed, 2021-07-07 at 12:48 +0800, CK Hu wrote:
> Hi, Jason:
> 
> On Wed, 2021-07-07 at 12:12 +0800, jason-jh.lin wrote:
> > Add mediatek-drm of vdosys0 support for MT8195.
> > 
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.c | 24
> > ++++++++++++++++++++++++
> >  1 file changed, 24 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > index b46bdb8985da..9074ce32912c 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > @@ -147,6 +147,23 @@ static const enum mtk_ddp_comp_id
> > mt8183_mtk_ddp_ext[] = {
> >  	DDP_COMPONENT_DPI0,
> >  };
> >  
> > +static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
> > +	DDP_COMPONENT_OVL0,
> > +	DDP_COMPONENT_RDMA0,
> > +	DDP_COMPONENT_COLOR0,
> > +	DDP_COMPONENT_CCORR,
> > +	DDP_COMPONENT_AAL0,
> > +	DDP_COMPONENT_GAMMA,
> > +	DDP_COMPONENT_DITHER,
> > +#ifdef CONFIG_MTK_DPTX_SUPPORT
> > +	DDP_COMPONENT_DSC0,
> > +	DDP_COMPONENT_MERGE0,
> > +	DDP_COMPONENT_DP_INTF0,
> > +#else
> 
> CONFIG_MTK_DPTX_SUPPORT is not defined, so remove this part.
> 
> Regards,
> CK
> 

Hi CK,

OK, I'll remove this part at the next version.

Regard,
Jason-JH.Lin

> > +	DDP_COMPONENT_DSI0,
> > +#endif
> > +};
> > +
> >  static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data
> > = {
> >  	.main_path = mt2701_mtk_ddp_main,
> >  	.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
> > @@ -186,6 +203,11 @@ static const struct mtk_mmsys_driver_data
> > mt8183_mmsys_driver_data = {
> >  	.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
> >  };
> >  
> > +static const struct mtk_mmsys_driver_data
> > mt8195_vdosys0_driver_data = {
> > +	.main_path = mt8195_mtk_ddp_main,
> > +	.main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
> > +};
> > +
> >  static int mtk_drm_kms_init(struct drm_device *drm)
> >  {
> >  	struct mtk_drm_private *private = drm->dev_private;
> > @@ -468,6 +490,8 @@ static const struct of_device_id
> > mtk_drm_of_ids[] = {
> >  	  .data = &mt8173_mmsys_driver_data},
> >  	{ .compatible = "mediatek,mt8183-mmsys",
> >  	  .data = &mt8183_mmsys_driver_data},
> > +	{.compatible = "mediatek,mt8195-vdosys0",
> > +	  .data = &mt8195_vdosys0_driver_data},
> >  	{ }
> >  };
> >  MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
> 
> 
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 42+ messages in thread

* Re: [PATCH v1 06/17] soc: mediatek: add mtk-mutex support for mt8195
  2021-07-07  4:52   ` CK Hu
@ 2021-07-10  7:01     ` Jason-JH Lin
  0 siblings, 0 replies; 42+ messages in thread
From: Jason-JH Lin @ 2021-07-10  7:01 UTC (permalink / raw)
  To: CK Hu
  Cc: chunkuang.hu, matthias.bgg, linux-arm-kernel, linux-mediatek,
	linux-kernel, devicetree, Project_Global_Chrome_Upstream_Group,
	fshao, nancy.lin, singo.chang

Hi CK,

OK, I'll separate DRM part at the next version.

Regard,
Jason-JH.Lin

On Wed, 2021-07-07 at 12:52 +0800, CK Hu wrote:
> Hi, Jason:
> 
> On Wed, 2021-07-07 at 12:12 +0800, jason-jh.lin wrote:
> > Add mtk-mutex support for mt8195.
> 
> Separate DRM part and SoC part into different patch.
> 
> Regards,
> CK
> 
> > 
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.c |   2 +
> >  drivers/soc/mediatek/mtk-mutex.c       | 105
> > +++++++++++++++++++++++--
> >  2 files changed, 102 insertions(+), 5 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > index 9074ce32912c..5b7ead493487 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > @@ -470,6 +470,8 @@ static const struct of_device_id
> > mtk_ddp_comp_dt_ids[] = {
> >  	  .data = (void *)MTK_DISP_MUTEX },
> >  	{ .compatible = "mediatek,mt8183-disp-mutex",
> >  	  .data = (void *)MTK_DISP_MUTEX },
> > +	{ .compatible = "mediatek,mt8195-disp-mutex",
> > +	  .data = (void *)MTK_DISP_MUTEX },
> >  	{ .compatible = "mediatek,mt2701-disp-pwm",
> >  	  .data = (void *)MTK_DISP_BLS },
> >  	{ .compatible = "mediatek,mt8173-disp-pwm",
> > diff --git a/drivers/soc/mediatek/mtk-mutex.c
> > b/drivers/soc/mediatek/mtk-mutex.c
> > index 2e4bcc300576..080bdabfb024 100644
> > --- a/drivers/soc/mediatek/mtk-mutex.c
> > +++ b/drivers/soc/mediatek/mtk-mutex.c
> > @@ -17,6 +17,9 @@
> >  #define MT8183_MUTEX0_MOD0			0x30
> >  #define MT8183_MUTEX0_SOF0			0x2c
> >  
> > +#define MT8195_DISP_MUTEX0_MOD0			0x30
> > +#define MT8195_DISP_MUTEX0_SOF			0x2c
> > +
> >  #define DISP_REG_MUTEX_EN(n)			(0x20 + 0x20 *
> > (n))
> >  #define DISP_REG_MUTEX(n)			(0x24 + 0x20 * (n))
> >  #define DISP_REG_MUTEX_RST(n)			(0x28 + 0x20 *
> > (n))
> > @@ -67,6 +70,36 @@
> >  #define MT8173_MUTEX_MOD_DISP_PWM1		24
> >  #define MT8173_MUTEX_MOD_DISP_OD		25
> >  
> > +#define MT8195_MUTEX_MOD_DISP_OVL0		0
> > +#define MT8195_MUTEX_MOD_DISP_WDMA0		1
> > +#define MT8195_MUTEX_MOD_DISP_RDMA0		2
> > +#define MT8195_MUTEX_MOD_DISP_COLOR0		3
> > +#define MT8195_MUTEX_MOD_DISP_CCORR0		4
> > +#define MT8195_MUTEX_MOD_DISP_AAL0		5
> > +#define MT8195_MUTEX_MOD_DISP_GAMMA0		6
> > +#define MT8195_MUTEX_MOD_DISP_DITHER0		7
> > +#define MT8195_MUTEX_MOD_DISP_DSI0		8
> > +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0	9
> > +#define MT8195_MUTEX_MOD_DISP_OVL1		10
> > +#define MT8195_MUTEX_MOD_DISP_WDMA1		11
> > +#define MT8195_MUTEX_MOD_DISP_RDMA1		12
> > +#define MT8195_MUTEX_MOD_DISP_COLOR1		13
> > +#define MT8195_MUTEX_MOD_DISP_CCORR1		14
> > +#define MT8195_MUTEX_MOD_DISP_AAL1		15
> > +#define MT8195_MUTEX_MOD_DISP_GAMMA1		16
> > +#define MT8195_MUTEX_MOD_DISP_DITHER1		17
> > +#define MT8195_MUTEX_MOD_DISP_DSI1		18
> > +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1	19
> > +#define MT8195_MUTEX_MOD_DISP_VPP_MERGE		20
> > +#define MT8195_MUTEX_MOD_DISP_DP_INTF0		21
> > +#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0	22
> > +#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1	23
> > +#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2	24
> > +#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3	25
> > +#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4	26
> > +#define MT8195_MUTEX_MOD_DISP_PWM0		27
> > +#define MT8195_MUTEX_MOD_DISP_PWM1		28
> > +
> >  #define MT2712_MUTEX_MOD_DISP_PWM2		10
> >  #define MT2712_MUTEX_MOD_DISP_OVL0		11
> >  #define MT2712_MUTEX_MOD_DISP_OVL1		12
> > @@ -101,11 +134,36 @@
> >  #define MT2712_MUTEX_SOF_DSI3			6
> >  #define MT8167_MUTEX_SOF_DPI0			2
> >  #define MT8167_MUTEX_SOF_DPI1			3
> > +
> >  #define MT8183_MUTEX_SOF_DSI0			1
> >  #define MT8183_MUTEX_SOF_DPI0			2
> >  
> > -#define MT8183_MUTEX_EOF_DSI0			(MT8183_MUTEX_S
> > OF_DSI0 << 6)
> > -#define MT8183_MUTEX_EOF_DPI0			(MT8183_MUTEX_S
> > OF_DPI0 << 6)
> > +#define MT8183_MUTEX_EOF_CONVERT(sof)	((sof) << 6)
> > +#define MT8183_MUTEX_EOF_DSI0 \
> > +	MT8183_MUTEX_EOF_CONVERT(MT8183_MUTEX_SOF_DSI0)
> > +#define MT8183_MUTEX_EOF_DPI0 \
> > +	MT8183_MUTEX_EOF_CONVERT(MT8183_MUTEX_SOF_DPI0)
> > +
> > +#define MT8195_MUTEX_SOF_DSI0			1
> > +#define MT8195_MUTEX_SOF_DSI1			2
> > +#define MT8195_MUTEX_SOF_DP_INTF0		3
> > +#define MT8195_MUTEX_SOF_DP_INTF1		4
> > +#define MT8195_MUTEX_SOF_DPI0			6 /* for
> > HDMI_TX */
> > +#define MT8195_MUTEX_SOF_DPI1			5 /* for
> > digital video out */
> > +
> > +#define MT8195_MUTEX_EOF_CONVERT(sof)	((sof) << 7)
> > +#define MT8195_MUTEX_EOF_DSI0 \
> > +	MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DSI0)
> > +#define MT8195_MUTEX_EOF_DSI1 \
> > +	MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DSI1)
> > +#define MT8195_MUTEX_EOF_DP_INTF0 \
> > +	MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DP_INTF0)
> > +#define MT8195_MUTEX_EOF_DP_INTF1 \
> > +	MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DP_INTF1)
> > +#define MT8195_MUTEX_EOF_DPI0 \
> > +	MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DPI0)
> > +#define MT8195_MUTEX_EOF_DPI1 \
> > +	MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DPI1)
> >  
> >  struct mtk_mutex {
> >  	int id;
> > @@ -120,6 +178,9 @@ enum mtk_mutex_sof_id {
> >  	MUTEX_SOF_DPI1,
> >  	MUTEX_SOF_DSI2,
> >  	MUTEX_SOF_DSI3,
> > +	MUTEX_SOF_DP_INTF0,
> > +	MUTEX_SOF_DP_INTF1,
> > +	DDP_MUTEX_SOF_MAX,
> >  };
> >  
> >  struct mtk_mutex_data {
> > @@ -214,7 +275,20 @@ static const unsigned int
> > mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> >  	[DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
> >  };
> >  
> > -static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> > +static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] =
> > {
> > +	[DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
> > +	[DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
> > +	[DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
> > +	[DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0,
> > +	[DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
> > +	[DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
> > +	[DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
> > +	[DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
> > +	[DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
> > +	[DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
> > +};
> > +
> > +static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> >  	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> >  	[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
> >  	[MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
> > @@ -224,7 +298,7 @@ static const unsigned int
> > mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> >  	[MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
> >  };
> >  
> > -static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> > +static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> >  	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> >  	[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
> >  	[MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
> > @@ -232,12 +306,24 @@ static const unsigned int
> > mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> >  };
> >  
> >  /* Add EOF setting so overlay hardware can receive frame done irq
> > */
> > -static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> > +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> >  	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> >  	[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
> >  	[MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 |
> > MT8183_MUTEX_EOF_DPI0,
> >  };
> >  
> > +static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> > +	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> > +	[MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 |
> > MT8195_MUTEX_EOF_DSI0,
> > +	[MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 |
> > MT8195_MUTEX_EOF_DSI1,
> > +	[MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 |
> > MT8195_MUTEX_EOF_DPI0,
> > +	[MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 |
> > MT8195_MUTEX_EOF_DPI1,
> > +	[MUTEX_SOF_DP_INTF0] =
> > +		MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0,
> > +	[MUTEX_SOF_DP_INTF1] =
> > +		MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1,
> > +};
> > +
> >  static const struct mtk_mutex_data mt2701_mutex_driver_data = {
> >  	.mutex_mod = mt2701_mutex_mod,
> >  	.mutex_sof = mt2712_mutex_sof,
> > @@ -275,6 +361,13 @@ static const struct mtk_mutex_data
> > mt8183_mutex_driver_data = {
> >  	.no_clk = true,
> >  };
> >  
> > +static const struct mtk_mutex_data mt8195_mutex_driver_data = {
> > +	.mutex_mod = mt8195_mutex_mod,
> > +	.mutex_sof = mt8195_mutex_sof,
> > +	.mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
> > +	.mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
> > +};
> > +
> >  struct mtk_mutex *mtk_mutex_get(struct device *dev)
> >  {
> >  	struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
> > @@ -507,6 +600,8 @@ static const struct of_device_id
> > mutex_driver_dt_match[] = {
> >  	  .data = &mt8173_mutex_driver_data},
> >  	{ .compatible = "mediatek,mt8183-disp-mutex",
> >  	  .data = &mt8183_mutex_driver_data},
> > +	{ .compatible = "mediatek,mt8195-disp-mutex",
> > +	  .data = &mt8195_mutex_driver_data},
> >  	{},
> >  };
> >  MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
> 
> 
_______________________________________________
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^ permalink raw reply	[flat|nested] 42+ messages in thread

* Re: [PATCH v1 07/17] drm/mediatek: add OVL support for MT8195
  2021-07-07  5:03   ` CK Hu
@ 2021-07-10  7:05     ` Jason-JH Lin
  0 siblings, 0 replies; 42+ messages in thread
From: Jason-JH Lin @ 2021-07-10  7:05 UTC (permalink / raw)
  To: CK Hu
  Cc: chunkuang.hu, matthias.bgg, linux-arm-kernel, linux-mediatek,
	linux-kernel, Project_Global_Chrome_Upstream_Group, fshao,
	nancy.lin, singo.chang

On Wed, 2021-07-07 at 13:03 +0800, CK Hu wrote:
> Hi, Jason:
> 
> On Wed, 2021-07-07 at 12:12 +0800, jason-jh.lin wrote:
> > Add OVL support for MT8195.
> > 
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 9 +++++++++
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.c  | 2 ++
> >  2 files changed, 11 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > index 961f87f8d4d1..99c39487026d 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > @@ -455,6 +455,13 @@ static const struct mtk_disp_ovl_data
> > mt8183_ovl_2l_driver_data = {
> >  	.fmt_rgb565_is_0 = true,
> >  };
> >  
> > +static const struct mtk_disp_ovl_data mt8195_ovl_driver_data = {
> > +	.addr = DISP_REG_OVL_ADDR_MT8173,
> > +	.gmc_bits = 10,
> > +	.layer_nr = 4,
> > +	.fmt_rgb565_is_0 = true,
> > +};
> 
> mt8195_ovl_driver_data is identical to mt8183_ovl_driver_data, so
> remove
> mt8195_ovl_driver_data and use mt8183_ovl_driver_data.
> 
> > +
> >  static const struct of_device_id mtk_disp_ovl_driver_dt_match[] =
> > {
> >  	{ .compatible = "mediatek,mt2701-disp-ovl",
> >  	  .data = &mt2701_ovl_driver_data},
> > @@ -464,6 +471,8 @@ static const struct of_device_id
> > mtk_disp_ovl_driver_dt_match[] = {
> >  	  .data = &mt8183_ovl_driver_data},
> >  	{ .compatible = "mediatek,mt8183-disp-ovl-2l",
> >  	  .data = &mt8183_ovl_2l_driver_data},
> > +	{ .compatible = "mediatek,mt8195-disp-ovl",
> > +	  .data = &mt8195_ovl_driver_data},
> 
> One question, is mediatek,mt8195-disp-ovl identical to
> mediatek,mt8183-disp-ovl in hardware function? If so, use the
> compatible
> as
> 
> compatible = "mediatek,mt8195-disp-ovl", "mediatek,mt8183-disp-ovl";
> 
> And driver just keep "mediatek,mt8183-disp-ovl" and remove
> "mediatek,mt8195-disp-ovl".
> 
> If the hardware function has some different, just forget this.
> 
> Regards,
> CK
> 
Hi CK,

OK, I'll remove this patch at the next version.

Regard,
Jason-JH.Lin
> >  	{},
> >  };
> >  MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match);
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > index 5b7ead493487..65038d5b19cb 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > @@ -424,6 +424,8 @@ static const struct of_device_id
> > mtk_ddp_comp_dt_ids[] = {
> >  	  .data = (void *)MTK_DISP_OVL },
> >  	{ .compatible = "mediatek,mt8183-disp-ovl",
> >  	  .data = (void *)MTK_DISP_OVL },
> > +	{ .compatible = "mediatek,mt8195-disp-ovl",
> > +	  .data = (void *)MTK_DISP_OVL },
> >  	{ .compatible = "mediatek,mt8183-disp-ovl-2l",
> >  	  .data = (void *)MTK_DISP_OVL_2L },
> >  	{ .compatible = "mediatek,mt2701-disp-rdma",
> 
> 
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^ permalink raw reply	[flat|nested] 42+ messages in thread

* Re: [PATCH v1 08/17] drm/mediatek: Add component_del in OVL remove function
  2021-07-07  5:12   ` CK Hu
@ 2021-07-10  7:06     ` Jason-JH Lin
  0 siblings, 0 replies; 42+ messages in thread
From: Jason-JH Lin @ 2021-07-10  7:06 UTC (permalink / raw)
  To: CK Hu
  Cc: chunkuang.hu, matthias.bgg, linux-arm-kernel, linux-mediatek,
	linux-kernel, Project_Global_Chrome_Upstream_Group, fshao,
	nancy.lin, singo.chang

On Wed, 2021-07-07 at 13:12 +0800, CK Hu wrote:
> Hi, Jason:
> 
> On Wed, 2021-07-07 at 12:12 +0800, jason-jh.lin wrote:
> > Add component_del in OVL remove function.
> > 
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > index 99c39487026d..7504e86b167a 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > @@ -158,7 +158,6 @@ void mtk_ovl_stop(struct device *dev)
> >  		reg = reg & ~OVL_LAYER_SMI_ID_EN;
> >  		writel_relaxed(reg, ovl->regs +
> > DISP_REG_OVL_DATAPATH_CON);
> >  	}
> > -
> 
> This modification is not related to this patch, so move out of this
> patch.
> 
Hi CK,

OK, I'll remove this patch at the next version.

Regard,
Jason-JH.Lin
> >  }
> >  
> >  void mtk_ovl_config(struct device *dev, unsigned int w,
> > @@ -424,6 +423,8 @@ static int mtk_disp_ovl_probe(struct
> > platform_device *pdev)
> >  
> >  static int mtk_disp_ovl_remove(struct platform_device *pdev)
> >  {
> > +	component_del(&pdev->dev, &mtk_disp_ovl_component_ops);
> > +
> 
> This is a fix-up of patch [1]. Change this patch to fix all sub
> drivers,
> add Fixes tag, and move this patch out of this series. (This fix-up
> is
> not related to mt8195, so send this patch independently).
> 
> [1]
> 
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?h=v5.13&id=ff1395609e20c1cd98b3ec65d16dc18f0471dca3
> 
> Regards,
> CK
> 
> >  	return 0;
> >  }
> >  
> 
> 
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^ permalink raw reply	[flat|nested] 42+ messages in thread

* Re: [PATCH v1 09/17] drm/mediatek: add OVL support multi-layer
  2021-07-07  5:43   ` CK Hu
@ 2021-07-10  7:17     ` Jason-JH Lin
  0 siblings, 0 replies; 42+ messages in thread
From: Jason-JH Lin @ 2021-07-10  7:17 UTC (permalink / raw)
  To: CK Hu
  Cc: chunkuang.hu, matthias.bgg, linux-arm-kernel, linux-mediatek,
	linux-kernel, Project_Global_Chrome_Upstream_Group, fshao,
	nancy.lin, singo.chang

On Wed, 2021-07-07 at 13:43 +0800, CK Hu wrote:
> Hi, Jason:
> 
> On Wed, 2021-07-07 at 12:12 +0800, jason-jh.lin wrote:
> > Add datapath_con settings to support multi-layer output.
> 
> 
> What is multi-layer output? Why we need this?
> 
Hi CK,

This patch is not the multi-layer output fix up patch.
The fix up patch is this one:

https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/commit/drivers/gpu/drm/mediatek/mtk_disp_ovl.c?h=mediatek-drm-next&id=d41ff4dcf093885dcc253e3861834eea294827cb

So this patch is not necessary for mt8195 DRM series patches.
I'll remove this patch at the next version.

By the way, this patches is for:
1. If GCLAST is not enabled, SMI will not know if the group is over.
SMI will wait until the last signal is received before it starts to
act.
It may cause OVL can not receive any data from SMI.

To support OVL multi-layer output, add datapath_con settings below:
GCLAST_EN = BIT(24), enable last SMI signal of ovl group
HDR_GCLAST_EN = BIT(25), enable last SMI signal of ovl AFBC group

2. After OUTPUT_CLAMP is enabled, the data will be rounded from 12-bit
to 10-bit. Because the modules after OVL need 10-bit input currently.
It may cause underflow problem, if there is no rounding to 10-bit.

To support 10bit data rounding, add datapath_con settings below:
OUTPUT_CLAMP = BIT(26), rounding data from 12-bit to 10-bit

Regard,
Jason-JH.Lin
> > 
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 15 ++++++++++++---
> >  1 file changed, 12 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > index 7504e86b167a..95fd5e00eb91 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > @@ -18,14 +18,17 @@
> >  #include "mtk_drm_ddp_comp.h"
> >  
> >  #define DISP_REG_OVL_INTEN			0x0004
> > -#define OVL_FME_CPL_INT					BIT(1)
> > +#define OVL_FME_CPL_INT				BIT(1)
> >  #define DISP_REG_OVL_INTSTA			0x0008
> >  #define DISP_REG_OVL_EN				0x000c
> >  #define DISP_REG_OVL_RST			0x0014
> >  #define DISP_REG_OVL_ROI_SIZE			0x0020
> >  #define DISP_REG_OVL_DATAPATH_CON		0x0024
> > -#define OVL_LAYER_SMI_ID_EN				BIT(0)
> > -#define OVL_BGCLR_SEL_IN				BIT(2)
> > +#define OVL_LAYER_SMI_ID_EN			BIT(0)
> > +#define OVL_BGCLR_SEL_IN			BIT(2)
> > +#define OVL_GCLAST_EN				BIT(24)
> > +#define OVL_HDR_GCLAST_EN			BIT(25)
> > +#define OVL_OUTPUT_CLAMP			BIT(26)
> >  #define DISP_REG_OVL_ROI_BGCLR			0x0028
> >  #define DISP_REG_OVL_SRC_CON			0x002c
> >  #define DISP_REG_OVL_CON(n)			(0x0030 + 0x20
> > * (n))
> > @@ -222,6 +225,7 @@ void mtk_ovl_layer_on(struct device *dev,
> > unsigned int idx,
> >  	unsigned int gmc_thrshd_l;
> >  	unsigned int gmc_thrshd_h;
> >  	unsigned int gmc_value;
> > +	unsigned int datapatch_con;
> >  	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
> >  
> >  	mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs,
> > @@ -237,6 +241,11 @@ void mtk_ovl_layer_on(struct device *dev,
> > unsigned int idx,
> >  			    gmc_thrshd_h << 16 | gmc_thrshd_h << 24;
> >  	mtk_ddp_write(cmdq_pkt, gmc_value,
> >  		      &ovl->cmdq_reg, ovl->regs,
> > DISP_REG_OVL_RDMA_GMC(idx));
> > +
> > +	datapatch_con = OVL_GCLAST_EN | OVL_HDR_GCLAST_EN |
> > OVL_OUTPUT_CLAMP;
> > +	mtk_ddp_write_mask(cmdq_pkt, datapatch_con, &ovl->cmdq_reg,
> > ovl->regs,
> > +				 DISP_REG_OVL_DATAPATH_CON,
> > datapatch_con);
> 
> For mt8173 or other SoC, this does not turn on. Now you turn on this,
> would this influence other SoC?
> 
> Regards,
> CK
> 
> > +
> >  	mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &ovl->cmdq_reg, ovl-
> > >regs,
> >  			   DISP_REG_OVL_SRC_CON, BIT(idx));
> >  }
> 
> 
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^ permalink raw reply	[flat|nested] 42+ messages in thread

* Re: [PATCH v1 11/17] drm/mediatek: add COLOR support for MT8195
  2021-07-07  6:01   ` CK Hu
@ 2021-07-10  7:21     ` Jason-JH Lin
  0 siblings, 0 replies; 42+ messages in thread
From: Jason-JH Lin @ 2021-07-10  7:21 UTC (permalink / raw)
  To: CK Hu
  Cc: chunkuang.hu, matthias.bgg, linux-arm-kernel, linux-mediatek,
	linux-kernel, Project_Global_Chrome_Upstream_Group, fshao,
	nancy.lin, singo.chang

On Wed, 2021-07-07 at 14:01 +0800, CK Hu wrote:
> Hi, Jason:
> 
> On Wed, 2021-07-07 at 12:12 +0800, jason-jh.lin wrote:
> > Add COLOR support for MT8195.
> > 
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_disp_color.c | 6 ++++++
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.c    | 2 ++
> >  2 files changed, 8 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_color.c
> > b/drivers/gpu/drm/mediatek/mtk_disp_color.c
> > index 63f411ab393b..ce2cf9f504cc 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_color.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_color.c
> > @@ -149,6 +149,10 @@ static const struct mtk_disp_color_data
> > mt8173_color_driver_data = {
> >  	.color_offset = DISP_COLOR_START_MT8173,
> >  };
> >  
> > +static const struct mtk_disp_color_data mt8195_color_driver_data =
> > {
> > +	.color_offset = DISP_COLOR_START_MT8173,
> > +};
> 
> mt8195_color_driver_data is identical to mt8173_color_driver_data, so
> use mt8173_color_driver_data and remove mt8195_color_driver_data.
> 
> > +
> >  static const struct of_device_id mtk_disp_color_driver_dt_match[]
> > = {
> >  	{ .compatible = "mediatek,mt2701-disp-color",
> >  	  .data = &mt2701_color_driver_data},
> > @@ -156,6 +160,8 @@ static const struct of_device_id
> > mtk_disp_color_driver_dt_match[] = {
> >  	  .data = &mt8167_color_driver_data},
> >  	{ .compatible = "mediatek,mt8173-disp-color",
> >  	  .data = &mt8173_color_driver_data},
> > +	{ .compatible = "mediatek,mt8195-disp-color",
> > +	  .data = &mt8195_color_driver_data},
> >  	{},
> >  };
> >  MODULE_DEVICE_TABLE(of, mtk_disp_color_driver_dt_match);
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > index 8b24623dcd91..28bf4a11efb0 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > @@ -444,6 +444,8 @@ static const struct of_device_id
> > mtk_ddp_comp_dt_ids[] = {
> >  	  .data = (void *)MTK_DISP_COLOR },
> >  	{ .compatible = "mediatek,mt8173-disp-color",
> >  	  .data = (void *)MTK_DISP_COLOR },
> > +	{ .compatible = "mediatek,mt8195-disp-color",
> > +	  .data = (void *)MTK_DISP_COLOR },
> 
> Is mediatek,mt8195-disp-color identical to
> mediatek,mt8173-disp-color in hardware function? If so, use the
> compatible
> as
> 
> compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-
> color";
> 
> And driver just keep "mediatek,mt8173-disp-color" and remove
> "mediatek,mt8195-disp-color".
> 
> If the hardware function has some different, just forget this.
> 
> Regards,
> CK
> 
Hi CK,

OK, I'll remove this patch at the next version.

Regard,
Jason-JH.Lin
> >  	{ .compatible = "mediatek,mt8173-disp-aal",
> >  	  .data = (void *)MTK_DISP_AAL},
> >  	{ .compatible = "mediatek,mt8173-disp-gamma",
> 
> 
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^ permalink raw reply	[flat|nested] 42+ messages in thread

* Re: [PATCH v1 12/17] drm/mediatek: add CCORR support for MT8195
  2021-07-07  6:02   ` CK Hu
@ 2021-07-10  7:22     ` Jason-JH Lin
  0 siblings, 0 replies; 42+ messages in thread
From: Jason-JH Lin @ 2021-07-10  7:22 UTC (permalink / raw)
  To: CK Hu
  Cc: chunkuang.hu, matthias.bgg, linux-arm-kernel, linux-mediatek,
	linux-kernel, Project_Global_Chrome_Upstream_Group, fshao,
	nancy.lin, singo.chang

On Wed, 2021-07-07 at 14:02 +0800, CK Hu wrote:
> Hi, Jason:
> 
> On Wed, 2021-07-07 at 12:12 +0800, jason-jh.lin wrote:
> > Add CCORR support for MT8195.
> > 
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 2 ++
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.c    | 2 ++
> >  2 files changed, 4 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> > b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> > index 141cb36b9c07..8188b220cc6d 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> > @@ -208,6 +208,8 @@ static const struct mtk_disp_ccorr_data
> > mt8183_ccorr_driver_data = {
> >  static const struct of_device_id mtk_disp_ccorr_driver_dt_match[]
> > = {
> >  	{ .compatible = "mediatek,mt8183-disp-ccorr",
> >  	  .data = &mt8183_ccorr_driver_data},
> > +	{ .compatible = "mediatek,mt8195-disp-ccorr",
> > +	  .data = &mt8183_ccorr_driver_data},
> >  	{},
> >  };
> >  MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match);
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > index 28bf4a11efb0..058b50d0e64b 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > @@ -440,6 +440,8 @@ static const struct of_device_id
> > mtk_ddp_comp_dt_ids[] = {
> >  	  .data = (void *)MTK_DISP_WDMA },
> >  	{ .compatible = "mediatek,mt8183-disp-ccorr",
> >  	  .data = (void *)MTK_DISP_CCORR },
> > +	{ .compatible = "mediatek,mt8195-disp-ccorr",
> > +	  .data = (void *)MTK_DISP_CCORR },
> 
> The same question as OVL and COLOR.
> 
> Regards,
> CK
> 
Hi CK,

OK, I'll remove this patch at the next version.

Regard,
Jason-JH.Lin
> >  	{ .compatible = "mediatek,mt2701-disp-color",
> >  	  .data = (void *)MTK_DISP_COLOR },
> >  	{ .compatible = "mediatek,mt8173-disp-color",
> 
> 
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^ permalink raw reply	[flat|nested] 42+ messages in thread

* Re: [PATCH v1 13/17] drm/mediatek: Add AAL support for MT8195
  2021-07-07  6:14   ` CK Hu
@ 2021-07-10  7:35     ` Jason-JH Lin
  0 siblings, 0 replies; 42+ messages in thread
From: Jason-JH Lin @ 2021-07-10  7:35 UTC (permalink / raw)
  To: CK Hu
  Cc: chunkuang.hu, matthias.bgg, linux-arm-kernel, linux-mediatek,
	linux-kernel, Project_Global_Chrome_Upstream_Group, fshao,
	nancy.lin, singo.chang

On Wed, 2021-07-07 at 14:14 +0800, CK Hu wrote:
> Hi, Jason:
> 
> On Wed, 2021-07-07 at 12:12 +0800, jason-jh.lin wrote:
> > 1. Add AAL support for MT8195.
> > 2. Add AAL_OUTPUT_SIZE configuration.
> > 
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 8 +++++++-
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.c      | 2 ++
> >  2 files changed, 9 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > index 75bc00e17fc4..f154f7c0cd11 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > @@ -34,6 +34,7 @@
> >  
> >  #define DISP_AAL_EN				0x0000
> >  #define DISP_AAL_SIZE				0x0030
> > +#define DISP_AAL_OUTPUT_SIZE			0x04d8
> >  
> >  #define DISP_DITHER_EN				0x0000
> >  #define DITHER_EN				BIT(0)
> > @@ -196,7 +197,12 @@ static void mtk_aal_config(struct device *dev,
> > unsigned int w,
> >  {
> >  	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> >  
> > -	mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv-
> > >regs, DISP_AAL_SIZE);
> > +	mtk_ddp_write(cmdq_pkt, w << 16 | h,
> > +				&priv->cmdq_reg, priv->regs,
> > +				DISP_AAL_SIZE);
> 
> Why do you change this?
> 
> > +	mtk_ddp_write(cmdq_pkt, w << 16 | h,
> > +				&priv->cmdq_reg, priv->regs,
> > +				DISP_AAL_OUTPUT_SIZE);
> 
> This seems not related to mt8195, so move this modification to
> another
> patch.
> 
> >  }
> >  
> >  static void mtk_aal_gamma_set(struct device *dev, struct
> > drm_crtc_state *state)
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > index 058b50d0e64b..459bb1e53f2e 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > @@ -450,6 +450,8 @@ static const struct of_device_id
> > mtk_ddp_comp_dt_ids[] = {
> >  	  .data = (void *)MTK_DISP_COLOR },
> >  	{ .compatible = "mediatek,mt8173-disp-aal",
> >  	  .data = (void *)MTK_DISP_AAL},
> > +	{ .compatible = "mediatek,mt8195-disp-aal",
> > +	  .data = (void *)MTK_DISP_AAL},
> 
> The same question for OVL, COLOR, CCORR.
> 
> Regards,
> CK
> 
> 
Hi CK,

To avoid the output height is incorrect, AAL_OUTPUT_SIZE
configuration is necessary setting for every chips.

> 
Other chips may set AAL_OUPUT_SIZE in boot loader or somewhere before
kernel, so they didn't need this confiuration here.

So I'll remove this patch at the next version.

Regard,
Jason-JH.Lin

> >  	{ .compatible = "mediatek,mt8173-disp-gamma",
> >  	  .data = (void *)MTK_DISP_GAMMA, },
> >  	{ .compatible = "mediatek,mt8183-disp-gamma",
> 
> 
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^ permalink raw reply	[flat|nested] 42+ messages in thread

* Re: [PATCH v1 16/17] drm/mediatek: add MERGE support for MT8195
  2021-07-07  7:02   ` CK Hu
@ 2021-07-10  7:52     ` Jason-JH Lin
  0 siblings, 0 replies; 42+ messages in thread
From: Jason-JH Lin @ 2021-07-10  7:52 UTC (permalink / raw)
  To: CK Hu
  Cc: chunkuang.hu, matthias.bgg, linux-arm-kernel, linux-mediatek,
	linux-kernel, Project_Global_Chrome_Upstream_Group, fshao,
	nancy.lin, singo.chang

Hi CK,

On Wed, 2021-07-07 at 15:02 +0800, CK Hu wrote:
> Hi, Jason:
> 
> On Wed, 2021-07-07 at 12:12 +0800, jason-jh.lin wrote:
> > 1. Add MERGE module file.
> > 2. Add REG_FLD macro in mtk_dem_crtc header to support
> >    bitwise register settings.
> > 
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/Makefile           |   1 +
> >  drivers/gpu/drm/mediatek/mtk_disp_drv.h     |  11 +
> >  drivers/gpu/drm/mediatek/mtk_disp_merge.c   | 623
> > ++++++++++++++++++++
> >  drivers/gpu/drm/mediatek/mtk_drm_crtc.h     |  31 +
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |  16 +
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |   1 +
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.c      |   4 +
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.h      |   1 +
> >  drivers/soc/mediatek/mtk-mutex.c            |   1 +
> >  include/linux/soc/mediatek/mtk-mmsys.h      |   6 +
> >  10 files changed, 695 insertions(+)
> >  create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
> > 
> > diff --git a/drivers/gpu/drm/mediatek/Makefile
> > b/drivers/gpu/drm/mediatek/Makefile
> > index dc54a7a69005..5fd95b9d5aae 100644
> > --- a/drivers/gpu/drm/mediatek/Makefile
> > +++ b/drivers/gpu/drm/mediatek/Makefile
> > @@ -5,6 +5,7 @@ mediatek-drm-y := mtk_disp_ccorr.o \
> >  		  mtk_disp_gamma.o \
> >  		  mtk_disp_ovl.o \
> >  		  mtk_disp_rdma.o \
> > +		  mtk_disp_merge.o \
> >  		  mtk_drm_crtc.o \
> >  		  mtk_drm_ddp_comp.o \
> >  		  mtk_drm_drv.o \
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > index cafd9df2d63b..7fd5260e2a72 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > @@ -89,4 +89,15 @@ void mtk_rdma_enable_vblank(struct device *dev,
> >  			    void *vblank_cb_data);
> >  void mtk_rdma_disable_vblank(struct device *dev);
> >  
> > +int mtk_merge_clk_enable(struct device *dev);
> > +void mtk_merge_clk_disable(struct device *dev);
> > +void mtk_merge_enable_vblank(struct device *dev,
> > +		    void (*vblank_cb)(void *), void *vblank_cb_data);
> > +void mtk_merge_disable_vblank(struct device *dev);
> > +void mtk_merge_config(struct device *dev, unsigned int width,
> > +		     unsigned int height, unsigned int vrefresh,
> > +		     unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> > +void mtk_merge_start(struct device *dev);
> > +void mtk_merge_stop(struct device *dev);
> > +
> >  #endif
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> > b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> > new file mode 100644
> > index 000000000000..4867fe3fb93f
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> > @@ -0,0 +1,623 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (c) 2019 MediaTek Inc.
> 
> 2021
> 
OK, I'll fix it.
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/component.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_irq.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/pm_runtime.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> > +
> > +#include "mtk_drm_crtc.h"
> > +#include "mtk_drm_ddp_comp.h"
> > +#include "mtk_drm_drv.h"
> > +#include "mtk_disp_drv.h"
> > +
> > +#define DISP_REG_MERGE_CTRL (0x000)
> > +#define FLD_MERGE_EN REG_FLD_MSB_LSB(0, 0)
> 
> #define FLD_MERGE_EN   BIT(0)
> 
OK, I'll fix it.

> > +#define FLD_MERGE_RST REG_FLD_MSB_LSB(4, 4)
> > +#define FLD_MERGE_LR_SWAP REG_FLD_MSB_LSB(8, 8)
> > +#define FLD_MERGE_DCM_DIS REG_FLD_MSB_LSB(12, 12)
> > +
> > +#define DISP_REG_MERGE_WIDTH (0x004)
> > +#define FLD_IN_WIDHT_L REG_FLD_MSB_LSB(15, 0)
> 
> #define FLD_IN_WIDHT_L GENMASK(15, 0)
> 
OK, I'll fix it.

> > +#define FLD_IN_WIDHT_R REG_FLD_MSB_LSB(31, 16)
> > +
> > +#define DISP_REG_MERGE_HEIGHT (0x008)
> > +#define FLD_IN_HEIGHT REG_FLD_MSB_LSB(15, 0)
> > +
> > +#define DISP_REG_MERGE_SHADOW_CRTL (0x00c)
> > +
> > +#define DISP_REG_MERGE_DGB0 (0x010)
> > +#define FLD_PIXEL_CNT REG_FLD_MSB_LSB(15, 0)
> > +#define FLD_MERGE_STATE REG_FLD_MSB_LSB(17, 16)
> > +
> > +#define DISP_REG_MERGE_DGB1 (0x014)
> > +#define FLD_LINE_CNT REG_FLD_MSB_LSB(15, 0)
> > +
> > +#define DISP_REG_MERGE_CFG2_0 (0x160)
> > +
> > +#define DISP_REG_MERGE_CFG2_2 (0x168)
> > +
> > +#define MT8195_DISP_MERGE_RESET		0x004
> 
> MT8195_DISP_MERGE_RESET is useless, so remove.
> 
OK, I'll remove it.

> > +#define MT8195_DISP_MERGE_CFG_0		0x010
> > +#define MT8195_DISP_MERGE_CFG_1		0x014
> > +#define MT8195_DISP_MERGE_CFG_4		0x020
> > +#define MT8195_DISP_MERGE_CFG_5		0x024
> > +#define MT8195_DISP_MERGE_CFG_8		0x030
> > +#define MT8195_DISP_MERGE_CFG_9		0x034
> > +#define MT8195_DISP_MERGE_CFG_10	0x038
> > +#define MT8195_DISP_MERGE_CFG_11	0x03c
> > +#define MT8195_DISP_MERGE_CFG_12	0x040
> > +#define CFG_11_11_1PI_1PO_BYPASS	1
> > +#define CFG_11_11_2PI_2PO_BYPASS	2
> > +#define CFG_10_10_2PI_1PO_BYPASS	3
> > +#define CFG_10_10_2PI_2PO_BYPASS	4
> > +#define CFG_10_10_1PI_1PO_BUF_MODE	5
> > +#define CFG_10_10_1PI_2PO_BUF_MODE	6
> > +#define CFG_10_10_2PI_1PO_BUF_MODE	7
> > +#define CFG_10_10_2PI_2PO_BUF_MODE	8
> > +#define CFG_10_01_1PI_1PO_BUF_MODE	9
> > +#define CFG_10_01_2PI_1PO_BUF_MODE	10
> > +#define CFG_01_10_1PI_1PO_BUF_MODE	11
> > +#define CFG_01_10_1PI_2PO_BUF_MODE	12
> > +#define CFG_01_01_1PI_1PO_BUF_MODE	13
> > +#define CFG_10_11_1PI_1PO_SPLIT		14
> > +#define CFG_10_11_2PI_1PO_SPLIT		15
> > +#define CFG_01_11_1PI_1PO_SPLIT		16
> > +#define CFG_11_10_1PI_1PO_MERGE		17
> > +#define CFG_11_10_1PI_2PO_MERGE		18
> > +#define CFG_10_10_1PI_1PO_TO422		19
> > +#define CFG_10_10_1PI_2PO_TO444		20
> > +#define CFG_10_10_2PI_2PO_TO444		21
> > +#define MT8195_DISP_MERGE_CFG_13	0x044
> > +#define MT8195_DISP_MERGE_CFG_14	0x048
> > +#define MT8195_DISP_MERGE_CFG_15	0x04c
> > +#define MT8195_DISP_MERGE_CFG_17	0x054
> > +#define MT8195_DISP_MERGE_CFG_18	0x058
> > +#define MT8195_DISP_MERGE_CFG_19	0x05c
> > +#define MT8195_DISP_MERGE_CFG_20	0x060
> > +#define MT8195_DISP_MERGE_CFG_21	0x064
> > +#define MT8195_DISP_MERGE_CFG_22	0x068
> > +#define MT8195_DISP_MERGE_CFG_23	0x06c
> > +#define MT8195_DISP_MERGE_CFG_24	0x070
> > +#define MT8195_DISP_MERGE_CFG_25	0x074
> > +#define MT8195_DISP_MERGE_CFG_26	0x078
> > +#define MT8195_DISP_MERGE_CFG_27	0x07c
> > +#define MT8195_DISP_MERGE_CFG_28	0x080
> > +#define MT8195_DISP_MERGE_CFG_29	0x084
> > +#define MT8195_DISP_MERGE_CFG_36	0x0a0
> > +#define MT8195_DISP_MERGE_CFG_36_FLD_ULTRA_EN \
> > +	REG_FLD(1, 0)
> > +#define MT8195_DISP_MERGE_CFG_36_FLD_PREULTRA_EN \
> > +	REG_FLD(1, 4)
> > +#define MT8195_DISP_MERGE_CFG_36_FLD_HALT_FOR_DVFS_EN \
> > +	REG_FLD(1, 8)
> > +#define MT8195_DISP_MERGE_CFG_36_VAL_ULTRA_EN(val) \
> > +	REG_FLD_VAL(MT8195_DISP_MERGE_CFG_36_FLD_ULTRA_EN, val)
> > +#define MT8195_DISP_MERGE_CFG_36_VAL_PREULTRA_EN(val) \
> > +	REG_FLD_VAL(MT8195_DISP_MERGE_CFG_36_FLD_PREULTRA_EN, val)
> > +#define MT8195_DISP_MERGE_CFG_36_VAL_HALT_FOR_DVFS_EN(val) \
> > +	REG_FLD_VAL(MT8195_DISP_MERGE_CFG_36_FLD_HALT_FOR_DVFS_EN, val)
> > +#define MT8195_DISP_MERGE_CFG_37	0x0a4
> > +#define MT8195_DISP_MERGE_CFG_37_FLD_BUFFER_MODE \
> > +	REG_FLD(2, 0)
> > +#define MT8195_DISP_MERGE_CFG_37_VAL_BUFFER_MODE(val) \
> > +	REG_FLD_VAL(MT8195_DISP_MERGE_CFG_37_FLD_BUFFER_MODE, val)
> > +#define MT8195_DISP_MERGE_CFG_38	0x0a8
> > +#define MT8195_DISP_MERGE_CFG_38_FLD_VDE_BLOCK_ULTRA \
> > +	REG_FLD(1, 0)
> > +#define MT8195_DISP_MERGE_CFG_38_FLD_VALID_TH_BLOCK_ULTRA \
> > +	REG_FLD(1, 4)
> > +#define MT8195_DISP_MERGE_CFG_38_FLD_ULTRA_FIFO_VALID_TH \
> > +	REG_FLD(16, 16)
> > +#define MT8195_DISP_MERGE_CFG_38_VAL_VDE_BLOCK_ULTRA(val) \
> > +	REG_FLD_VAL(MT8195_DISP_MERGE_CFG_38_FLD_VDE_BLOCK_ULTRA, val)
> > +#define MT8195_DISP_MERGE_CFG_38_VAL_VALID_TH_BLOCK_ULTRA(val) \
> > +	REG_FLD_VAL(MT8195_DISP_MERGE_CFG_38_FLD_VALID_TH_BLOCK_ULTRA,
> > val)
> > +#define MT8195_DISP_MERGE_CFG_38_VAL_ULTRA_FIFO_VALID_TH(val) \
> > +	REG_FLD_VAL(MT8195_DISP_MERGE_CFG_38_FLD_ULTRA_FIFO_VALID_TH,
> > val)
> > +#define MT8195_DISP_MERGE_CFG_39	0x0ac
> > +#define MT8195_DISP_MERGE_CFG_39_FLD_NVDE_FORCE_PREULTRA \
> > +	REG_FLD(1, 8)
> > +#define MT8195_DISP_MERGE_CFG_39_FLD_NVALID_TH_FORCE_PREULTRA \
> > +	REG_FLD(1, 12)
> > +#define MT8195_DISP_MERGE_CFG_39_FLD_PREULTRA_FIFO_VALID_TH \
> > +	REG_FLD(16, 16)
> > +#define MT8195_DISP_MERGE_CFG_39_VAL_NVDE_FORCE_PREULTRA(val) \
> > +	REG_FLD_VAL(MT8195_DISP_MERGE_CFG_39_FLD_NVDE_FORCE_PREULTRA,
> > val)
> > +#define MT8195_DISP_MERGE_CFG_39_VAL_NVALID_TH_FORCE_PREULTRA(val)
> > \
> > +	REG_FLD_VAL(MT8195_DISP_MERGE_CFG_39_FLD_NVALID_TH_FORCE_PREULT
> > RA, val)
> > +#define MT8195_DISP_MERGE_CFG_39_VAL_PREULTRA_FIFO_VALID_TH(val) \
> > +	REG_FLD_VAL(MT8195_DISP_MERGE_CFG_39_FLD_PREULTRA_FIFO_VALID_TH
> > , val)
> > +#define MT8195_DISP_MERGE_CFG_40	0x0b0
> > +#define MT8195_DISP_MERGE_CFG_40_FLD_ULTRA_TH_LOW \
> > +	REG_FLD(16, 0)
> > +#define MT8195_DISP_MERGE_CFG_40_FLD_ULTRA_TH_HIGH \
> > +	REG_FLD(16, 16)
> > +#define MT8195_DISP_MERGE_CFG_40_VAL_ULTRA_TH_LOW(val) \
> > +	REG_FLD_VAL(MT8195_DISP_MERGE_CFG_40_FLD_ULTRA_TH_LOW, (val))
> > +#define MT8195_DISP_MERGE_CFG_40_VAL_ULTRA_TH_HIGH(val) \
> > +	REG_FLD_VAL(MT8195_DISP_MERGE_CFG_40_FLD_ULTRA_TH_HIGH, val)
> > +#define MT8195_DISP_MERGE_CFG_41	0x0b4
> > +#define MT8195_DISP_MERGE_CFG_41_FLD_PREULTRA_TH_LOW \
> > +	REG_FLD(16, 0)
> > +#define MT8195_DISP_MERGE_CFG_41_FLD_PREULTRA_TH_HIGH \
> > +	REG_FLD(16, 16)
> > +#define MT8195_DISP_MERGE_CFG_41_VAL_PREULTRA_TH_LOW(val) \
> > +	REG_FLD_VAL(MT8195_DISP_MERGE_CFG_41_FLD_PREULTRA_TH_LOW, val)
> > +#define MT8195_DISP_MERGE_CFG_41_VAL_PREULTRA_TH_HIGH(val) \
> > +	REG_FLD_VAL(MT8195_DISP_MERGE_CFG_41_FLD_PREULTRA_TH_HIGH, val)
> > +
> > +struct mtk_disp_merge_data {
> > +	bool need_golden_setting;
> > +	enum mtk_ddp_comp_id gs_comp_id;
> > +};
> 
> Now only support mt8195-merge, so remove mtk_disp_merge_data.
> 
OK, I'll remove it.
> > +
> > +struct mtk_merge_config_struct {
> > +	unsigned short width_right;
> > +	unsigned short width_left;
> > +	unsigned int height;
> > +	unsigned int fmt;
> > +	unsigned int mode;
> > +	unsigned int swap;
> 
> Could you explain this parameter?
> 
The swap parameter is for the MERGE output swapping.
Each value in the register MT8195_DISP_MERGE_CFG_10 is decribed below:
5'h01 : RG swap, {R,G,B} -> {G,R,B}
5'h02 : GB swap, {R,G,B} -> {R,B,G}
5'h04 : BR swap, {R,G,B} -> {B,G,R}
5'h08 : RG-GB swap, {R,G,B} -> {B,R,G}
5'h10 : RB-GB swap, {R,G,B} -> {G,B,R}
else : No swap

> > +};
> > +
> > +struct mtk_disp_merge {
> > +	struct mtk_ddp_comp ddp_comp;
> > +	struct drm_crtc *crtc;
> 
> I think sub driver should get rid of ddp_comp and crtc.
> 
OK, I'll remove it.

> > +	struct clk *clk;
> > +	struct clk *async_clk;
> > +	void __iomem *regs;
> > +	struct cmdq_client_reg		cmdq_reg;
> > +	int irq;
> > +	void (*vblank_cb)(void *data);
> 
> Why implement vblank_cb? For the first patch of one driver, just keep
> the basic function.

OK, I'll remove it.
> 
> > +	void *vblank_cb_data;
> > +	const struct mtk_disp_merge_data *data;
> > +};
> > +
> > +static struct mtk_ddp_comp *merge_5_comp;
> 
> Useless, so remove.
> 
OK, I'll remove it.
> > +
> > +static inline struct mtk_disp_merge *comp_to_merge(struct
> > mtk_ddp_comp *comp)
> > +{
> > +	return container_of(comp, struct mtk_disp_merge, ddp_comp);
> > +}
> 
> Useless, so remove.
> 
OK, I'll remove it.
> > +
> > +void mtk_merge_start(struct device *dev)
> > +{
> > +	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > +
> > +	mtk_ddp_write_mask(NULL, 0x1, &priv->cmdq_reg, priv->regs,
> > +		DISP_REG_MERGE_CTRL, ~0);
> 
> Your mask is 0xffffffff, use mtk_ddp_write().
> 
OK, I'll fix it.

> > +}
> > +
> > +void mtk_merge_stop(struct device *dev)
> > +{
> > +	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > +
> > +	mtk_ddp_write_mask(NULL, 0x0, &priv->cmdq_reg, priv->regs,
> > +		DISP_REG_MERGE_CTRL, ~0);
> 
> Your mask is 0xffffffff, use mtk_ddp_write().
> 
OK, I'll fix it.
> > +}
> > +
> > +static int mtk_merge_check_params(struct mtk_merge_config_struct
> > *merge_config)
> > +{
> > +	if (!merge_config->height ||
> > +		!merge_config->width_left || !merge_config-
> > >width_right) {
> > +		pr_err("%s:merge input width l(%u) w(%u) h(%u)\n",
> > +			  __func__, merge_config->width_left,
> > +			  merge_config->width_right, merge_config-
> > >height);
> > +		return -EINVAL;
> > +	}
> > +	pr_debug("%s:merge input width l(%u) r(%u) height(%u)\n",
> > +			  __func__, merge_config->width_left,
> > +			  merge_config->width_right, merge_config-
> > >height);
> > +	return 0;
> > +}
> > +
> > +static int mtk_merge_golden_setting(struct mtk_disp_merge *priv,
> > +				  struct cmdq_pkt *handle)
> > +{
> > +	int ultra_en = 1;
> > +	int preultra_en = 1;
> > +	int halt_for_dvfs_en = 0;
> > +	int buffer_mode = 3;
> > +	int vde_block_ultra = 0;
> > +	int valid_th_block_ultra = 0;
> > +	int ultra_fifo_valid_th = 0;
> > +	int nvde_force_preultra = 0;
> > +	int nvalid_th_force_preultra = 0;
> > +	int preultra_fifo_valid_th = 0;
> > +	int ultra_th_low = 0xe10;
> > +	int ultra_th_high = 0x12c0;
> > +	int preultra_th_low = 0x12c0;
> > +	int preultra_th_high = 0x1518;
> > +
> > +	mtk_ddp_write_mask(handle,
> > +		MT8195_DISP_MERGE_CFG_36_VAL_ULTRA_EN(ultra_en) |
> > +		MT8195_DISP_MERGE_CFG_36_VAL_PREULTRA_EN(preultra_en) |
> > +		MT8195_DISP_MERGE_CFG_36_VAL_HALT_FOR_DVFS_EN(halt_for_
> > dvfs_en),
> > +		&priv->cmdq_reg, priv->regs,
> > +		MT8195_DISP_MERGE_CFG_36,
> > +		REG_FLD_MASK(MT8195_DISP_MERGE_CFG_36_FLD_ULTRA_EN) |
> > +		REG_FLD_MASK(MT8195_DISP_MERGE_CFG_36_FLD_PREULTRA_EN)
> > |
> > +		REG_FLD_MASK(MT8195_DISP_MERGE_CFG_36_FLD_HALT_FOR_DVFS
> > _EN));
> > +
> > +	mtk_ddp_write_mask(handle,
> > +		MT8195_DISP_MERGE_CFG_37_VAL_BUFFER_MODE(buffer_mode),
> > +		&priv->cmdq_reg, priv->regs,
> > +		MT8195_DISP_MERGE_CFG_37,
> > +		REG_FLD_MASK(MT8195_DISP_MERGE_CFG_37_FLD_BUFFER_MODE))
> > ;
> > +
> > +	mtk_ddp_write_mask(handle,
> > +		MT8195_DISP_MERGE_CFG_38_VAL_VDE_BLOCK_ULTRA
> > +		(vde_block_ultra) |
> > +		MT8195_DISP_MERGE_CFG_38_VAL_VALID_TH_BLOCK_ULTRA
> > +		(valid_th_block_ultra) |
> > +		MT8195_DISP_MERGE_CFG_38_VAL_ULTRA_FIFO_VALID_TH
> > +		(ultra_fifo_valid_th),
> > +		&priv->cmdq_reg, priv->regs,
> > +		MT8195_DISP_MERGE_CFG_38,
> > +		REG_FLD_MASK
> > +		(MT8195_DISP_MERGE_CFG_38_FLD_VDE_BLOCK_ULTRA) |
> > +		REG_FLD_MASK
> > +		(MT8195_DISP_MERGE_CFG_38_FLD_VALID_TH_BLOCK_ULTRA) |
> > +		REG_FLD_MASK
> > +		(MT8195_DISP_MERGE_CFG_38_FLD_ULTRA_FIFO_VALID_TH));
> > +
> > +	mtk_ddp_write_mask(handle,
> > +		MT8195_DISP_MERGE_CFG_39_VAL_NVDE_FORCE_PREULTRA
> > +		(nvde_force_preultra) |
> > +		MT8195_DISP_MERGE_CFG_39_VAL_NVALID_TH_FORCE_PREULTRA
> > +		(nvalid_th_force_preultra) |
> > +		MT8195_DISP_MERGE_CFG_39_VAL_PREULTRA_FIFO_VALID_TH
> > +		(preultra_fifo_valid_th),
> > +		&priv->cmdq_reg, priv->regs,
> > +		MT8195_DISP_MERGE_CFG_39,
> > +		REG_FLD_MASK
> > +		(MT8195_DISP_MERGE_CFG_39_FLD_NVDE_FORCE_PREULTRA) |
> > +		REG_FLD_MASK
> > +		(MT8195_DISP_MERGE_CFG_39_FLD_NVALID_TH_FORCE_PREULTRA)
> > |
> > +		REG_FLD_MASK
> > +		(MT8195_DISP_MERGE_CFG_39_FLD_PREULTRA_FIFO_VALID_TH));
> > +
> > +	mtk_ddp_write_mask(handle,
> > +		MT8195_DISP_MERGE_CFG_40_VAL_ULTRA_TH_LOW(ultra_th_low)
> > |
> > +		MT8195_DISP_MERGE_CFG_40_VAL_ULTRA_TH_HIGH(ultra_th_hig
> > h),
> > +		&priv->cmdq_reg, priv->regs,
> > +		MT8195_DISP_MERGE_CFG_40,
> > +		REG_FLD_MASK(MT8195_DISP_MERGE_CFG_40_FLD_ULTRA_TH_LOW)
> > |
> > +		REG_FLD_MASK(MT8195_DISP_MERGE_CFG_40_FLD_ULTRA_TH_HIGH
> > ));
> > +
> > +	mtk_ddp_write_mask(handle,
> > +		MT8195_DISP_MERGE_CFG_41_VAL_PREULTRA_TH_LOW(preultra_t
> > h_low) |
> > +		MT8195_DISP_MERGE_CFG_41_VAL_PREULTRA_TH_HIGH(preultra_
> > th_high),
> > +		&priv->cmdq_reg, priv->regs,
> > +		MT8195_DISP_MERGE_CFG_41,
> > +		REG_FLD_MASK(MT8195_DISP_MERGE_CFG_41_FLD_PREULTRA_TH_L
> > OW) |
> > +		REG_FLD_MASK(MT8195_DISP_MERGE_CFG_41_FLD_PREULTRA_TH_H
> > IGH));
> > +
> > +	return 0;
> > +}
> > +
> > +void mtk_merge_config(struct device *dev, unsigned int w,
> > +				  unsigned int h, unsigned int
> > vrefresh,
> > +				  unsigned int bpc, struct cmdq_pkt
> > *handle)
> > +{
> > +	struct mtk_merge_config_struct merge_config;
> > +	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > +	struct mtk_ddp_comp *comp = &priv->ddp_comp;
> > +
> > +	/*golden setting*/
> > +	if (priv->data) {
> > +		if (priv->data->need_golden_setting &&
> > +			priv->data->gs_comp_id == comp->id)
> > +			mtk_merge_golden_setting(priv, handle);
> > +	}
> > +
> > +	switch (comp->id) {
> > +	case DDP_COMPONENT_MERGE0:
> > +		merge_config.mode = CFG_10_10_1PI_2PO_BUF_MODE;
> > +		merge_config.width_left = w;
> > +		merge_config.width_right = w;
> > +		merge_config.height = h;
> > +		merge_config.swap = 0;
> > +		break;
> > +	case DDP_COMPONENT_MERGE5:
> > +		merge_config.mode = CFG_10_10_2PI_2PO_BUF_MODE;
> > +		merge_config.width_left = w;
> > +		merge_config.width_right = w;
> > +		merge_config.height = h;
> > +		merge_config.swap = 0;
> > +		break;
> > +	default:
> > +		pr_err("No find component merge %d\n", comp->id);
> > +		return;
> > +	}
> > +
> > +	mtk_merge_check_params(&merge_config);
> > +
> > +	switch (merge_config.mode) {
> > +	case CFG_10_10_1PI_1PO_BUF_MODE:
> 
> CFG_10_10_1PI_1PO_BUF_MODE is useless, so remove.

OK, I'll remove it.
> 
> > +	case CFG_10_10_1PI_2PO_BUF_MODE:
> > +	case CFG_10_10_2PI_2PO_BUF_MODE:
> > +		mtk_ddp_write_mask(handle,
> > +			(merge_config.height << 16 |
> > merge_config.width_left),
> > +			&priv->cmdq_reg, priv->regs,
> > +			MT8195_DISP_MERGE_CFG_0, ~0);
> > +
> > +		mtk_ddp_write_mask(handle,
> > +			(merge_config.height << 16 |
> > merge_config.width_left),
> > +			&priv->cmdq_reg, priv->regs,
> > +			MT8195_DISP_MERGE_CFG_4, ~0);
> > +
> > +		mtk_ddp_write_mask(handle,
> > +			(merge_config.height << 16 |
> > merge_config.width_left),
> > +			&priv->cmdq_reg, priv->regs,
> > +			MT8195_DISP_MERGE_CFG_24, ~0);
> > +
> > +		mtk_ddp_write_mask(handle,
> > +			(merge_config.height << 16 |
> > merge_config.width_left),
> > +			&priv->cmdq_reg, priv->regs,
> > +			MT8195_DISP_MERGE_CFG_25, ~0);
> > +
> > +		mtk_ddp_write_mask(handle,
> > +			merge_config.swap,
> > +			&priv->cmdq_reg, priv->regs,
> > +			MT8195_DISP_MERGE_CFG_10, 0x1f);
> > +	break;
> > +	case CFG_11_10_1PI_2PO_MERGE:
> 
> CFG_11_10_1PI_2PO_MERGE is useless, so remove.
> 
OK, I'll remove it.

> > +		mtk_ddp_write_mask(handle,
> > +			(merge_config.height << 16 |
> > merge_config.width_left),
> > +			&priv->cmdq_reg, priv->regs,
> > +			MT8195_DISP_MERGE_CFG_0, ~0);
> > +
> > +		mtk_ddp_write_mask(handle,
> > +			(merge_config.height << 16 |
> > merge_config.width_right),
> > +			&priv->cmdq_reg, priv->regs,
> > +			MT8195_DISP_MERGE_CFG_1, ~0);
> > +
> > +		mtk_ddp_write_mask(handle,
> > +			(merge_config.height << 16 | w),
> > +			&priv->cmdq_reg, priv->regs,
> > +			MT8195_DISP_MERGE_CFG_4, ~0);
> > +
> > +		mtk_ddp_write_mask(handle,
> > +			(merge_config.height << 16 |
> > merge_config.width_left),
> > +			&priv->cmdq_reg, priv->regs,
> > +			MT8195_DISP_MERGE_CFG_24, ~0);
> > +
> > +		mtk_ddp_write_mask(handle,
> > +			(merge_config.height << 16 |
> > merge_config.width_right),
> > +			&priv->cmdq_reg, priv->regs,
> > +			MT8195_DISP_MERGE_CFG_25, ~0);
> > +
> > +		mtk_ddp_write_mask(handle,
> > +			(merge_config.height << 16 |
> > merge_config.width_left),
> > +			&priv->cmdq_reg, priv->regs,
> > +			MT8195_DISP_MERGE_CFG_26, ~0);
> > +
> > +		mtk_ddp_write_mask(handle,
> > +			(merge_config.height << 16 |
> > merge_config.width_right),
> > +			&priv->cmdq_reg, priv->regs,
> > +			MT8195_DISP_MERGE_CFG_27, ~0);
> > +
> > +		mtk_ddp_write_mask(handle,
> > +			merge_config.swap,
> > +			&priv->cmdq_reg, priv->regs,
> > +			MT8195_DISP_MERGE_CFG_10, 0x1f);
> > +	break;
> > +	default:
> > +	break;
> > +	}
> > +	mtk_ddp_write_mask(handle, merge_config.mode,
> > +		&priv->cmdq_reg, priv->regs, MT8195_DISP_MERGE_CFG_12,
> > 0x1f);
> > +	mtk_ddp_write_mask(handle, 0x1,
> > +		&priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CTRL, 0x1);
> > +}
> > +
> > +int mtk_merge_clk_enable(struct device *dev)
> > +{
> > +	int ret = 0;
> > +	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > +
> > +	ret = pm_runtime_get_sync(dev);
> > +
> > +	if (priv->clk) {
> > +		ret = clk_prepare_enable(priv->clk);
> > +		if (ret)
> > +			pr_err("merge clk prepare enable failed\n");
> > +	}
> > +
> > +	if (priv->async_clk) {
> > +		ret = clk_prepare_enable(priv->async_clk);
> > +		if (ret)
> > +			pr_err("async clk prepare enable failed\n");
> > +	}
> > +
> > +	return ret;
> > +}
> > +
> > +void mtk_merge_clk_disable(struct device *dev)
> > +{
> > +	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > +
> > +	if (priv->async_clk)
> > +		clk_disable_unprepare(priv->async_clk);
> > +
> > +	if (priv->clk)
> > +		clk_disable_unprepare(priv->clk);
> > +
> > +	pm_runtime_put_sync(dev);
> > +}
> > +
> > +void mtk_merge_enable_vblank(struct device *dev,
> > +			    void (*vblank_cb)(void *),
> > +			    void *vblank_cb_data)
> > +{
> > +	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > +	int irq_frame_done_en = BIT(16);
> > +
> > +	priv->vblank_cb = vblank_cb;
> > +	priv->vblank_cb_data = vblank_cb_data;
> > +
> > +	writel(irq_frame_done_en, priv->regs + DISP_REG_MERGE_CFG2_0);
> > +}
> 
> Useless, so remove.
> 
OK, I'll remove it.
> > +
> > +void mtk_merge_disable_vblank(struct device *dev)
> > +{
> > +	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > +
> > +	priv->vblank_cb = NULL;
> > +	priv->vblank_cb_data = NULL;
> > +
> > +	writel(0x0, priv->regs + DISP_REG_MERGE_CFG2_0);
> > +}
> 
> Useless, so remove.
> 
OK, I'll remove it.
> > +
> > +static int mtk_disp_merge_bind(struct device *dev, struct device
> > *master,
> > +			       void *data)
> > +{
> > +	return 0;
> > +}
> > +
> > +static void mtk_disp_merge_unbind(struct device *dev, struct
> > device *master,
> > +				  void *data)
> > +{
> > +}
> > +
> > +static irqreturn_t mtk_disp_merge_irq_handler(int irq, void
> > *dev_id)
> > +{
> > +	struct mtk_disp_merge *priv = dev_id;
> > +
> > +	/* Clear frame completion interrupt */
> > +	writel(0x1, priv->regs + DISP_REG_MERGE_CFG2_2);
> > +	writel(0x0, priv->regs + DISP_REG_MERGE_CFG2_2);
> > +
> > +	if (!priv->vblank_cb)
> > +		return IRQ_NONE;
> > +
> > +	priv->vblank_cb(priv->vblank_cb_data);
> > +
> > +	return IRQ_HANDLED;
> > +}
> 
> Useless, so remove.

OK, I'll remove it.
> 
> > +
> > +static const struct component_ops mtk_disp_merge_component_ops = {
> > +	.bind	= mtk_disp_merge_bind,
> > +	.unbind = mtk_disp_merge_unbind,
> > +};
> > +
> > +static int mtk_disp_merge_probe(struct platform_device *pdev)
> > +{
> > +	struct device *dev = &pdev->dev;
> > +	struct resource *res;
> > +	struct mtk_disp_merge *priv;
> > +	enum mtk_ddp_comp_id comp_id;
> > +	int ret;
> > +
> > +	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> > +	if (!priv)
> > +		return -ENOMEM;
> > +
> > +	comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_MERGE);
> > +	if ((int)comp_id < 0) {
> > +		dev_err(dev, "Failed to identify by alias: %d\n",
> > comp_id);
> > +		return comp_id;
> > +	}
> > +
> > +	priv->ddp_comp.id = comp_id;
> > +
> > +	if (comp_id == DDP_COMPONENT_MERGE5)
> > +		merge_5_comp = &priv->ddp_comp;
> > +
> > +	priv->clk = devm_clk_get(dev, NULL);
> > +	if (IS_ERR(priv->clk)) {
> > +		dev_err(dev, "failed to get merge clk\n");
> > +		return PTR_ERR(priv->clk);
> > +	}
> > +
> > +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > +	priv->regs = devm_ioremap_resource(dev, res);
> > +	if (IS_ERR(priv->regs)) {
> > +		dev_err(dev, "failed to ioremap merge\n");
> > +		return PTR_ERR(priv->regs);
> > +	}
> > +
> > +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> > +	ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
> > +	if (ret)
> > +		dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
> > +#endif
> > +
> > +	priv->irq = platform_get_irq(pdev, 0);
> > +	if (priv->irq < 0)
> > +		priv->irq = 0;
> > +
> > +	priv->async_clk = of_clk_get(dev->of_node, 1);
> 
> From binding document and device tree, there is no async clk, would
> you
> modify binding document?
> 
> Regards,
> CK
> 

The display binding document is no decription for the MERGE module
currently. I'll separate it from the display document if it is
neccessary.

Regards,
Jason-JH.Lin
> > +	if (IS_ERR(priv->async_clk)) {
> > +		ret = PTR_ERR(priv->async_clk);
> > +		dev_dbg(dev, "No merge async clock: %d\n", ret);
> > +		priv->async_clk = NULL;
> > +	}
> > +
> > +	priv->data = of_device_get_match_data(dev);
> > +
> > +	if (priv->irq) {
> > +		ret = devm_request_irq(dev, priv->irq,
> > +					mtk_disp_merge_irq_handler,
> > +					IRQF_TRIGGER_NONE,
> > dev_name(dev), priv);
> > +		if (ret < 0) {
> > +			dev_err(dev, "Failed to request irq %d: %d\n",
> > +					priv->irq, ret);
> > +			return ret;
> > +		}
> > +	}
> > +
> > +	platform_set_drvdata(pdev, priv);
> > +
> > +	pm_runtime_enable(dev);
> > +
> > +	ret = component_add(dev, &mtk_disp_merge_component_ops);
> > +	if (ret != 0) {
> > +		dev_err(dev, "Failed to add component: %d\n", ret);
> > +		pm_runtime_disable(dev);
> > +	}
> > +
> > +	return ret;
> > +}
> > +
> > +static int mtk_disp_merge_remove(struct platform_device *pdev)
> > +{
> > +	component_del(&pdev->dev, &mtk_disp_merge_component_ops);
> > +
> > +	pm_runtime_disable(&pdev->dev);
> > +
> > +	return 0;
> > +}
> > +
> > +static const struct mtk_disp_merge_data mt8195_merge_driver_data =
> > {
> > +	.need_golden_setting = true,
> > +	.gs_comp_id = DDP_COMPONENT_MERGE5,
> > +};
> > +
> > +static const struct of_device_id mtk_disp_merge_driver_dt_match[]
> > = {
> > +	{
> > +		.compatible = "mediatek,mt8195-disp-merge",
> > +		.data = &mt8195_merge_driver_data
> > +	},
> > +	{},
> > +};
> > +
> > +MODULE_DEVICE_TABLE(of, mtk_disp_merge_driver_dt_match);
> > +
> > +struct platform_driver mtk_disp_merge_driver = {
> > +	.probe = mtk_disp_merge_probe,
> > +	.remove = mtk_disp_merge_remove,
> > +	.driver = {
> > +		.name = "mediatek-disp-merge",
> > +		.owner = THIS_MODULE,
> > +		.of_match_table = mtk_disp_merge_driver_dt_match,
> > +	},
> > +};
> > +
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> > index cb9a36c48d4f..7419cd0fb424 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> > @@ -14,6 +14,37 @@
> >  #define MTK_MAX_BPC	10
> >  #define MTK_MIN_BPC	3
> >  
> > +#define _MASK_SHIFT(val, width, shift) \
> > +	(((val) >> (shift)) & ((1 << (width)) - 1))
> > +
> > +#define REG_FLD(width, shift) \
> > +	((unsigned int)((((width) & 0xff) << 16) | ((shift) & 0xff)))
> > +
> > +#define REG_FLD_MSB_LSB(msb, lsb) REG_FLD((msb) - (lsb) + 1,
> > (lsb))
> > +
> > +#define REG_FLD_WIDTH(field) ((unsigned int)(((field) >> 16) &
> > 0xff))
> > +
> > +#define REG_FLD_SHIFT(field) ((unsigned int)((field) & 0xff))
> > +
> > +#define REG_FLD_MASK(field) \
> > +	((unsigned int)((1ULL << REG_FLD_WIDTH(field)) - 1) \
> > +	 << REG_FLD_SHIFT(field))
> > +
> > +#define REG_FLD_VAL(field, val) \
> > +	(((val) << REG_FLD_SHIFT(field)) & REG_FLD_MASK(field))
> > +
> > +#define REG_FLD_VAL_GET(field, regval) \
> > +	(((regval) & REG_FLD_MASK(field)) >> REG_FLD_SHIFT(field))
> > +
> > +#define DISP_REG_GET_FIELD(field, reg32) \
> > +	REG_FLD_VAL_GET(field, __raw_readl((unsigned long *)(reg32)))
> > +
> > +#define SET_VAL_MASK(o_val, o_mask, i_val, i_fld) \
> > +	do { \
> > +		(o_val) |= ((i_val) << REG_FLD_SHIFT(i_fld)); \
> > +		(o_mask) |= (REG_FLD_MASK(i_fld)); \
> > +	} while (0)
> > +
> >  void mtk_drm_crtc_commit(struct drm_crtc *crtc);
> >  int mtk_drm_crtc_create(struct drm_device *drm_dev,
> >  			const enum mtk_ddp_comp_id *path,
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > index f154f7c0cd11..2ccf3db1950d 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > @@ -339,6 +339,14 @@ static const struct mtk_ddp_comp_funcs
> > ddp_rdma = {
> >  	.layer_config = mtk_rdma_layer_config,
> >  };
> >  
> > +static const struct mtk_ddp_comp_funcs ddp_merge = {
> > +	.clk_enable = mtk_merge_clk_enable,
> > +	.clk_disable = mtk_merge_clk_disable,
> > +	.start = mtk_merge_start,
> > +	.stop = mtk_merge_stop,
> > +	.config = mtk_merge_config,
> > +};
> > +
> >  static const struct mtk_ddp_comp_funcs ddp_ufoe = {
> >  	.clk_enable = mtk_ddp_clk_enable,
> >  	.clk_disable = mtk_ddp_clk_disable,
> > @@ -362,6 +370,7 @@ static const char * const
> > mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> >  	[MTK_DISP_MUTEX] = "mutex",
> >  	[MTK_DISP_OD] = "od",
> >  	[MTK_DISP_BLS] = "bls",
> > +	[MTK_DISP_MERGE] = "merge",
> >  };
> >  
> >  struct mtk_ddp_comp_match {
> > @@ -397,6 +406,12 @@ static const struct mtk_ddp_comp_match
> > mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
> >  	[DDP_COMPONENT_RDMA0]	= { MTK_DISP_RDMA,	0,
> > &ddp_rdma },
> >  	[DDP_COMPONENT_RDMA1]	= { MTK_DISP_RDMA,	1,
> > &ddp_rdma },
> >  	[DDP_COMPONENT_RDMA2]	= { MTK_DISP_RDMA,	2,
> > &ddp_rdma },
> > +	[DDP_COMPONENT_MERGE0]	= { MTK_DISP_MERGE,	0,
> > &ddp_merge },
> > +	[DDP_COMPONENT_MERGE1]	= { MTK_DISP_MERGE,	1,
> > &ddp_merge },
> > +	[DDP_COMPONENT_MERGE2]	= { MTK_DISP_MERGE,	2,
> > &ddp_merge },
> > +	[DDP_COMPONENT_MERGE3]	= { MTK_DISP_MERGE,	3,
> > &ddp_merge },
> > +	[DDP_COMPONENT_MERGE4]	= { MTK_DISP_MERGE,	4,
> > &ddp_merge },
> > +	[DDP_COMPONENT_MERGE5]	= { MTK_DISP_MERGE,	5,
> > &ddp_merge },
> >  	[DDP_COMPONENT_UFOE]	= { MTK_DISP_UFOE,	0,
> > &ddp_ufoe },
> >  	[DDP_COMPONENT_WDMA0]	= { MTK_DISP_WDMA,	0, NULL },
> >  	[DDP_COMPONENT_WDMA1]	= { MTK_DISP_WDMA,	1, NULL },
> > @@ -515,6 +530,7 @@ int mtk_ddp_comp_init(struct device_node *node,
> > struct mtk_ddp_comp *comp,
> >  	    type == MTK_DISP_CCORR ||
> >  	    type == MTK_DISP_COLOR ||
> >  	    type == MTK_DISP_GAMMA ||
> > +	    type == MTK_DISP_MERGE ||
> >  	    type == MTK_DPI ||
> >  	    type == MTK_DSI ||
> >  	    type == MTK_DISP_OVL ||
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > index bb914d976cf5..038775b4531b 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > @@ -34,6 +34,7 @@ enum mtk_ddp_comp_type {
> >  	MTK_DISP_MUTEX,
> >  	MTK_DISP_OD,
> >  	MTK_DISP_BLS,
> > +	MTK_DISP_MERGE,
> >  	MTK_DDP_COMP_TYPE_MAX,
> >  };
> >  
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > index 635cebf9ff0f..f891316008aa 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > @@ -462,6 +462,8 @@ static const struct of_device_id
> > mtk_ddp_comp_dt_ids[] = {
> >  	  .data = (void *)MTK_DISP_DITHER },
> >  	{ .compatible = "mediatek,mt8195-disp-dither",
> >  	  .data = (void *)MTK_DISP_DITHER },
> > +	{ .compatible = "mediatek,mt8195-disp-merge",
> > +	  .data = (void *)MTK_DISP_MERGE },
> >  	{ .compatible = "mediatek,mt8173-disp-ufoe",
> >  	  .data = (void *)MTK_DISP_UFOE },
> >  	{ .compatible = "mediatek,mt2701-dsi",
> > @@ -579,6 +581,7 @@ static int mtk_drm_probe(struct platform_device
> > *pdev)
> >  		if (comp_type == MTK_DISP_CCORR ||
> >  		    comp_type == MTK_DISP_COLOR ||
> >  		    comp_type == MTK_DISP_GAMMA ||
> > +		    comp_type == MTK_DISP_MERGE ||
> >  		    comp_type == MTK_DISP_OVL ||
> >  		    comp_type == MTK_DISP_OVL_2L ||
> >  		    comp_type == MTK_DISP_RDMA ||
> > @@ -683,6 +686,7 @@ static struct platform_driver * const
> > mtk_drm_drivers[] = {
> >  	&mtk_disp_rdma_driver,
> >  	&mtk_dpi_driver,
> >  	&mtk_drm_platform_driver,
> > +	&mtk_disp_merge_driver,
> >  	&mtk_dsi_driver,
> >  };
> >  
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > index 637f5669e895..18548a373626 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > @@ -51,6 +51,7 @@ extern struct platform_driver
> > mtk_disp_color_driver;
> >  extern struct platform_driver mtk_disp_gamma_driver;
> >  extern struct platform_driver mtk_disp_ovl_driver;
> >  extern struct platform_driver mtk_disp_rdma_driver;
> > +extern struct platform_driver mtk_disp_merge_driver;
> >  extern struct platform_driver mtk_dpi_driver;
> >  extern struct platform_driver mtk_dsi_driver;
> >  
> > diff --git a/drivers/soc/mediatek/mtk-mutex.c
> > b/drivers/soc/mediatek/mtk-mutex.c
> > index 080bdabfb024..84ece5486902 100644
> > --- a/drivers/soc/mediatek/mtk-mutex.c
> > +++ b/drivers/soc/mediatek/mtk-mutex.c
> > @@ -284,6 +284,7 @@ static const unsigned int
> > mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> >  	[DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
> >  	[DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
> >  	[DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
> > +	[DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
> >  	[DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
> >  	[DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
> >  };
> > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
> > b/include/linux/soc/mediatek/mtk-mmsys.h
> > index 2228bf6133da..3135ce82a7f7 100644
> > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > @@ -39,6 +39,12 @@ enum mtk_ddp_comp_id {
> >  	DDP_COMPONENT_UFOE,
> >  	DDP_COMPONENT_WDMA0,
> >  	DDP_COMPONENT_WDMA1,
> > +	DDP_COMPONENT_MERGE0,
> > +	DDP_COMPONENT_MERGE1,
> > +	DDP_COMPONENT_MERGE2,
> > +	DDP_COMPONENT_MERGE3,
> > +	DDP_COMPONENT_MERGE4,
> > +	DDP_COMPONENT_MERGE5,
> >  	DDP_COMPONENT_ID_MAX,
> >  };
> >  
> 
> 
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^ permalink raw reply	[flat|nested] 42+ messages in thread

* Re: [PATCH v1 17/17] drm/mediatek: add DSC support for MT8195
  2021-07-07  7:35   ` CK Hu
@ 2021-07-10  7:55     ` Jason-JH Lin
  0 siblings, 0 replies; 42+ messages in thread
From: Jason-JH Lin @ 2021-07-10  7:55 UTC (permalink / raw)
  To: CK Hu
  Cc: chunkuang.hu, matthias.bgg, linux-arm-kernel, linux-mediatek,
	linux-kernel, Project_Global_Chrome_Upstream_Group, fshao,
	nancy.lin, singo.chang

HiCK,

On Wed, 2021-07-07 at 15:35 +0800, CK Hu wrote:
> Hi, Jason:
> 
> On Wed, 2021-07-07 at 12:12 +0800, jason-jh.lin wrote:
> > 1. Add DSC module file.
> > 2. Add mtk_panel_ext source file to get the mtk_panel_dsc_params
> >    from panel.
> > 3. Add DSC related path to mtk-mmsys routing table.
> > 
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/Makefile           |   4 +-
> >  drivers/gpu/drm/mediatek/mtk_disp_drv.h     |   8 +
> >  drivers/gpu/drm/mediatek/mtk_disp_dsc.c     | 286 ++++++++++++++++
> >  drivers/gpu/drm/mediatek/mtk_drm_crtc.h     |   1 +
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |  13 +
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |   1 +
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.c      |   4 +
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.h      |   1 +
> >  drivers/gpu/drm/mediatek/mtk_panel_ext.c    | 136 ++++++++
> >  drivers/gpu/drm/mediatek/mtk_panel_ext.h    | 344
> > ++++++++++++++++++++
> >  drivers/soc/mediatek/mt8195-mmsys.h         |  18 +
> >  drivers/soc/mediatek/mtk-mutex.c            |   1 +
> >  include/linux/soc/mediatek/mtk-mmsys.h      |   3 +
> >  13 files changed, 819 insertions(+), 1 deletion(-)
> >  create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_dsc.c
> >  create mode 100644 drivers/gpu/drm/mediatek/mtk_panel_ext.c
> >  create mode 100644 drivers/gpu/drm/mediatek/mtk_panel_ext.h
> > 
> > diff --git a/drivers/gpu/drm/mediatek/Makefile
> > b/drivers/gpu/drm/mediatek/Makefile
> > index 5fd95b9d5aae..4dc0b2901a22 100644
> > --- a/drivers/gpu/drm/mediatek/Makefile
> > +++ b/drivers/gpu/drm/mediatek/Makefile
> > @@ -6,13 +6,15 @@ mediatek-drm-y := mtk_disp_ccorr.o \
> >  		  mtk_disp_ovl.o \
> >  		  mtk_disp_rdma.o \
> >  		  mtk_disp_merge.o \
> > +		  mtk_disp_dsc.o \
> >  		  mtk_drm_crtc.o \
> >  		  mtk_drm_ddp_comp.o \
> >  		  mtk_drm_drv.o \
> >  		  mtk_drm_gem.o \
> >  		  mtk_drm_plane.o \
> >  		  mtk_dsi.o \
> > -		  mtk_dpi.o
> > +		  mtk_dpi.o \
> > +		  mtk_panel_ext.o
> >  
> >  obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
> >  
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > index 7fd5260e2a72..11a6c9d6cff3 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > @@ -100,4 +100,12 @@ void mtk_merge_config(struct device *dev,
> > unsigned int width,
> >  void mtk_merge_start(struct device *dev);
> >  void mtk_merge_stop(struct device *dev);
> >  
> > +int mtk_dsc_clk_enable(struct device *dev);
> > +void mtk_dsc_clk_disable(struct device *dev);
> > +void mtk_dsc_config(struct device *dev, unsigned int width,
> > +		     unsigned int height, unsigned int vrefresh,
> > +		     unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> > +void mtk_dsc_start(struct device *dev);
> > +void mtk_dsc_stop(struct device *dev);
> > +
> >  #endif
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_dsc.c
> > b/drivers/gpu/drm/mediatek/mtk_disp_dsc.c
> > new file mode 100644
> > index 000000000000..5da820feead5
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_dsc.c
> > @@ -0,0 +1,286 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (c) 2019 MediaTek Inc.
> 
> 2021
> 
OK, I'll fix it.

> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/component.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_irq.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/pm_runtime.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> > +
> > +#include "mtk_drm_crtc.h"
> > +#include "mtk_drm_ddp_comp.h"
> > +#include "mtk_drm_gem.h"
> > +#include "mtk_disp_drv.h"
> > +#ifdef CONFIG_MTK_DPTX_SUPPORT
> > +#include "mtk_dp_api.h"
> > +#endif
> > +
> > +#define DISP_REG_DSC_CON			0x0000
> > +#define DSC_EN						BIT(0)
> > +#define DSC_DUAL_INOUT				BIT(2)
> > +#define DSC_IN_SRC_SEL				BIT(3)
> > +#define DSC_BYPASS					BIT(4)
> > +#define DSC_RELAY					BIT(5)
> > +#define DSC_EMPTY_FLAG_SEL			0xc000
> > +#define DSC_UFOE_SEL				BIT(16)
> > +#define DISP_REG_DSC_OBUF			0x0070
> > +
> > +struct mtk_disp_dsc_data {
> > +	bool support_shadow;
> > +};
> 
> Now just support mt8195-dsc, so remove this.
> 
OK, I'll remove it.

> > +
> > +/**
> > + * struct mtk_disp_dsc - DISP_DSC driver structure
> > + * @clk - clk of dsc hardware
> > + * @regs - hardware register address of dsc
> > + * @ddp_comp - structure containing type enum and hardware
> > resources
> > + * @cmdq_reg - structure containing cmdq hardware resource
> > + * @data - dsc driver data
> > + * @enable - enable dsc hardward
> > + */
> > +struct mtk_disp_dsc {
> > +	struct clk *clk;
> > +	void __iomem *regs;
> > +	struct mtk_ddp_comp	ddp_comp;
> 
> Sub driver should get rid of ddp_comp.
> 
OK, I'll remove it.

> > +	struct cmdq_client_reg		cmdq_reg;
> > +	const struct mtk_disp_dsc_data *data;
> > +	int enable;
> 
> enable is always false, so remove it.
> 
OK, I'll remove it.

> > +};
> > +
> > +void mtk_dsc_start(struct device *dev)
> > +{
> > +	struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
> > +	void __iomem *baddr = dsc->regs;
> > +	int ret = 0;
> > +
> > +	ret = pm_runtime_get_sync(dev);
> > +	if (ret < 0)
> > +		DRM_ERROR("Failed to enable power domain: %d\n", ret);
> > +
> > +	if (dsc->enable) {
> > +		int high = BIT(14);
> > +		int obud_sw = BIT(31);
> > +		int obud_size = 706; /* unit is 6 byte */
> > +
> > +		/* DSC Empty flag always high */
> > +		mtk_ddp_write_mask(NULL, high,
> > +			&dsc->cmdq_reg, baddr,
> > +			DISP_REG_DSC_CON, DSC_EMPTY_FLAG_SEL);
> > +
> > +		/* DSC output buffer as FHD(plus) */
> > +		mtk_ddp_write_mask(NULL, (obud_sw | obud_size),
> > +			&dsc->cmdq_reg, baddr,
> > +			DISP_REG_DSC_OBUF, ~0);
> > +	}
> > +
> > +	mtk_ddp_write_mask(NULL, DSC_EN,
> > +		&dsc->cmdq_reg, baddr,
> > +		DISP_REG_DSC_CON, DSC_EN);
> > +
> > +	pr_debug("dsc_start:0x%x\n", readl(baddr + DISP_REG_DSC_CON));
> > +}
> > +
> > +void mtk_dsc_stop(struct device *dev)
> > +{
> > +	struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
> > +	void __iomem *baddr = dsc->regs;
> > +	int ret = 0;
> > +
> > +	mtk_ddp_write_mask(NULL, 0x0, &dsc->cmdq_reg, baddr,
> > +		DISP_REG_DSC_CON, DSC_EN);
> > +
> > +	pr_debug("dsc_stop:0x%x\n", readl(baddr + DISP_REG_DSC_CON));
> > +
> > +	ret = pm_runtime_put(dev);
> > +	if (ret < 0)
> > +		DRM_ERROR("Failed to disable power domain: %d\n", ret);
> > +}
> > +
> > +int mtk_dsc_clk_enable(struct device *dev)
> > +{
> > +	struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
> > +
> > +	return clk_prepare_enable(dsc->clk);
> > +}
> > +
> > +void mtk_dsc_clk_disable(struct device *dev)
> > +{
> > +	struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
> > +
> > +	clk_disable_unprepare(dsc->clk);
> > +}
> > +
> > +static struct mtk_panel_dsc_params *mtk_dsc_default_setting(void)
> > +{
> > +	static struct mtk_panel_dsc_params dsc_params = {
> > +		.enable = 0, /* 0: bypass mode */
> > +		.ver = 2,
> > +		.slice_mode = 1,
> > +		.rgb_swap = 0,
> > +		.dsc_cfg = 0x12, /* flatness_det_thr, 8bit */
> > +		.rct_on = 1, // default
> > +		.bit_per_channel = 8,
> > +		.dsc_line_buf_depth = 13, /* 9, 11: for 10bit */
> > +		.bp_enable = 1, /* align vend */
> > +		.bit_per_pixel = 128, /* 16 x bpp */
> > +		.pic_height = 2160,
> > +		.pic_width = 3840, /* for dp port 4k scenario */
> > +		.slice_height = 8,
> > +		.slice_width = 1920, /* frame_width/slice mode */
> > +		.chunk_size = 1920,
> > +		.xmit_delay = 512,
> > +		.dec_delay = 1216,
> > +		.scale_value = 32,
> > +		.increment_interval = 286,
> > +		.decrement_interval = 26,
> > +		.line_bpg_offset = 12,
> > +		.nfl_bpg_offset = 3511,
> > +		.slice_bpg_offset = 916,
> > +		.initial_offset = 6144,
> > +		.final_offset = 4336,
> > +		.flatness_minqp = 3,
> > +		.flatness_maxqp = 12,
> > +		.rc_model_size = 8192,
> > +		.rc_edge_factor = 6,
> > +		.rc_quant_incr_limit0 = 11,
> > +		.rc_quant_incr_limit1 = 11,
> > +		.rc_tgt_offset_hi = 3,
> > +		.rc_tgt_offset_lo = 3,
> > +	};
> > +
> > +	return &dsc_params;
> > +}
> 
> Useless, so remove.
> 
OK, I'll remove it.

> > +
> > +void mtk_dsc_config(struct device *dev, unsigned int w,
> > +				unsigned int h, unsigned int vrefresh,
> > +				unsigned int bpc, struct cmdq_pkt
> > *handle)
> > +{
> > +	struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
> > +	struct mtk_ddp_comp *comp = &dsc->ddp_comp;
> > +	struct mtk_panel_dsc_params *dsc_params;
> > +
> > +	dsc_params = mtk_dsc_default_setting();
> > +
> > +	if (dsc_params->enable == 1) {
> > +		/* dsc enable mode not support yet */
> > +		pr_debug("comp_id:%d, w:%d, h:%d\n",
> > +			comp->id, w, h);
> > +		pr_debug("slice_mode:%d, slice(%d,%d), bpp:%d\n",
> > +			dsc_params->slice_mode, dsc_params-
> > >slice_width,
> > +			dsc_params->slice_height, dsc_params-
> > >bit_per_pixel);
> > +	} else {
> > +		/* dsc bypass mode */
> > +		mtk_ddp_write_mask(handle, DSC_BYPASS,
> > +			&dsc->cmdq_reg, dsc->regs,
> > +			DISP_REG_DSC_CON, DSC_BYPASS);
> > +		mtk_ddp_write_mask(handle, DSC_UFOE_SEL,
> > +			&dsc->cmdq_reg, dsc->regs,
> > +			DISP_REG_DSC_CON, DSC_UFOE_SEL);
> > +		mtk_ddp_write_mask(handle, DSC_DUAL_INOUT,
> > +			&dsc->cmdq_reg, dsc->regs,
> > +			DISP_REG_DSC_CON, DSC_DUAL_INOUT);
> > +		dsc->enable = false;
> > +	}
> 
> Keep only bypass mode.
> 
OK, I'll fix it.
> > +}
> > +
> > +static int mtk_disp_dsc_bind(struct device *dev, struct device
> > *master,
> > +				  void *data)
> > +{
> > +	return 0;
> > +}
> > +
> > +static void mtk_disp_dsc_unbind(struct device *dev, struct device
> > *master,
> > +				 void *data)
> > +{
> > +}
> > +
> > +static const struct component_ops mtk_disp_dsc_component_ops = {
> > +	.bind = mtk_disp_dsc_bind,
> > +	.unbind = mtk_disp_dsc_unbind,
> > +};
> > +
> > +static int mtk_disp_dsc_probe(struct platform_device *pdev)
> > +{
> > +	struct device *dev = &pdev->dev;
> > +	struct resource *res;
> > +	struct mtk_disp_dsc *priv;
> > +	int irq;
> > +	int ret;
> > +
> > +	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> > +	if (!priv)
> > +		return -ENOMEM;
> > +
> > +	irq = platform_get_irq(pdev, 0);
> > +	if (irq < 0)
> > +		return irq;
> > +
> > +	priv->clk = devm_clk_get(dev, NULL);
> > +	if (IS_ERR(priv->clk)) {
> > +		dev_err(dev, "failed to get dsc clk\n");
> > +		return PTR_ERR(priv->clk);
> > +	}
> > +
> > +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > +	priv->regs = devm_ioremap_resource(dev, res);
> > +	if (IS_ERR(priv->regs)) {
> > +		dev_err(dev, "failed to ioremap dsc\n");
> > +		return PTR_ERR(priv->regs);
> > +	}
> > +
> > +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> > +	ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
> > +	if (ret)
> > +		dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
> > +#endif
> > +
> > +	priv->data = of_device_get_match_data(dev);
> > +	platform_set_drvdata(pdev, priv);
> > +
> > +	pm_runtime_enable(dev);
> > +
> > +	ret = component_add(dev, &mtk_disp_dsc_component_ops);
> > +	if (ret != 0) {
> > +		dev_err(dev, "Failed to add component: %d\n", ret);
> > +		pm_runtime_disable(dev);
> > +	}
> > +
> > +	return ret;
> > +}
> > +
> > +static int mtk_disp_dsc_remove(struct platform_device *pdev)
> > +{
> > +	component_del(&pdev->dev, &mtk_disp_dsc_component_ops);
> > +
> > +	pm_runtime_disable(&pdev->dev);
> > +
> > +	return 0;
> > +}
> > +
> > +static const struct mtk_disp_dsc_data mt8195_dsc_driver_data = {
> > +	.support_shadow = false,
> > +};
> > +
> > +static const struct of_device_id mtk_disp_dsc_driver_dt_match[] =
> > {
> > +	{
> > +		.compatible = "mediatek,mt8195-disp-dsc",
> > +		.data = &mt8195_dsc_driver_data
> > +	},
> > +	{},
> > +};
> > +
> > +MODULE_DEVICE_TABLE(of, mtk_disp_dsc_driver_dt_match);
> > +
> > +struct platform_driver mtk_disp_dsc_driver = {
> > +	.probe = mtk_disp_dsc_probe,
> > +	.remove = mtk_disp_dsc_remove,
> > +	.driver = {
> > +		.name = "mediatek-disp-dsc",
> > +		.owner = THIS_MODULE,
> > +		.of_match_table = mtk_disp_dsc_driver_dt_match,
> > +	},
> > +};
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> > index 7419cd0fb424..7b8f9cb96d44 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> > @@ -9,6 +9,7 @@
> >  #include <drm/drm_crtc.h>
> >  #include "mtk_drm_ddp_comp.h"
> >  #include "mtk_drm_plane.h"
> > +#include "mtk_panel_ext.h"
> >  
> >  #define MTK_LUT_SIZE	512
> >  #define MTK_MAX_BPC	10
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > index 2ccf3db1950d..b68bde6eb6ed 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > @@ -347,6 +347,14 @@ static const struct mtk_ddp_comp_funcs
> > ddp_merge = {
> >  	.config = mtk_merge_config,
> >  };
> >  
> > +static const struct mtk_ddp_comp_funcs ddp_dsc = {
> > +	.config = mtk_dsc_config,
> > +	.start = mtk_dsc_start,
> > +	.stop = mtk_dsc_stop,
> > +	.clk_enable = mtk_dsc_clk_enable,
> > +	.clk_disable = mtk_dsc_clk_disable,
> > +};
> > +
> >  static const struct mtk_ddp_comp_funcs ddp_ufoe = {
> >  	.clk_enable = mtk_ddp_clk_enable,
> >  	.clk_disable = mtk_ddp_clk_disable,
> > @@ -371,6 +379,7 @@ static const char * const
> > mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> >  	[MTK_DISP_OD] = "od",
> >  	[MTK_DISP_BLS] = "bls",
> >  	[MTK_DISP_MERGE] = "merge",
> > +	[MTK_DISP_DSC] = "dsc",
> >  };
> >  
> >  struct mtk_ddp_comp_match {
> > @@ -412,6 +421,9 @@ static const struct mtk_ddp_comp_match
> > mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
> >  	[DDP_COMPONENT_MERGE3]	= { MTK_DISP_MERGE,	3,
> > &ddp_merge },
> >  	[DDP_COMPONENT_MERGE4]	= { MTK_DISP_MERGE,	4,
> > &ddp_merge },
> >  	[DDP_COMPONENT_MERGE5]	= { MTK_DISP_MERGE,	5,
> > &ddp_merge },
> > +	[DDP_COMPONENT_DSC0]	= { MTK_DISP_DSC,	0, &ddp_dsc
> > },
> > +	[DDP_COMPONENT_DSC1]	= { MTK_DISP_DSC,	1, &ddp_dsc
> > },
> > +	[DDP_COMPONENT_DSC1_VIRTUAL0]	= { MTK_DISP_DSC,	-1,
> > &ddp_dsc },
> >  	[DDP_COMPONENT_UFOE]	= { MTK_DISP_UFOE,	0,
> > &ddp_ufoe },
> >  	[DDP_COMPONENT_WDMA0]	= { MTK_DISP_WDMA,	0, NULL },
> >  	[DDP_COMPONENT_WDMA1]	= { MTK_DISP_WDMA,	1, NULL },
> > @@ -531,6 +543,7 @@ int mtk_ddp_comp_init(struct device_node *node,
> > struct mtk_ddp_comp *comp,
> >  	    type == MTK_DISP_COLOR ||
> >  	    type == MTK_DISP_GAMMA ||
> >  	    type == MTK_DISP_MERGE ||
> > +	    type == MTK_DISP_DSC ||
> >  	    type == MTK_DPI ||
> >  	    type == MTK_DSI ||
> >  	    type == MTK_DISP_OVL ||
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > index 038775b4531b..b4f6b52dac69 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > @@ -35,6 +35,7 @@ enum mtk_ddp_comp_type {
> >  	MTK_DISP_OD,
> >  	MTK_DISP_BLS,
> >  	MTK_DISP_MERGE,
> > +	MTK_DISP_DSC,
> >  	MTK_DDP_COMP_TYPE_MAX,
> >  };
> >  
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > index f891316008aa..af3e69e0edbe 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > @@ -464,6 +464,8 @@ static const struct of_device_id
> > mtk_ddp_comp_dt_ids[] = {
> >  	  .data = (void *)MTK_DISP_DITHER },
> >  	{ .compatible = "mediatek,mt8195-disp-merge",
> >  	  .data = (void *)MTK_DISP_MERGE },
> > +	{ .compatible = "mediatek,mt8195-disp-dsc",
> > +	  .data = (void *)MTK_DISP_DSC },
> >  	{ .compatible = "mediatek,mt8173-disp-ufoe",
> >  	  .data = (void *)MTK_DISP_UFOE },
> >  	{ .compatible = "mediatek,mt2701-dsi",
> > @@ -582,6 +584,7 @@ static int mtk_drm_probe(struct platform_device
> > *pdev)
> >  		    comp_type == MTK_DISP_COLOR ||
> >  		    comp_type == MTK_DISP_GAMMA ||
> >  		    comp_type == MTK_DISP_MERGE ||
> > +		    comp_type == MTK_DISP_DSC ||
> >  		    comp_type == MTK_DISP_OVL ||
> >  		    comp_type == MTK_DISP_OVL_2L ||
> >  		    comp_type == MTK_DISP_RDMA ||
> > @@ -687,6 +690,7 @@ static struct platform_driver * const
> > mtk_drm_drivers[] = {
> >  	&mtk_dpi_driver,
> >  	&mtk_drm_platform_driver,
> >  	&mtk_disp_merge_driver,
> > +	&mtk_disp_dsc_driver,
> >  	&mtk_dsi_driver,
> >  };
> >  
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > index 18548a373626..7f821b96aac3 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > @@ -52,6 +52,7 @@ extern struct platform_driver
> > mtk_disp_gamma_driver;
> >  extern struct platform_driver mtk_disp_ovl_driver;
> >  extern struct platform_driver mtk_disp_rdma_driver;
> >  extern struct platform_driver mtk_disp_merge_driver;
> > +extern struct platform_driver mtk_disp_dsc_driver;
> >  extern struct platform_driver mtk_dpi_driver;
> >  extern struct platform_driver mtk_dsi_driver;
> >  
> > diff --git a/drivers/gpu/drm/mediatek/mtk_panel_ext.c
> > b/drivers/gpu/drm/mediatek/mtk_panel_ext.c
> > new file mode 100644
> > index 000000000000..5887a1cd08bc
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_panel_ext.c
> > @@ -0,0 +1,136 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (c) 2019 MediaTek Inc.
> > + */
> > +
> > +#include <linux/err.h>
> > +#include <linux/module.h>
> > +
> > +#include <drm/drm_atomic_helper.h>
> > +#include <drm/drm_crtc_helper.h>
> > +#include <drm/drm_mipi_dsi.h>
> > +
> > +#include <drm/drm_panel.h>
> > +
> > +#include "mtk_panel_ext.h"
> > +
> > +struct _panel_rst_ctx {
> > +	struct drm_panel *panel;
> > +	panel_tch_rst rst_cb;
> > +};
> > +
> > +static DEFINE_MUTEX(panel_ext_lock);
> > +static LIST_HEAD(panel_ext_list);
> > +static struct _panel_rst_ctx panel_rst_ctx;
> > +
> > +void mtk_panel_init(struct mtk_panel_ctx *ctx)
> > +{
> > +	INIT_LIST_HEAD(&ctx->list);
> > +}
> > +
> > +void mtk_panel_add(struct mtk_panel_ctx *ctx)
> > +{
> > +	mutex_lock(&panel_ext_lock);
> > +	list_add_tail(&ctx->list, &panel_ext_list);
> > +	mutex_unlock(&panel_ext_lock);
> > +}
> > +
> > +void mtk_panel_remove(struct mtk_panel_ctx *ctx)
> > +{
> > +	mutex_lock(&panel_ext_lock);
> > +	list_del_init(&ctx->list);
> > +	mutex_unlock(&panel_ext_lock);
> > +}
> > +
> > +int mtk_panel_attach(struct mtk_panel_ctx *ctx, struct drm_panel
> > *panel)
> > +{
> > +	if (ctx->panel)
> > +		return -EBUSY;
> > +
> > +	ctx->panel = panel;
> > +
> > +	return 0;
> > +}
> > +
> > +int mtk_panel_tch_handle_reg(struct drm_panel *panel)
> > +{
> > +	mutex_lock(&panel_ext_lock);
> > +	if (panel_rst_ctx.panel) {
> > +		mutex_unlock(&panel_ext_lock);
> > +		return -EEXIST;
> > +	}
> > +	panel_rst_ctx.panel = panel;
> > +	mutex_unlock(&panel_ext_lock);
> > +
> > +	return 0;
> > +}
> > +
> > +void **mtk_panel_tch_handle_init(void)
> > +{
> > +	return (void **)&panel_rst_ctx.rst_cb;
> > +}
> > +
> > +int mtk_panel_tch_rst(struct drm_panel *panel)
> > +{
> > +	int ret = 0;
> > +
> > +	mutex_lock(&panel_ext_lock);
> > +	if (panel_rst_ctx.rst_cb && panel_rst_ctx.panel == panel)
> > +		panel_rst_ctx.rst_cb();
> > +	else
> > +		ret = -EEXIST;
> > +	mutex_unlock(&panel_ext_lock);
> > +
> > +	return ret;
> > +}
> > +
> > +int mtk_panel_detach(struct mtk_panel_ctx *ctx)
> > +{
> > +	ctx->panel = NULL;
> > +
> > +	return 0;
> > +}
> > +
> > +int mtk_panel_ext_create(struct device *dev,
> > +			 struct mtk_panel_params *ext_params,
> > +			 struct mtk_panel_funcs *ext_funcs,
> > +			 struct drm_panel *panel)
> > +{
> > +	struct mtk_panel_ctx *ext_ctx;
> > +	struct mtk_panel_ext *ext;
> > +
> > +	ext_ctx = devm_kzalloc(dev, sizeof(struct mtk_panel_ctx),
> > GFP_KERNEL);
> > +	if (!ext_ctx)
> > +		return -ENOMEM;
> > +
> > +	ext = devm_kzalloc(dev, sizeof(struct mtk_panel_ext),
> > GFP_KERNEL);
> > +	if (!ext)
> > +		return -ENOMEM;
> > +
> > +	mtk_panel_init(ext_ctx);
> > +	ext->params = ext_params;
> > +	ext->funcs = ext_funcs;
> > +	ext_ctx->ext = ext;
> > +
> > +	mtk_panel_add(ext_ctx);
> > +	mtk_panel_attach(ext_ctx, panel);
> > +
> > +	return 0;
> > +}
> > +
> > +struct mtk_panel_ext *find_panel_ext(struct drm_panel *panel)
> > +{
> > +	struct mtk_panel_ctx *ctx;
> > +
> > +	mutex_lock(&panel_ext_lock);
> > +
> > +	list_for_each_entry(ctx, &panel_ext_list, list) {
> > +		if (ctx->panel == panel) {
> > +			mutex_unlock(&panel_ext_lock);
> > +			return ctx->ext;
> > +		}
> > +	}
> > +
> > +	mutex_unlock(&panel_ext_lock);
> > +	return NULL;
> > +}
> > diff --git a/drivers/gpu/drm/mediatek/mtk_panel_ext.h
> > b/drivers/gpu/drm/mediatek/mtk_panel_ext.h
> > new file mode 100644
> > index 000000000000..f828d468817d
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_panel_ext.h
> > @@ -0,0 +1,344 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Copyright (c) 2019 MediaTek Inc.
> > + */
> > +
> > +#ifndef __MTK_PANEL_EXT_H__
> > +#define __MTK_PANEL_EXT_H__
> > +
> > +#include <drm/drm_panel.h>
> > +
> > +#define RT_MAX_NUM 10
> > +#define ESD_CHECK_NUM 3
> > +#define MAX_TX_CMD_NUM 20
> > +#define MAX_RX_CMD_NUM 20
> > +#define READ_DDIC_SLOT_NUM 4
> > +#define MAX_DYN_CMD_NUM 20
> > +
> > +struct mtk_dsi;
> > +struct cmdq_pkt;
> > +struct mtk_panel_para_table {
> > +	u8 count;
> > +	u8 para_list[64];
> > +};
> > +
> > +/*
> > + *	DSI data type:
> > + *	DSI_DCS_WRITE_SHORT_PACKET_NO_PARAM		0x05
> > + *	DSI_DCS_WRITE_SHORT_PACKET_1_PARAM		0x15
> > + *	DSI_DCS_WRITE_LONG_PACKET				0x39
> > + *	DSI_DCS_READ_NO_PARAM					0x0
> > 6
> > +
> > + *	DSI_GERNERIC_WRITE_SHORT_NO_PARAM		0x03
> > + *	DSI_GERNERIC_WRITE_SHORT_1_PARAM		0x13
> > + *	DSI_GERNERIC_WRITE_SHORT_1_PARAM		0x23
> > + *	DSI_GERNERIC_WRITE_LONG_PACKET			0x29
> > + *	DSI_GERNERIC_READ_NO_PARAM				0x04
> > + *	DSI_GERNERIC_READ_1_PARAM				0x14
> > + *	DSI_GERNERIC_READ_2_PARAM				0x24
> > + */
> > +
> > +/**
> > + * struct mtk_ddic_dsi_msg - MTK write/read DDIC RG cmd buffer
> > + * @channel: virtual channel id
> > + * @flags: flags controlling this message transmission
> > + * @type: payload data type array
> > + * @tx_len: length of @tx_buf
> > + * @tx_buf: data array to be written
> > + * @tx_cmd_num: tx cmd number
> > + * @rx_len: length of @rx_buf
> > + * @rx_buf: data array to be read, or NULL
> > + * @rx_cmd_num: rx cmd number
> > + */
> > +struct mtk_ddic_dsi_msg {
> > +	u8 channel;
> > +	u16 flags;
> > +
> > +	u8 type[MAX_TX_CMD_NUM];
> > +	size_t tx_len[MAX_TX_CMD_NUM];
> > +	const void *tx_buf[MAX_TX_CMD_NUM];
> > +	size_t tx_cmd_num;
> > +
> > +	size_t rx_len[MAX_RX_CMD_NUM];
> > +	void *rx_buf[MAX_RX_CMD_NUM];
> > +	size_t rx_cmd_num;
> > +};
> > +
> > +struct DSI_RX_DATA_REG {
> > +	unsigned char byte0;
> > +	unsigned char byte1;
> > +	unsigned char byte2;
> > +	unsigned char byte3;
> > +};
> > +
> > +typedef void (*dcs_write_gce) (struct mtk_dsi *dsi, struct
> > cmdq_pkt *handle,
> > +				const void *data, size_t len);
> > +typedef void (*dcs_grp_write_gce) (struct mtk_dsi *dsi, struct
> > cmdq_pkt *handle,
> > +				struct mtk_panel_para_table
> > *para_table,
> > +				unsigned int para_size);
> > +typedef int (*panel_tch_rst) (void);
> > +
> > +enum MTK_PANEL_OUTPUT_MODE {
> > +	MTK_PANEL_SINGLE_PORT = 0x0,
> > +	MTK_PANEL_DSC_SINGLE_PORT,
> > +	MTK_PANEL_DUAL_PORT,
> > +};
> > +
> > +struct esd_check_item {
> > +	unsigned char cmd;
> > +	unsigned char count;
> > +	unsigned char para_list[RT_MAX_NUM];
> > +	unsigned char mask_list[RT_MAX_NUM];
> > +};
> > +
> > +enum MTK_PANEL_MODE_SWITCH_STAGE {
> > +	BEFORE_DSI_POWERDOWN,
> > +	AFTER_DSI_POWERON,
> > +};
> > +
> > +enum MIPITX_PHY_PORT {
> > +	MIPITX_PHY_PORT_0 = 0,
> > +	MIPITX_PHY_PORT_1,
> > +	MIPITX_PHY_PORT_NUM
> > +};
> > +
> > +enum MIPITX_PHY_LANE_SWAP {
> > +	MIPITX_PHY_LANE_0 = 0,
> > +	MIPITX_PHY_LANE_1,
> > +	MIPITX_PHY_LANE_2,
> > +	MIPITX_PHY_LANE_3,
> > +	MIPITX_PHY_LANE_CK,
> > +	MIPITX_PHY_LANE_RX,
> > +	MIPITX_PHY_LANE_NUM
> > +};
> > +
> > +enum FPS_CHANGE_INDEX {
> > +	DYNFPS_NOT_DEFINED = 0,
> > +	DYNFPS_DSI_VFP = 1,
> > +	DYNFPS_DSI_HFP = 2,
> > +	DYNFPS_DSI_MIPI_CLK = 4,
> > +};
> > +
> > +struct mtk_panel_dsc_params {
> > +	unsigned int enable;
> > +	unsigned int ver; /* [7:4] major [3:0] minor */
> > +	unsigned int slice_mode;
> > +	unsigned int rgb_swap;
> > +	unsigned int dsc_cfg;
> > +	unsigned int rct_on;
> > +	unsigned int bit_per_channel;
> > +	unsigned int dsc_line_buf_depth;
> > +	unsigned int bp_enable;
> > +	unsigned int bit_per_pixel;
> > +	unsigned int pic_height; /* need to check */
> > +	unsigned int pic_width;  /* need to check */
> > +	unsigned int slice_height;
> > +	unsigned int slice_width;
> > +	unsigned int chunk_size;
> > +	unsigned int xmit_delay;
> > +	unsigned int dec_delay;
> > +	unsigned int scale_value;
> > +	unsigned int increment_interval;
> > +	unsigned int decrement_interval;
> > +	unsigned int line_bpg_offset;
> > +	unsigned int nfl_bpg_offset;
> > +	unsigned int slice_bpg_offset;
> > +	unsigned int initial_offset;
> > +	unsigned int final_offset;
> > +	unsigned int flatness_minqp;
> > +	unsigned int flatness_maxqp;
> > +	unsigned int rc_model_size;
> > +	unsigned int rc_edge_factor;
> > +	unsigned int rc_quant_incr_limit0;
> > +	unsigned int rc_quant_incr_limit1;
> > +	unsigned int rc_tgt_offset_hi;
> > +	unsigned int rc_tgt_offset_lo;
> > +};
> > +
> > +struct mtk_dsi_phy_timcon {
> > +	unsigned int hs_trail;
> > +	unsigned int hs_prpr;
> > +	unsigned int hs_zero;
> > +	unsigned int lpx;
> > +	unsigned int ta_get;
> > +	unsigned int ta_sure;
> > +	unsigned int ta_go;
> > +	unsigned int da_hs_exit;
> > +	unsigned int clk_trail;
> > +	unsigned int cont_det;
> > +	unsigned int da_hs_sync;
> > +	unsigned int clk_zero;
> > +	unsigned int clk_hs_prpr;
> > +	unsigned int clk_hs_exit;
> > +	unsigned int clk_hs_post;
> > +};
> > +
> > +struct dynamic_mipi_params {
> > +	unsigned int switch_en;
> > +	unsigned int pll_clk;
> > +	unsigned int data_rate;
> > +
> > +	unsigned int vsa;
> > +	unsigned int vbp;
> > +	unsigned int vfp;
> > +	unsigned int vfp_lp_dyn;
> > +
> > +	unsigned int hsa;
> > +	unsigned int hbp;
> > +	unsigned int hfp;
> > +};
> > +
> > +struct dfps_switch_cmd {
> > +	unsigned int src_fps;
> > +	unsigned int cmd_num;
> > +	unsigned char para_list[64];
> > +};
> > +
> > +struct dynamic_fps_params {
> > +	unsigned int switch_en;
> > +	unsigned int vact_timing_fps;
> > +	struct dfps_switch_cmd dfps_cmd_table[MAX_DYN_CMD_NUM];
> > +
> > +	unsigned int lfr_enable;
> > +	unsigned int lfr_minimum_fps;
> > +};
> > +
> > +struct mtk_panel_params {
> > +	unsigned int pll_clk;
> > +	unsigned int data_rate;
> > +	struct mtk_dsi_phy_timcon phy_timcon;
> > +	unsigned int vfp_low_power;
> > +	struct dynamic_mipi_params dyn;
> > +	struct dynamic_fps_params dyn_fps;
> > +	unsigned int cust_esd_check;
> > +	unsigned int esd_check_enable;
> > +	struct esd_check_item lcm_esd_check_table[ESD_CHECK_NUM];
> > +	unsigned int ssc_disable;
> > +	unsigned int ssc_range;
> > +	int lcm_color_mode;
> > +	unsigned int min_luminance;
> > +	unsigned int average_luminance;
> > +	unsigned int max_luminance;
> > +	unsigned int round_corner_en;
> > +	unsigned int corner_pattern_height;
> > +	unsigned int corner_pattern_height_bot;
> > +	unsigned int corner_pattern_tp_size;
> > +	void *corner_pattern_lt_addr;
> > +	unsigned int physical_width_um;
> > +	unsigned int physical_height_um;
> > +	unsigned int lane_swap_en;
> > +	unsigned int is_cphy;
> > +	enum MIPITX_PHY_LANE_SWAP
> > +		lane_swap[MIPITX_PHY_PORT_NUM][MIPITX_PHY_LANE_NUM];
> > +	struct mtk_panel_dsc_params dsc_params;
> > +	unsigned int output_mode;
> > +	unsigned int hbm_en_time;
> > +	unsigned int hbm_dis_time;
> > +	unsigned int lcm_index;
> > +	unsigned int wait_sof_before_dec_vfp;
> > +	unsigned int doze_delay;
> > +};
> > +
> > +struct mtk_panel_ext {
> > +	struct mtk_panel_funcs *funcs;
> > +	struct mtk_panel_params *params;
> > +};
> > +
> > +struct mtk_panel_ctx {
> > +	struct drm_panel *panel;
> > +	struct mtk_panel_ext *ext;
> > +
> > +	struct list_head list;
> > +};
> > +
> > +struct mtk_panel_funcs {
> > +	int (*set_backlight_cmdq)(void *dsi_drv, dcs_write_gce cb,
> > +		 void *handle, unsigned int level);
> > +	int (*set_aod_light_mode)(void *dsi_drv, dcs_write_gce cb,
> > +		 void *handle, unsigned int mode);
> > +	int (*set_backlight_grp_cmdq)(void *dsi_drv, dcs_grp_write_gce
> > cb,
> > +		 void *handle, unsigned int level);
> > +	int (*reset)(struct drm_panel *panel, int on);
> > +	int (*ata_check)(struct drm_panel *panel);
> > +	int (*ext_param_set)(struct drm_panel *panel, unsigned int
> > mode);
> > +	int (*ext_param_get)(struct mtk_panel_params *ext_para,
> > +		 unsigned int mode);
> > +	int (*mode_switch)(struct drm_panel *panel, unsigned int
> > cur_mode,
> > +		 unsigned int dst_mode, enum
> > MTK_PANEL_MODE_SWITCH_STAGE stage);
> > +	int (*get_virtual_heigh)(void);
> > +	int (*get_virtual_width)(void);
> > +	/**
> > +	 * @doze_enable_start:
> > +	 *
> > +	 * Call the @doze_enable_start before starting AOD mode.
> > +	 * The LCM off may add here to avoid panel show unexpected
> > +	 * content when switching to specific panel low power mode.
> > +	 */
> > +	int (*doze_enable_start)(struct drm_panel *panel,
> > +		 void *dsi_drv, dcs_write_gce cb, void *handle);
> > +
> > +	/**
> > +	 * @doze_enable:
> > +	 *
> > +	 * Call the @doze_enable starts AOD mode.
> > +	 */
> > +	int (*doze_enable)(struct drm_panel *panel,
> > +		 void *dsi_drv, dcs_write_gce cb, void *handle);
> > +
> > +	/**
> > +	 * @doze_disable:
> > +	 *
> > +	 * Call the @doze_disable before ending AOD mode.
> > +	 */
> > +	int (*doze_disable)(struct drm_panel *panel,
> > +		 void *dsi_drv, dcs_write_gce cb, void *handle);
> > +
> > +	/**
> > +	 * @doze_post_disp_on:
> > +	 *
> > +	 * In some situation, the LCM off may set in @doze_enable &
> > @disable.
> > +	 * After LCM switch to the new mode stable, system call
> > +	 * @doze_post_disp_on to turn on panel.
> > +	 */
> > +	int (*doze_post_disp_on)(struct drm_panel *panel,
> > +		 void *dsi_drv, dcs_write_gce cb, void *handle);
> > +
> > +	/**
> > +	 * @doze_area:
> > +	 *
> > +	 * Send the panel area in command here.
> > +	 */
> > +	int (*doze_area)(struct drm_panel *panel,
> > +		 void *dsi_drv, dcs_write_gce cb, void *handle);
> > +
> > +	/**
> > +	 * @doze_get_mode_flags:
> > +	 *
> > +	 * If CV switch is needed for doze mode, fill the mode_flags in
> > this
> > +	 * function for both CMD and VDO mode.
> > +	 */
> > +	unsigned long (*doze_get_mode_flags)(struct drm_panel *panel,
> > +				   int aod_en);
> > +
> > +	int (*hbm_set_cmdq)(struct drm_panel *panel, void *dsi_drv,
> > +		 dcs_write_gce cb, void *handle, bool en);
> > +	void (*hbm_get_state)(struct drm_panel *panel, bool *state);
> > +	void (*hbm_get_wait_state)(struct drm_panel *panel, bool
> > *wait);
> > +	bool (*hbm_set_wait_state)(struct drm_panel *panel, bool wait);
> > +};
> > +
> > +void mtk_panel_init(struct mtk_panel_ctx *ctx);
> > +void mtk_panel_add(struct mtk_panel_ctx *ctx);
> > +void mtk_panel_remove(struct mtk_panel_ctx *ctx);
> > +int mtk_panel_attach(struct mtk_panel_ctx *ctx, struct drm_panel
> > *panel);
> > +int mtk_panel_detach(struct mtk_panel_ctx *ctx);
> > +struct mtk_panel_ext *find_panel_ext(struct drm_panel *panel);
> > +int mtk_panel_ext_create(struct device *dev,
> > +			 struct mtk_panel_params *ext_params,
> > +			 struct mtk_panel_funcs *ext_funcs,
> > +			 struct drm_panel *panel);
> > +int mtk_panel_tch_handle_reg(struct drm_panel *panel);
> > +void **mtk_panel_tch_handle_init(void);
> > +int mtk_panel_tch_rst(struct drm_panel *panel);
> 
> All mtk_panel_ext is useless, so remove.
> 
OK, I'll remove it.

> > +
> > +#endif
> > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> > b/drivers/soc/mediatek/mt8195-mmsys.h
> 
> Move mmsys part to another patch.
> 
> Regards,
> CK
> 
OK, I'll move it.

Regards,
Jason-JH.Lin
> > index 47f3d0ea3c6c..73e9e8286d50 100644
> > --- a/drivers/soc/mediatek/mt8195-mmsys.h
> > +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> > @@ -161,12 +161,30 @@ static const struct mtk_mmsys_routes
> > mmsys_mt8195_routing_table[] = {
> >  	}, {
> >  		DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
> >  		MT8195_VDO0_OVL_MOUT_EN, MOUT_DISP_OVL1_TO_DISP_RDMA1
> > +	}, {
> > +		DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
> > +		MT8195_VDO0_SEL_IN, SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
> > +	}, {
> > +		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
> > +		MT8195_VDO0_SEL_IN,
> > SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
> > +	}, {
> > +		DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
> > +		MT8195_VDO0_SEL_IN, SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
> >  	}, {
> >  		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> >  		MT8195_VDO0_SEL_IN, SEL_IN_DSI0_FROM_DISP_DITHER0
> > +	}, {
> > +		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
> > +		MT8195_VDO0_SEL_OUT, SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
> >  	}, {
> >  		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> >  		MT8195_VDO0_SEL_OUT, DDP_COMPONENT_DSI0
> > +	}, {
> > +		DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
> > +		MT8195_VDO0_SEL_OUT, SOUT_DSC_WRAP0_OUT_TO_DSI0
> > +	}, {
> > +		DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
> > +		MT8195_VDO0_SEL_OUT, SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
> >  	}
> >  };
> >  
> > diff --git a/drivers/soc/mediatek/mtk-mutex.c
> > b/drivers/soc/mediatek/mtk-mutex.c
> > index 84ece5486902..d74eb3f97f1d 100644
> > --- a/drivers/soc/mediatek/mtk-mutex.c
> > +++ b/drivers/soc/mediatek/mtk-mutex.c
> > @@ -285,6 +285,7 @@ static const unsigned int
> > mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> >  	[DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
> >  	[DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
> >  	[DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
> > +	[DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
> >  	[DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
> >  	[DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
> >  };
> > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
> > b/include/linux/soc/mediatek/mtk-mmsys.h
> > index 3135ce82a7f7..89a625743737 100644
> > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > @@ -45,6 +45,9 @@ enum mtk_ddp_comp_id {
> >  	DDP_COMPONENT_MERGE3,
> >  	DDP_COMPONENT_MERGE4,
> >  	DDP_COMPONENT_MERGE5,
> > +	DDP_COMPONENT_DSC0,
> > +	DDP_COMPONENT_DSC1,
> > +	DDP_COMPONENT_DSC1_VIRTUAL0,
> >  	DDP_COMPONENT_ID_MAX,
> >  };
> >  
> 
> 
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^ permalink raw reply	[flat|nested] 42+ messages in thread

end of thread, other threads:[~2021-07-10  8:09 UTC | newest]

Thread overview: 42+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-07-07  4:12 [PATCH v1 00/17] Add MediaTek SoC DRM (vdosys0) support for mt8195 jason-jh.lin
2021-07-07  4:12 ` [PATCH v1 01/17] dt-bindings: mediatek: add definition for mt8195 display jason-jh.lin
2021-07-07  4:33   ` CK Hu
2021-07-10  6:57     ` Jason-JH Lin
2021-07-07  4:12 ` [PATCH v1 02/17] dt-bindings: arm: mediatek: add definition for mt8195 mmsys jason-jh.lin
2021-07-07  4:12 ` [PATCH v1 03/17] arm64: dts: mt8195: add display node for vdosys0 jason-jh.lin
2021-07-07  4:12 ` [PATCH v1 04/17] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0 jason-jh.lin
2021-07-07  4:44   ` CK Hu
2021-07-10  6:58     ` Jason-JH Lin
2021-07-07  4:12 ` [PATCH v1 05/17] drm/mediatek: add mediatek-drm of vdosys0 support for MT8195 jason-jh.lin
2021-07-07  4:48   ` CK Hu
2021-07-10  6:59     ` Jason-JH Lin
2021-07-07  4:12 ` [PATCH v1 06/17] soc: mediatek: add mtk-mutex support for mt8195 jason-jh.lin
2021-07-07  4:52   ` CK Hu
2021-07-10  7:01     ` Jason-JH Lin
2021-07-07  4:12 ` [PATCH v1 07/17] drm/mediatek: add OVL support for MT8195 jason-jh.lin
2021-07-07  5:03   ` CK Hu
2021-07-10  7:05     ` Jason-JH Lin
2021-07-07  4:12 ` [PATCH v1 08/17] drm/mediatek: Add component_del in OVL remove function jason-jh.lin
2021-07-07  5:12   ` CK Hu
2021-07-10  7:06     ` Jason-JH Lin
2021-07-07  4:12 ` [PATCH v1 09/17] drm/mediatek: add OVL support multi-layer jason-jh.lin
2021-07-07  5:43   ` CK Hu
2021-07-10  7:17     ` Jason-JH Lin
2021-07-07  4:12 ` [PATCH v1 10/17] drm/mediatek: add RDMA support for MT8195 jason-jh.lin
2021-07-07  4:12 ` [PATCH v1 11/17] drm/mediatek: add COLOR " jason-jh.lin
2021-07-07  6:01   ` CK Hu
2021-07-10  7:21     ` Jason-JH Lin
2021-07-07  4:12 ` [PATCH v1 12/17] drm/mediatek: add CCORR " jason-jh.lin
2021-07-07  6:02   ` CK Hu
2021-07-10  7:22     ` Jason-JH Lin
2021-07-07  4:12 ` [PATCH v1 13/17] drm/mediatek: Add AAL " jason-jh.lin
2021-07-07  6:14   ` CK Hu
2021-07-10  7:35     ` Jason-JH Lin
2021-07-07  4:12 ` [PATCH v1 14/17] drm/mediatek: add GAMMA " jason-jh.lin
2021-07-07  4:12 ` [PATCH v1 15/17] drm/mediatek: add DITHER " jason-jh.lin
2021-07-07  4:12 ` [PATCH v1 16/17] drm/mediatek: add MERGE " jason-jh.lin
2021-07-07  7:02   ` CK Hu
2021-07-10  7:52     ` Jason-JH Lin
2021-07-07  4:12 ` [PATCH v1 17/17] drm/mediatek: add DSC " jason-jh.lin
2021-07-07  7:35   ` CK Hu
2021-07-10  7:55     ` Jason-JH Lin

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