From: Kewei Xu <kewei.xu@mediatek.com>
To: <wsa@the-dreams.de>
Cc: <matthias.bgg@gmail.com>, <robh+dt@kernel.org>,
<linux-i2c@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
<linux-mediatek@lists.infradead.org>,
<srv_heupstream@mediatek.com>, <leilk.liu@mediatek.com>,
<qii.wang@mediatek.com>, <yuhan.wei@mediatek.com>,
<kewei.xu@mediatek.com>, <ot_daolong.zhu@mediatek.com>,
<liguo.zhang@mediatek.com>
Subject: [PATCH v4 6/8] i2c: mediatek: Add OFFSET_EXT_CONF setting back
Date: Sat, 17 Jul 2021 18:17:57 +0800 [thread overview]
Message-ID: <1626517079-9057-7-git-send-email-kewei.xu@mediatek.com> (raw)
In-Reply-To: <1626517079-9057-1-git-send-email-kewei.xu@mediatek.com>
In the commit be5ce0e97cc7 ("i2c: mediatek: Add i2c ac-timing adjust
support"), we miss setting OFFSET_EXT_CONF register if
i2c->dev_comp->timing_adjust is false, now add it back.
Fixes: be5ce0e97cc7 ("i2c: mediatek: Add i2c ac-timing adjust support")
Signed-off-by: Kewei Xu <kewei.xu@mediatek.com>
---
drivers/i2c/busses/i2c-mt65xx.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
index abdbf27b6eb4..a2a5a4ec1d81 100644
--- a/drivers/i2c/busses/i2c-mt65xx.c
+++ b/drivers/i2c/busses/i2c-mt65xx.c
@@ -41,6 +41,8 @@
#define I2C_HANDSHAKE_RST 0x0020
#define I2C_FIFO_ADDR_CLR 0x0001
#define I2C_DELAY_LEN 0x0002
+#define I2C_ST_START_CON 0x8001
+#define I2C_FS_START_CON 0x1800
#define I2C_TIME_CLR_VALUE 0x0000
#define I2C_TIME_DEFAULT_VALUE 0x0003
#define I2C_WRRD_TRANAC_VALUE 0x0002
@@ -484,6 +486,7 @@ static void mtk_i2c_clock_disable(struct mtk_i2c *i2c)
static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
{
u16 control_reg;
+ u16 ext_conf_val;
if (i2c->dev_comp->apdma_sync) {
writel(I2C_DMA_WARM_RST, i2c->pdmabase + OFFSET_RST);
@@ -518,8 +521,13 @@ static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
if (i2c->dev_comp->ltiming_adjust)
mtk_i2c_writew(i2c, i2c->ltiming_reg, OFFSET_LTIMING);
+ if (i2c->speed_hz <= I2C_MAX_STANDARD_MODE_FREQ)
+ ext_conf_val = I2C_ST_START_CON;
+ else
+ ext_conf_val = I2C_FS_START_CON;
+
if (i2c->dev_comp->timing_adjust) {
- mtk_i2c_writew(i2c, i2c->ac_timing.ext, OFFSET_EXT_CONF);
+ ext_conf_val = i2c->ac_timing.ext;
mtk_i2c_writew(i2c, i2c->ac_timing.inter_clk_div,
OFFSET_CLOCK_DIV);
mtk_i2c_writew(i2c, I2C_SCL_MIS_COMP_VALUE,
@@ -544,6 +552,7 @@ static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
OFFSET_HS_STA_STO_AC_TIMING);
}
}
+ mtk_i2c_writew(i2c, ext_conf_val, OFFSET_EXT_CONF);
/* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */
if (i2c->have_pmic)
--
2.18.0
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next prev parent reply other threads:[~2021-07-17 10:30 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-17 10:17 [PATCH V4 0/8] Introduce an attribute to choose timing setting Kewei Xu
2021-07-17 10:17 ` [PATCH v4 1/8] i2c: mediatek: fixing the incorrect register offset Kewei Xu
2021-07-17 10:17 ` [PATCH v4 2/8] dt-bindings: i2c: update bindings for MT8195 SoC Kewei Xu
2021-07-17 10:17 ` [PATCH v4 3/8] i2c: mediatek: Reset the handshake signal between i2c and dma Kewei Xu
2021-08-11 8:41 ` Chen-Yu Tsai
2021-08-21 7:40 ` Kewei Xu
2021-07-17 10:17 ` [PATCH v4 4/8] i2c: mediatek: Dump i2c/dma register when a timeout occurs Kewei Xu
2021-07-17 10:17 ` [PATCH v4 5/8] dt-bindings: i2c: add attribute default-timing-adjust Kewei Xu
2021-07-22 3:10 ` Rob Herring
2021-08-18 6:37 ` Kewei Xu
2021-07-17 10:17 ` Kewei Xu [this message]
2021-07-17 10:17 ` [PATCH v4 7/8] i2c: mediatek: Isolate speed setting via dts for special devices Kewei Xu
2021-07-17 10:17 ` [PATCH v4 8/8] i2c: mediatek: modify bus speed calculation formula Kewei Xu
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