From: Richard Zhu <hongxing.zhu@nxp.com>
To: l.stach@pengutronix.de, bhelgaas@google.com, lorenzo.pieralisi@arm.com
Cc: linux-pci@vger.kernel.org, linux-imx@nxp.com,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, kernel@pengutronix.de,
Richard Zhu <hongxing.zhu@nxp.com>
Subject: [RESEND v2 1/5] PCI: imx6: Encapsulate the clock enable into one standalone function
Date: Fri, 15 Oct 2021 14:05:37 +0800 [thread overview]
Message-ID: <1634277941-6672-2-git-send-email-hongxing.zhu@nxp.com> (raw)
In-Reply-To: <1634277941-6672-1-git-send-email-hongxing.zhu@nxp.com>
No function changes, just encapsulate the i.MX PCIe clocks enable
operations into one standalone function
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
drivers/pci/controller/dwc/pci-imx6.c | 79 ++++++++++++++++-----------
1 file changed, 48 insertions(+), 31 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 26f49f797b0f..1fa1dba6da81 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -470,38 +470,16 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
return ret;
}
-static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie)
-{
- u32 val;
- struct device *dev = imx6_pcie->pci->dev;
-
- if (regmap_read_poll_timeout(imx6_pcie->iomuxc_gpr,
- IOMUXC_GPR22, val,
- val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED,
- PHY_PLL_LOCK_WAIT_USLEEP_MAX,
- PHY_PLL_LOCK_WAIT_TIMEOUT))
- dev_err(dev, "PCIe PLL lock timeout\n");
-}
-
-static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
+static int imx6_pcie_clk_enable(struct imx6_pcie *imx6_pcie)
{
struct dw_pcie *pci = imx6_pcie->pci;
struct device *dev = pci->dev;
int ret;
- if (imx6_pcie->vpcie && !regulator_is_enabled(imx6_pcie->vpcie)) {
- ret = regulator_enable(imx6_pcie->vpcie);
- if (ret) {
- dev_err(dev, "failed to enable vpcie regulator: %d\n",
- ret);
- return;
- }
- }
-
ret = clk_prepare_enable(imx6_pcie->pcie_phy);
if (ret) {
dev_err(dev, "unable to enable pcie_phy clock\n");
- goto err_pcie_phy;
+ return ret;
}
ret = clk_prepare_enable(imx6_pcie->pcie_bus);
@@ -524,6 +502,51 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
/* allow the clocks to stabilize */
usleep_range(200, 500);
+ return 0;
+
+err_ref_clk:
+ clk_disable_unprepare(imx6_pcie->pcie);
+err_pcie:
+ clk_disable_unprepare(imx6_pcie->pcie_bus);
+err_pcie_bus:
+ clk_disable_unprepare(imx6_pcie->pcie_phy);
+
+ return ret;
+}
+
+static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie)
+{
+ u32 val;
+ struct device *dev = imx6_pcie->pci->dev;
+
+ if (regmap_read_poll_timeout(imx6_pcie->iomuxc_gpr,
+ IOMUXC_GPR22, val,
+ val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED,
+ PHY_PLL_LOCK_WAIT_USLEEP_MAX,
+ PHY_PLL_LOCK_WAIT_TIMEOUT))
+ dev_err(dev, "PCIe PLL lock timeout\n");
+}
+
+static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
+{
+ struct dw_pcie *pci = imx6_pcie->pci;
+ struct device *dev = pci->dev;
+ int ret;
+
+ if (imx6_pcie->vpcie && !regulator_is_enabled(imx6_pcie->vpcie)) {
+ ret = regulator_enable(imx6_pcie->vpcie);
+ if (ret) {
+ dev_err(dev, "failed to enable vpcie regulator: %d\n",
+ ret);
+ return;
+ }
+ }
+
+ ret = imx6_pcie_clk_enable(imx6_pcie);
+ if (ret) {
+ dev_err(dev, "unable to enable pcie clocks\n");
+ goto err_clks;
+ }
/* Some boards don't have PCIe reset GPIO. */
if (gpio_is_valid(imx6_pcie->reset_gpio)) {
@@ -578,13 +601,7 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
return;
-err_ref_clk:
- clk_disable_unprepare(imx6_pcie->pcie);
-err_pcie:
- clk_disable_unprepare(imx6_pcie->pcie_bus);
-err_pcie_bus:
- clk_disable_unprepare(imx6_pcie->pcie_phy);
-err_pcie_phy:
+err_clks:
if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) {
ret = regulator_disable(imx6_pcie->vpcie);
if (ret)
--
2.25.1
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next prev parent reply other threads:[~2021-10-15 6:32 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-15 6:05 [RESEND v2 0/5] PCI: imx6: refine codes and add compliance tests mode support Richard Zhu
2021-10-15 6:05 ` Richard Zhu [this message]
2021-10-15 18:13 ` [RESEND v2 1/5] PCI: imx6: Encapsulate the clock enable into one standalone function Lucas Stach
2021-10-19 7:32 ` Richard Zhu
2021-10-15 6:05 ` [RESEND v2 2/5] PCI: imx6: Add the error propagation from host_init Richard Zhu
2021-10-15 18:16 ` Lucas Stach
2021-10-19 7:33 ` Richard Zhu
2021-10-15 6:05 ` [RESEND v2 3/5] PCI: imx6: Fix the regulator dump when link never came up Richard Zhu
2021-10-15 18:22 ` Lucas Stach
2021-10-19 7:39 ` Richard Zhu
2021-10-20 3:22 ` Richard Zhu
2021-10-15 18:34 ` Fabio Estevam
2021-10-19 7:44 ` Richard Zhu
2021-10-15 6:05 ` [RESEND v2 4/5] PCI: imx6: Fix the clock reference handling unbalance " Richard Zhu
2021-10-15 18:24 ` Lucas Stach
2021-10-19 7:43 ` Richard Zhu
2021-10-15 18:49 ` Bjorn Helgaas
2021-10-15 18:51 ` Bjorn Helgaas
2021-10-19 7:56 ` Richard Zhu
2021-10-22 8:02 ` Richard Zhu
2021-10-23 9:53 ` Krzysztof Wilczyński
2021-10-25 2:35 ` Richard Zhu
2021-10-26 22:21 ` Bjorn Helgaas
2021-10-27 1:30 ` Richard Zhu
2021-10-26 16:38 ` Bjorn Helgaas
2021-10-27 1:29 ` Richard Zhu
2021-10-19 7:45 ` Richard Zhu
2021-10-15 6:05 ` [RESEND v2 5/5] PCI: imx6: Add the compliance tests mode support Richard Zhu
2021-10-15 18:28 ` Lucas Stach
2021-10-19 8:12 ` Richard Zhu
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