From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E53CFC433F5 for ; Wed, 9 Mar 2022 12:07:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:From:Cc:To :Subject:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=Fcr57NkXrY/bj68M8mnZpLKjRg6CY+JpPgFYnVfOgSg=; b=VtyQQOr1MJr7VQ agcv60ud4bQ8aLbpZgjjJYAZ95g6zjMhGVNY9tneA3iMkUfNTdYz7t2e37AG2TR4tE5nuZ6fZjsYq dO5EgoC8v/htm5wWpMHFxxGDOsx81p0Qd7PbD3FsYnRLblkolw1AR1Ae2b7gnSOGCU9ssVbHpMiJZ cyFZQ0Z9/kKsh1Rv1EEwn0o1Fe2h0zXmEBhZT/93vtuebijEc0clHnhseAjQy7a5H4fW03uU10ecc oyB/ipUcMgo0ytZIMswJKPAB5bDasm959yf2wUc6vZts0B+m8tZRMnPFVgIPWWmaGn0IR0l7F+gsd QBendkkeQSWKHU7jDM5g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nRv4s-008TH2-6r; Wed, 09 Mar 2022 12:06:02 +0000 Received: from ams.source.kernel.org ([2604:1380:4601:e00::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nRv4n-008TFb-OA for linux-arm-kernel@lists.infradead.org; Wed, 09 Mar 2022 12:06:00 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 5A987B81FE8; Wed, 9 Mar 2022 12:05:56 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C34C5C340E8; Wed, 9 Mar 2022 12:05:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1646827555; bh=BNQbMelhQHwTKSONJ8DBtY0ztBIxPPza+wArFkSEOtc=; h=Subject:To:Cc:From:Date:From; b=STS1omxyT9uenFl2mnOrw6Y53VevlHIlpR5boyMNKfhAcxQzsosXvXuIURqK3tmxU AYeKrb4fmnCdrgGeIFNZbCZXiIYPxczcGJre8vy2MAfMsYXQBF0TCNrTf0Hlsywal8 EHz2n9GF85Ve/Vg44ZXIVcca4dq17OUyeWZmkfx8= Subject: Patch "arm64: Add Cortex-X2 CPU part definition" has been added to the 5.4-stable tree To: anshuman.khandual@arm.com, catalin.marinas@arm.com, gregkh@linuxfoundation.org, james.morse@arm.com, linux-arm-kernel@lists.infradead.org, suzuki.poulose@arm.com, will@kernel.org Cc: From: Date: Wed, 09 Mar 2022 13:05:52 +0100 Message-ID: <1646827552138209@kroah.com> MIME-Version: 1.0 X-stable: commit X-Patchwork-Hint: ignore X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220309_040557_976827_A4E8721E X-CRM114-Status: GOOD ( 13.96 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This is a note to let you know that I've just added the patch titled arm64: Add Cortex-X2 CPU part definition to the 5.4-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary The filename of the patch is: arm64-add-cortex-x2-cpu-part-definition.patch and it can be found in the queue-5.4 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let know about it. >From foo@baz Wed Mar 9 01:00:43 PM CET 2022 From: Anshuman Khandual Date: Mon, 24 Jan 2022 08:45:37 +0530 Subject: arm64: Add Cortex-X2 CPU part definition From: Anshuman Khandual commit 72bb9dcb6c33cfac80282713c2b4f2b254cd24d1 upstream. Add the CPU Partnumbers for the new Arm designs. Cc: Will Deacon Cc: Suzuki Poulose Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual Reviewed-by: Suzuki K Poulose Link: https://lore.kernel.org/r/1642994138-25887-2-git-send-email-anshuman.khandual@arm.com Signed-off-by: Catalin Marinas Signed-off-by: James Morse Signed-off-by: Greg Kroah-Hartman --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -73,6 +73,7 @@ #define ARM_CPU_PART_NEOVERSE_N1 0xD0C #define ARM_CPU_PART_CORTEX_A77 0xD0D #define ARM_CPU_PART_CORTEX_A710 0xD47 +#define ARM_CPU_PART_CORTEX_X2 0xD48 #define ARM_CPU_PART_NEOVERSE_N2 0xD49 #define APM_CPU_PART_POTENZA 0x000 @@ -107,6 +108,7 @@ #define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1) #define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77) #define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710) +#define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2) #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) Patches currently in stable-queue which might be from anshuman.khandual@arm.com are queue-5.4/arm64-add-neoverse-n2-cortex-a710-cpu-part-definition.patch queue-5.4/arm64-add-cortex-x2-cpu-part-definition.patch _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel