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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id v4-20020a4a9744000000b00448a3ecdc9dsm2062708ooi.22.2022.10.03.06.24.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Oct 2022 06:24:48 -0700 (PDT) Received: (nullmailer pid 1863792 invoked by uid 1000); Mon, 03 Oct 2022 13:24:47 -0000 From: Rob Herring To: Serge Semin Cc: Dinh Nguyen , Michail Ivanov , James Morse , Michal Simek , Tony Luck , Punnaiah Choudary Kalluri , linux-edac@vger.kernel.org, Borislav Petkov , Serge Semin , Robert Richter , Alexey Malahov , linux-arm-kernel@lists.infradead.org, Pavel Parkhomenko , linux-kernel@vger.kernel.org, Mauro Carvalho Chehab , Manish Narani , Krzysztof Kozlowski , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org In-Reply-To: <20220929234121.13955-3-Sergey.Semin@baikalelectronics.ru> References: <20220929234121.13955-1-Sergey.Semin@baikalelectronics.ru> <20220929234121.13955-3-Sergey.Semin@baikalelectronics.ru> Message-Id: <166479586876.1658787.6925988592765037866.robh@kernel.org> Subject: Re: [PATCH v3 02/13] dt-bindings: memory: Add Baikal-T1 DDRC DT-schema Date: Mon, 03 Oct 2022 08:24:47 -0500 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221003_062451_243079_947D14D6 X-CRM114-Status: GOOD ( 16.60 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, 30 Sep 2022 02:41:10 +0300, Serge Semin wrote: > Baikal-T1 DDR controller is based on the DW uMCTL2 DDRC IP-core v2.51a > with up to DDR3 protocol capability and 32-bit data bus + 8-bit ECC. There > are individual IRQs for each ECC and DFI events. The dedicated scrubber > clock source is absent since it's fully synchronous to the core clock. > In addition to that the DFI-DDR PHY CSRs can be accessed via a separate > registers space. > > Signed-off-by: Serge Semin > Reviewed-by: Rob Herring > > --- > > Changelog v2: > - Keep the alphabetically ordered compatible strings list. (@Krzysztof) > - Fix grammar nitpicks in the patch log. (@Krzysztof) > - Drop the PHY CSR region. (@Rob) > - Move the device bindings to the separate DT-schema. > --- > .../memory-controllers/baikal,bt1-ddrc.yaml | 91 +++++++++++++++++++ > 1 file changed, 91 insertions(+) > create mode 100644 Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: ./Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml: Unable to find schema file matching $id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-common.yaml Error: Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.example.dts:41.30-31 syntax error FATAL ERROR: Unable to parse input tree make[1]: *** [scripts/Makefile.lib:384: Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.example.dtb] Error 1 make[1]: *** Waiting for unfinished jobs.... make: *** [Makefile:1420: dt_binding_check] Error 2 doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/ This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel