From: Maxime Ripard <maxime@cerno.tech>
To: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>,
Eric Anholt <eric@anholt.net>
Cc: Stefan Wahren <stefan.wahren@i2se.com>,
Tim Gover <tim.gover@raspberrypi.com>,
Dave Stevenson <dave.stevenson@raspberrypi.com>,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
Hoegeun Kwon <hoegeun.kwon@samsung.com>,
Chanwoo Choi <cw00.choi@samsung.com>,
bcm-kernel-feedback-list@broadcom.com,
linux-rpi-kernel@lists.infradead.org,
Phil Elwell <phil@raspberrypi.com>,
linux-arm-kernel@lists.infradead.org,
Maxime Ripard <maxime@cerno.tech>
Subject: [PATCH v5 02/80] drm/vc4: Add support for the BCM2711 HVS5
Date: Thu, 3 Sep 2020 10:00:34 +0200 [thread overview]
Message-ID: <1d02fab3b916d639c2dc05608c117bbd8230ebe8.1599120059.git-series.maxime@cerno.tech> (raw)
In-Reply-To: <cover.dddc064d8bb83e46744336af67dcb13139e5747d.1599120059.git-series.maxime@cerno.tech>
From: Dave Stevenson <dave.stevenson@raspberrypi.com>
The HVS found in the BCM2711 is slightly different from the previous
generations.
Most notably, the display list layout changes a bit, the LBM doesn't have
the same size and the formats ordering for some formats is swapped.
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Tested-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
---
drivers/gpu/drm/vc4/vc4_drv.h | 4 +-
drivers/gpu/drm/vc4/vc4_hvs.c | 34 ++++--
drivers/gpu/drm/vc4/vc4_plane.c | 194 ++++++++++++++++++++++++---------
drivers/gpu/drm/vc4/vc4_regs.h | 67 +++++++++++-
4 files changed, 240 insertions(+), 59 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index fa19160c801f..e4cde1f9224b 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -329,7 +329,11 @@ struct vc4_hvs {
spinlock_t mm_lock;
struct drm_mm_node mitchell_netravali_filter;
+
struct debugfs_regset32 regset;
+
+ /* HVS version 5 flag, therefore requires updated dlist structures */
+ bool hvs5;
};
struct vc4_plane {
diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c
index 2d2bf59c0503..836d8799d79e 100644
--- a/drivers/gpu/drm/vc4/vc4_hvs.c
+++ b/drivers/gpu/drm/vc4/vc4_hvs.c
@@ -277,11 +277,19 @@ void vc4_hvs_atomic_enable(struct drm_crtc *crtc,
* mode.
*/
dispctrl = SCALER_DISPCTRLX_ENABLE;
- dispctrl |= VC4_SET_FIELD(mode->hdisplay,
- SCALER_DISPCTRLX_WIDTH) |
- VC4_SET_FIELD(mode->vdisplay,
- SCALER_DISPCTRLX_HEIGHT) |
- (oneshot ? SCALER_DISPCTRLX_ONESHOT : 0);
+
+ if (!vc4->hvs->hvs5)
+ dispctrl |= VC4_SET_FIELD(mode->hdisplay,
+ SCALER_DISPCTRLX_WIDTH) |
+ VC4_SET_FIELD(mode->vdisplay,
+ SCALER_DISPCTRLX_HEIGHT) |
+ (oneshot ? SCALER_DISPCTRLX_ONESHOT : 0);
+ else
+ dispctrl |= VC4_SET_FIELD(mode->hdisplay,
+ SCALER5_DISPCTRLX_WIDTH) |
+ VC4_SET_FIELD(mode->vdisplay,
+ SCALER5_DISPCTRLX_HEIGHT) |
+ (oneshot ? SCALER5_DISPCTRLX_ONESHOT : 0);
HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel), dispctrl);
}
@@ -521,6 +529,9 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
hvs->pdev = pdev;
+ if (of_device_is_compatible(pdev->dev.of_node, "brcm,bcm2711-hvs"))
+ hvs->hvs5 = true;
+
hvs->regs = vc4_ioremap_regs(pdev, 0);
if (IS_ERR(hvs->regs))
return PTR_ERR(hvs->regs);
@@ -529,7 +540,10 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
hvs->regset.regs = hvs_regs;
hvs->regset.nregs = ARRAY_SIZE(hvs_regs);
- hvs->dlist = hvs->regs + SCALER_DLIST_START;
+ if (!hvs->hvs5)
+ hvs->dlist = hvs->regs + SCALER_DLIST_START;
+ else
+ hvs->dlist = hvs->regs + SCALER5_DLIST_START;
spin_lock_init(&hvs->mm_lock);
@@ -547,7 +561,12 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
* between planes when they don't overlap on the screen, but
* for now we just allocate globally.
*/
- drm_mm_init(&hvs->lbm_mm, 0, 96 * 1024);
+ if (!hvs->hvs5)
+ /* 96kB */
+ drm_mm_init(&hvs->lbm_mm, 0, 96 * 1024);
+ else
+ /* 70k words */
+ drm_mm_init(&hvs->lbm_mm, 0, 70 * 2 * 1024);
/* Upload filter kernels. We only have the one for now, so we
* keep it around for the lifetime of the driver.
@@ -632,6 +651,7 @@ static int vc4_hvs_dev_remove(struct platform_device *pdev)
}
static const struct of_device_id vc4_hvs_dt_match[] = {
+ { .compatible = "brcm,bcm2711-hvs" },
{ .compatible = "brcm,bcm2835-hvs" },
{}
};
diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c
index d040d9f12c6d..20c949b57827 100644
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
@@ -32,45 +32,60 @@ static const struct hvs_format {
u32 drm; /* DRM_FORMAT_* */
u32 hvs; /* HVS_FORMAT_* */
u32 pixel_order;
+ u32 pixel_order_hvs5;
} hvs_formats[] = {
{
- .drm = DRM_FORMAT_XRGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
+ .drm = DRM_FORMAT_XRGB8888,
+ .hvs = HVS_PIXEL_FORMAT_RGBA8888,
.pixel_order = HVS_PIXEL_ORDER_ABGR,
+ .pixel_order_hvs5 = HVS_PIXEL_ORDER_ARGB,
},
{
- .drm = DRM_FORMAT_ARGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
+ .drm = DRM_FORMAT_ARGB8888,
+ .hvs = HVS_PIXEL_FORMAT_RGBA8888,
.pixel_order = HVS_PIXEL_ORDER_ABGR,
+ .pixel_order_hvs5 = HVS_PIXEL_ORDER_ARGB,
},
{
- .drm = DRM_FORMAT_ABGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
+ .drm = DRM_FORMAT_ABGR8888,
+ .hvs = HVS_PIXEL_FORMAT_RGBA8888,
.pixel_order = HVS_PIXEL_ORDER_ARGB,
+ .pixel_order_hvs5 = HVS_PIXEL_ORDER_ABGR,
},
{
- .drm = DRM_FORMAT_XBGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
+ .drm = DRM_FORMAT_XBGR8888,
+ .hvs = HVS_PIXEL_FORMAT_RGBA8888,
.pixel_order = HVS_PIXEL_ORDER_ARGB,
+ .pixel_order_hvs5 = HVS_PIXEL_ORDER_ABGR,
},
{
- .drm = DRM_FORMAT_RGB565, .hvs = HVS_PIXEL_FORMAT_RGB565,
+ .drm = DRM_FORMAT_RGB565,
+ .hvs = HVS_PIXEL_FORMAT_RGB565,
.pixel_order = HVS_PIXEL_ORDER_XRGB,
},
{
- .drm = DRM_FORMAT_BGR565, .hvs = HVS_PIXEL_FORMAT_RGB565,
+ .drm = DRM_FORMAT_BGR565,
+ .hvs = HVS_PIXEL_FORMAT_RGB565,
.pixel_order = HVS_PIXEL_ORDER_XBGR,
},
{
- .drm = DRM_FORMAT_ARGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551,
+ .drm = DRM_FORMAT_ARGB1555,
+ .hvs = HVS_PIXEL_FORMAT_RGBA5551,
.pixel_order = HVS_PIXEL_ORDER_ABGR,
},
{
- .drm = DRM_FORMAT_XRGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551,
+ .drm = DRM_FORMAT_XRGB1555,
+ .hvs = HVS_PIXEL_FORMAT_RGBA5551,
.pixel_order = HVS_PIXEL_ORDER_ABGR,
},
{
- .drm = DRM_FORMAT_RGB888, .hvs = HVS_PIXEL_FORMAT_RGB888,
+ .drm = DRM_FORMAT_RGB888,
+ .hvs = HVS_PIXEL_FORMAT_RGB888,
.pixel_order = HVS_PIXEL_ORDER_XRGB,
},
{
- .drm = DRM_FORMAT_BGR888, .hvs = HVS_PIXEL_FORMAT_RGB888,
+ .drm = DRM_FORMAT_BGR888,
+ .hvs = HVS_PIXEL_FORMAT_RGB888,
.pixel_order = HVS_PIXEL_ORDER_XBGR,
},
{
@@ -776,35 +791,6 @@ static int vc4_plane_mode_set(struct drm_plane *plane,
return -EINVAL;
}
- /* Control word */
- vc4_dlist_write(vc4_state,
- SCALER_CTL0_VALID |
- (rotation & DRM_MODE_REFLECT_X ? SCALER_CTL0_HFLIP : 0) |
- (rotation & DRM_MODE_REFLECT_Y ? SCALER_CTL0_VFLIP : 0) |
- VC4_SET_FIELD(SCALER_CTL0_RGBA_EXPAND_ROUND, SCALER_CTL0_RGBA_EXPAND) |
- (format->pixel_order << SCALER_CTL0_ORDER_SHIFT) |
- (hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
- VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
- (vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) |
- VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
- VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1));
-
- /* Position Word 0: Image Positions and Alpha Value */
- vc4_state->pos0_offset = vc4_state->dlist_count;
- vc4_dlist_write(vc4_state,
- VC4_SET_FIELD(state->alpha >> 8, SCALER_POS0_FIXED_ALPHA) |
- VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) |
- VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y));
-
- /* Position Word 1: Scaled Image Dimensions. */
- if (!vc4_state->is_unity) {
- vc4_dlist_write(vc4_state,
- VC4_SET_FIELD(vc4_state->crtc_w,
- SCALER_POS1_SCL_WIDTH) |
- VC4_SET_FIELD(vc4_state->crtc_h,
- SCALER_POS1_SCL_HEIGHT));
- }
-
/* Don't waste cycles mixing with plane alpha if the set alpha
* is opaque or there is no per-pixel alpha information.
* In any case we use the alpha property value as the fixed alpha.
@@ -812,20 +798,120 @@ static int vc4_plane_mode_set(struct drm_plane *plane,
mix_plane_alpha = state->alpha != DRM_BLEND_ALPHA_OPAQUE &&
fb->format->has_alpha;
- /* Position Word 2: Source Image Size, Alpha */
- vc4_state->pos2_offset = vc4_state->dlist_count;
- vc4_dlist_write(vc4_state,
- VC4_SET_FIELD(fb->format->has_alpha ?
- SCALER_POS2_ALPHA_MODE_PIPELINE :
- SCALER_POS2_ALPHA_MODE_FIXED,
- SCALER_POS2_ALPHA_MODE) |
- (mix_plane_alpha ? SCALER_POS2_ALPHA_MIX : 0) |
- (fb->format->has_alpha ? SCALER_POS2_ALPHA_PREMULT : 0) |
- VC4_SET_FIELD(vc4_state->src_w[0], SCALER_POS2_WIDTH) |
- VC4_SET_FIELD(vc4_state->src_h[0], SCALER_POS2_HEIGHT));
+ if (!vc4->hvs->hvs5) {
+ /* Control word */
+ vc4_dlist_write(vc4_state,
+ SCALER_CTL0_VALID |
+ (rotation & DRM_MODE_REFLECT_X ? SCALER_CTL0_HFLIP : 0) |
+ (rotation & DRM_MODE_REFLECT_Y ? SCALER_CTL0_VFLIP : 0) |
+ VC4_SET_FIELD(SCALER_CTL0_RGBA_EXPAND_ROUND, SCALER_CTL0_RGBA_EXPAND) |
+ (format->pixel_order << SCALER_CTL0_ORDER_SHIFT) |
+ (hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
+ VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
+ (vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) |
+ VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
+ VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1));
+
+ /* Position Word 0: Image Positions and Alpha Value */
+ vc4_state->pos0_offset = vc4_state->dlist_count;
+ vc4_dlist_write(vc4_state,
+ VC4_SET_FIELD(state->alpha >> 8, SCALER_POS0_FIXED_ALPHA) |
+ VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) |
+ VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y));
+
+ /* Position Word 1: Scaled Image Dimensions. */
+ if (!vc4_state->is_unity) {
+ vc4_dlist_write(vc4_state,
+ VC4_SET_FIELD(vc4_state->crtc_w,
+ SCALER_POS1_SCL_WIDTH) |
+ VC4_SET_FIELD(vc4_state->crtc_h,
+ SCALER_POS1_SCL_HEIGHT));
+ }
+
+ /* Position Word 2: Source Image Size, Alpha */
+ vc4_state->pos2_offset = vc4_state->dlist_count;
+ vc4_dlist_write(vc4_state,
+ VC4_SET_FIELD(fb->format->has_alpha ?
+ SCALER_POS2_ALPHA_MODE_PIPELINE :
+ SCALER_POS2_ALPHA_MODE_FIXED,
+ SCALER_POS2_ALPHA_MODE) |
+ (mix_plane_alpha ? SCALER_POS2_ALPHA_MIX : 0) |
+ (fb->format->has_alpha ?
+ SCALER_POS2_ALPHA_PREMULT : 0) |
+ VC4_SET_FIELD(vc4_state->src_w[0],
+ SCALER_POS2_WIDTH) |
+ VC4_SET_FIELD(vc4_state->src_h[0],
+ SCALER_POS2_HEIGHT));
+
+ /* Position Word 3: Context. Written by the HVS. */
+ vc4_dlist_write(vc4_state, 0xc0c0c0c0);
+
+ } else {
+ u32 hvs_pixel_order = format->pixel_order;
- /* Position Word 3: Context. Written by the HVS. */
- vc4_dlist_write(vc4_state, 0xc0c0c0c0);
+ if (format->pixel_order_hvs5)
+ hvs_pixel_order = format->pixel_order_hvs5;
+
+ /* Control word */
+ vc4_dlist_write(vc4_state,
+ SCALER_CTL0_VALID |
+ (hvs_pixel_order << SCALER_CTL0_ORDER_SHIFT) |
+ (hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
+ VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
+ (vc4_state->is_unity ?
+ SCALER5_CTL0_UNITY : 0) |
+ VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
+ VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1) |
+ SCALER5_CTL0_ALPHA_EXPAND |
+ SCALER5_CTL0_RGB_EXPAND);
+
+ /* Position Word 0: Image Positions and Alpha Value */
+ vc4_state->pos0_offset = vc4_state->dlist_count;
+ vc4_dlist_write(vc4_state,
+ (rotation & DRM_MODE_REFLECT_Y ?
+ SCALER5_POS0_VFLIP : 0) |
+ VC4_SET_FIELD(vc4_state->crtc_x,
+ SCALER_POS0_START_X) |
+ (rotation & DRM_MODE_REFLECT_X ?
+ SCALER5_POS0_HFLIP : 0) |
+ VC4_SET_FIELD(vc4_state->crtc_y,
+ SCALER5_POS0_START_Y)
+ );
+
+ /* Control Word 2 */
+ vc4_dlist_write(vc4_state,
+ VC4_SET_FIELD(state->alpha >> 4,
+ SCALER5_CTL2_ALPHA) |
+ fb->format->has_alpha ?
+ SCALER5_CTL2_ALPHA_PREMULT : 0 |
+ (mix_plane_alpha ?
+ SCALER5_CTL2_ALPHA_MIX : 0) |
+ VC4_SET_FIELD(fb->format->has_alpha ?
+ SCALER5_CTL2_ALPHA_MODE_PIPELINE :
+ SCALER5_CTL2_ALPHA_MODE_FIXED,
+ SCALER5_CTL2_ALPHA_MODE)
+ );
+
+ /* Position Word 1: Scaled Image Dimensions. */
+ if (!vc4_state->is_unity) {
+ vc4_dlist_write(vc4_state,
+ VC4_SET_FIELD(vc4_state->crtc_w,
+ SCALER_POS1_SCL_WIDTH) |
+ VC4_SET_FIELD(vc4_state->crtc_h,
+ SCALER_POS1_SCL_HEIGHT));
+ }
+
+ /* Position Word 2: Source Image Size */
+ vc4_state->pos2_offset = vc4_state->dlist_count;
+ vc4_dlist_write(vc4_state,
+ VC4_SET_FIELD(vc4_state->src_w[0],
+ SCALER5_POS2_WIDTH) |
+ VC4_SET_FIELD(vc4_state->src_h[0],
+ SCALER5_POS2_HEIGHT));
+
+ /* Position Word 3: Context. Written by the HVS. */
+ vc4_dlist_write(vc4_state, 0xc0c0c0c0);
+ }
/* Pointer Word 0/1/2: RGB / Y / Cb / Cr Pointers
@@ -1203,6 +1289,10 @@ static bool vc4_format_mod_supported(struct drm_plane *plane,
default:
return false;
}
+ case DRM_FORMAT_RGBX1010102:
+ case DRM_FORMAT_BGRX1010102:
+ case DRM_FORMAT_RGBA1010102:
+ case DRM_FORMAT_BGRA1010102:
case DRM_FORMAT_YUV422:
case DRM_FORMAT_YVU422:
case DRM_FORMAT_YUV420:
diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h
index 324462cc9cd4..91b785725555 100644
--- a/drivers/gpu/drm/vc4/vc4_regs.h
+++ b/drivers/gpu/drm/vc4/vc4_regs.h
@@ -327,6 +327,20 @@
# define SCALER_DISPCTRLX_HEIGHT_MASK VC4_MASK(11, 0)
# define SCALER_DISPCTRLX_HEIGHT_SHIFT 0
+# define SCALER5_DISPCTRLX_WIDTH_MASK VC4_MASK(28, 16)
+# define SCALER5_DISPCTRLX_WIDTH_SHIFT 16
+/* Generates a single frame when VSTART is seen and stops at the last
+ * pixel read from the FIFO.
+ */
+# define SCALER5_DISPCTRLX_ONESHOT BIT(15)
+/* Processes a single context in the dlist and then task switch,
+ * instead of an entire line.
+ */
+# define SCALER5_DISPCTRLX_ONECTX_MASK VC4_MASK(14, 13)
+# define SCALER5_DISPCTRLX_ONECTX_SHIFT 13
+# define SCALER5_DISPCTRLX_HEIGHT_MASK VC4_MASK(12, 0)
+# define SCALER5_DISPCTRLX_HEIGHT_SHIFT 0
+
#define SCALER_DISPBKGND0 0x00000044
# define SCALER_DISPBKGND_AUTOHS BIT(31)
# define SCALER_DISPBKGND_INTERLACE BIT(30)
@@ -460,6 +474,8 @@
#define SCALER_DLIST_START 0x00002000
#define SCALER_DLIST_SIZE 0x00004000
+#define SCALER5_DLIST_START 0x00004000
+
#define VC4_HDMI_CORE_REV 0x000
#define VC4_HDMI_SW_RESET_CONTROL 0x004
@@ -825,6 +841,8 @@ enum hvs_pixel_format {
HVS_PIXEL_FORMAT_PALETTE = 13,
HVS_PIXEL_FORMAT_YUV444_RGB = 14,
HVS_PIXEL_FORMAT_AYUV444_RGB = 15,
+ HVS_PIXEL_FORMAT_RGBA1010102 = 16,
+ HVS_PIXEL_FORMAT_YCBCR_10BIT = 17,
};
/* Note: the LSB is the rightmost character shown. Only valid for
@@ -879,6 +897,10 @@ enum hvs_pixel_format {
#define SCALER_CTL0_RGBA_EXPAND_MSB 2
#define SCALER_CTL0_RGBA_EXPAND_ROUND 3
+#define SCALER5_CTL0_ALPHA_EXPAND BIT(12)
+
+#define SCALER5_CTL0_RGB_EXPAND BIT(11)
+
#define SCALER_CTL0_SCL1_MASK VC4_MASK(10, 8)
#define SCALER_CTL0_SCL1_SHIFT 8
@@ -896,10 +918,13 @@ enum hvs_pixel_format {
/* Set to indicate no scaling. */
#define SCALER_CTL0_UNITY BIT(4)
+#define SCALER5_CTL0_UNITY BIT(15)
#define SCALER_CTL0_PIXEL_FORMAT_MASK VC4_MASK(3, 0)
#define SCALER_CTL0_PIXEL_FORMAT_SHIFT 0
+#define SCALER5_CTL0_PIXEL_FORMAT_MASK VC4_MASK(4, 0)
+
#define SCALER_POS0_FIXED_ALPHA_MASK VC4_MASK(31, 24)
#define SCALER_POS0_FIXED_ALPHA_SHIFT 24
@@ -909,12 +934,48 @@ enum hvs_pixel_format {
#define SCALER_POS0_START_X_MASK VC4_MASK(11, 0)
#define SCALER_POS0_START_X_SHIFT 0
+#define SCALER5_POS0_START_Y_MASK VC4_MASK(27, 16)
+#define SCALER5_POS0_START_Y_SHIFT 16
+
+#define SCALER5_POS0_START_X_MASK VC4_MASK(13, 0)
+#define SCALER5_POS0_START_X_SHIFT 0
+
+#define SCALER5_POS0_VFLIP BIT(31)
+#define SCALER5_POS0_HFLIP BIT(15)
+
+#define SCALER5_CTL2_ALPHA_MODE_MASK VC4_MASK(31, 30)
+#define SCALER5_CTL2_ALPHA_MODE_SHIFT 30
+#define SCALER5_CTL2_ALPHA_MODE_PIPELINE 0
+#define SCALER5_CTL2_ALPHA_MODE_FIXED 1
+#define SCALER5_CTL2_ALPHA_MODE_FIXED_NONZERO 2
+#define SCALER5_CTL2_ALPHA_MODE_FIXED_OVER_0x07 3
+
+#define SCALER5_CTL2_ALPHA_PREMULT BIT(29)
+
+#define SCALER5_CTL2_ALPHA_MIX BIT(28)
+
+#define SCALER5_CTL2_ALPHA_LOC BIT(25)
+
+#define SCALER5_CTL2_MAP_SEL_MASK VC4_MASK(18, 17)
+#define SCALER5_CTL2_MAP_SEL_SHIFT 17
+
+#define SCALER5_CTL2_GAMMA BIT(16)
+
+#define SCALER5_CTL2_ALPHA_MASK VC4_MASK(15, 4)
+#define SCALER5_CTL2_ALPHA_SHIFT 4
+
#define SCALER_POS1_SCL_HEIGHT_MASK VC4_MASK(27, 16)
#define SCALER_POS1_SCL_HEIGHT_SHIFT 16
#define SCALER_POS1_SCL_WIDTH_MASK VC4_MASK(11, 0)
#define SCALER_POS1_SCL_WIDTH_SHIFT 0
+#define SCALER5_POS1_SCL_HEIGHT_MASK VC4_MASK(28, 16)
+#define SCALER5_POS1_SCL_HEIGHT_SHIFT 16
+
+#define SCALER5_POS1_SCL_WIDTH_MASK VC4_MASK(12, 0)
+#define SCALER5_POS1_SCL_WIDTH_SHIFT 0
+
#define SCALER_POS2_ALPHA_MODE_MASK VC4_MASK(31, 30)
#define SCALER_POS2_ALPHA_MODE_SHIFT 30
#define SCALER_POS2_ALPHA_MODE_PIPELINE 0
@@ -930,6 +991,12 @@ enum hvs_pixel_format {
#define SCALER_POS2_WIDTH_MASK VC4_MASK(11, 0)
#define SCALER_POS2_WIDTH_SHIFT 0
+#define SCALER5_POS2_HEIGHT_MASK VC4_MASK(28, 16)
+#define SCALER5_POS2_HEIGHT_SHIFT 16
+
+#define SCALER5_POS2_WIDTH_MASK VC4_MASK(12, 0)
+#define SCALER5_POS2_WIDTH_SHIFT 0
+
/* Color Space Conversion words. Some values are S2.8 signed
* integers, except that the 2 integer bits map as {0x0: 0, 0x1: 1,
* 0x2: 2, 0x3: -1}
--
git-series 0.9.1
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next prev parent reply other threads:[~2020-09-03 8:04 UTC|newest]
Thread overview: 114+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20200904071259epcas1p3de4209531c0bc5ed6ea9ef19827b6ed5@epcas1p3.samsung.com>
2020-09-03 8:00 ` [PATCH v5 00/80] drm/vc4: Support BCM2711 Display Pipeline Maxime Ripard
2020-09-03 8:00 ` [PATCH v5 01/80] dt-bindings: display: Add support for the BCM2711 HVS Maxime Ripard
2020-09-03 8:00 ` Maxime Ripard [this message]
2020-09-03 8:00 ` [PATCH v5 03/80] drm/vc4: hvs: Boost the core clock during modeset Maxime Ripard
2020-09-03 8:00 ` [PATCH v5 04/80] drm/vc4: plane: Change LBM alignment constraint on LBM Maxime Ripard
2020-09-03 8:00 ` [PATCH v5 05/80] drm/vc4: plane: Optimize the LBM allocation size Maxime Ripard
2020-09-03 8:00 ` [PATCH v5 06/80] drm/vc4: plane: Create more planes Maxime Ripard
2020-09-03 8:00 ` [PATCH v5 07/80] drm/vc4: crtc: Deal with different number of pixel per clock Maxime Ripard
2020-09-03 8:00 ` [PATCH v5 08/80] drm/vc4: crtc: Use a shared interrupt Maxime Ripard
2020-09-03 8:00 ` [PATCH v5 09/80] drm/vc4: crtc: Move the cob allocation outside of bind Maxime Ripard
2020-09-03 8:00 ` [PATCH v5 10/80] drm/vc4: crtc: Rename HVS channel to output Maxime Ripard
2020-09-03 8:00 ` [PATCH v5 11/80] drm/vc4: crtc: Use local chan variable Maxime Ripard
2020-09-03 8:00 ` [PATCH v5 12/80] drm/vc4: crtc: Enable and disable the PV in atomic_enable / disable Maxime Ripard
2020-09-03 8:00 ` [PATCH v5 13/80] drm/vc4: kms: Convert to for_each_new_crtc_state Maxime Ripard
2020-09-04 15:42 ` Dave Stevenson
2020-09-03 8:00 ` [PATCH v5 14/80] drm/vc4: crtc: Assign output to channel automatically Maxime Ripard
2020-09-03 8:00 ` [PATCH v5 15/80] drm/vc4: crtc: Add FIFO depth to vc4_crtc_data Maxime Ripard
2020-09-03 8:00 ` [PATCH v5 16/80] drm/vc4: crtc: Add function to compute FIFO level bits Maxime Ripard
2020-09-03 8:00 ` [PATCH v5 17/80] drm/vc4: crtc: Rename HDMI encoder type to HDMI0 Maxime Ripard
2020-09-03 8:00 ` [PATCH v5 18/80] drm/vc4: crtc: Add HDMI1 encoder type Maxime Ripard
2020-09-03 8:00 ` [PATCH v5 19/80] drm/vc4: crtc: Disable color management for HVS5 Maxime Ripard
2020-09-03 8:00 ` [PATCH v5 20/80] drm/vc4: crtc: Turn pixelvalve reset into a function Maxime Ripard
2020-09-03 8:00 ` [PATCH v5 21/80] drm/vc4: crtc: Move PV dump to config_pv Maxime Ripard
2020-09-03 8:00 ` [PATCH v5 22/80] drm/vc4: crtc: Move HVS init and close to a function Maxime Ripard
2020-09-03 8:00 ` [PATCH v5 23/80] drm/vc4: crtc: Move the HVS gamma LUT setup to our init function Maxime Ripard
2020-09-03 8:00 ` [PATCH v5 24/80] drm/vc4: hvs: Make sure our channel is reset Maxime Ripard
2020-09-03 8:00 ` [PATCH v5 25/80] drm/vc4: crtc: Remove mode_set_nofb Maxime Ripard
2020-09-03 8:00 ` [PATCH v5 26/80] drm/vc4: crtc: Remove redundant pixelvalve reset Maxime Ripard
2020-09-03 8:00 ` [PATCH v5 27/80] drm/vc4: crtc: Move HVS channel init before the PV initialisation Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 28/80] drm/vc4: encoder: Add finer-grained encoder callbacks Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 29/80] drm/vc4: crtc: Add a delay after disabling the PixelValve output Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 30/80] drm/vc4: crtc: Clear the PixelValve FIFO on disable Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 31/80] drm/vc4: crtc: Clear the PixelValve FIFO during configuration Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 32/80] drm/vc4: hvs: Make the stop_channel function public Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 33/80] drm/vc4: hvs: Introduce a function to get the assigned FIFO Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 34/80] drm/vc4: crtc: Move the CRTC disable out Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 35/80] drm/vc4: drv: Disable the CRTC at boot time Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 36/80] dt-bindings: display: vc4: pv: Add BCM2711 pixel valves Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 37/80] drm/vc4: crtc: Add BCM2711 pixelvalves Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 38/80] drm/vc4: hdmi: Use debugfs private field Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 39/80] drm/vc4: hdmi: Move structure to header Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 40/80] drm/vc4: hdmi: rework connectors and encoders Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 41/80] drm/vc4: hdmi: Remove DDC argument to connector_init Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 42/80] drm/vc4: hdmi: Rename hdmi to vc4_hdmi Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 43/80] drm/vc4: hdmi: Move accessors " Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 44/80] drm/vc4: hdmi: Use local vc4_hdmi directly Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 45/80] drm/vc4: hdmi: Add container_of macros for encoders and connectors Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 46/80] drm/vc4: hdmi: Pass vc4_hdmi to CEC code Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 47/80] drm/vc4: hdmi: Retrieve the vc4_hdmi at unbind using our device Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 48/80] drm/vc4: hdmi: Remove vc4_dev hdmi pointer Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 49/80] drm/vc4: hdmi: Remove vc4_hdmi_connector Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 50/80] drm/vc4: hdmi: Introduce resource init and variant Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 51/80] drm/vc4: hdmi: Implement a register layout abstraction Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 52/80] drm/vc4: hdmi: Add reset callback Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 53/80] drm/vc4: hdmi: Add PHY init and disable function Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 54/80] drm/vc4: hdmi: Add PHY RNG enable / " Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 55/80] drm/vc4: hdmi: Add a CSC setup callback Maxime Ripard
2020-09-04 15:45 ` Dave Stevenson
2020-09-03 8:01 ` [PATCH v5 56/80] drm/vc4: hdmi: Add a set_timings callback Maxime Ripard
2020-09-04 15:46 ` Dave Stevenson
2020-09-03 8:01 ` [PATCH v5 57/80] drm/vc4: hdmi: Store the encoder type in the variant structure Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 58/80] drm/vc4: hdmi: Deal with multiple debugfs files Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 59/80] drm/vc4: hdmi: Move CEC init to its own function Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 60/80] drm/vc4: hdmi: Add CEC support flag Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 61/80] drm/vc4: hdmi: Remove unused CEC_CLOCK_DIV define Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 62/80] drm/vc4: hdmi: Rename drm_encoder pointer in mode_valid Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 63/80] drm/vc4: hdmi: Adjust HSM clock rate depending on pixel rate Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 64/80] drm/vc4: hdmi: Use clk_set_min_rate instead Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 65/80] drm/vc4: hdmi: Use reg-names to retrieve the HDMI audio registers Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 66/80] drm/vc4: hdmi: Reset audio infoframe on encoder_enable if previously streaming Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 67/80] drm/vc4: hdmi: Set the b-frame marker to the match ALSA's default Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 68/80] drm/vc4: hdmi: Add audio-related callbacks Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 69/80] drm/vc4: hdmi: Deal with multiple ALSA cards Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 70/80] drm/vc4: hdmi: Remove register dumps in enable Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 71/80] drm/vc4: hdmi: Always recenter the HDMI FIFO Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 72/80] drm/vc4: hdmi: Implement finer-grained hooks Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 73/80] drm/vc4: hdmi: Do the VID_CTL configuration at once Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 74/80] drm/vc4: hdmi: Switch to blank pixels when disabled Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 75/80] drm/vc4: hdmi: Add pixel BVB clock control Maxime Ripard
2020-09-04 9:46 ` Dave Stevenson
2020-09-07 16:21 ` Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 76/80] drm/vc4: hdmi: Support the BCM2711 HDMI controllers Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 77/80] dt-bindings: display: vc4: hdmi: Add BCM2711 HDMI controllers bindings Maxime Ripard
2020-09-07 11:54 ` Hoegeun Kwon
2020-09-03 8:01 ` [PATCH v5 78/80] dt-bindings: display: vc4: Document BCM2711 VC5 Maxime Ripard
2020-09-03 8:01 ` [PATCH v5 79/80] drm/vc4: drv: Support BCM2711 Maxime Ripard
2020-09-04 15:51 ` Dave Stevenson
2020-09-03 8:01 ` [PATCH v5 80/80] ARM: dts: bcm2711: Enable the display pipeline Maxime Ripard
2020-09-07 12:03 ` Hoegeun Kwon
2020-09-08 16:31 ` Nicolas Saenz Julienne
2020-09-29 22:15 ` Nathan Chancellor
2020-09-30 14:07 ` Maxime Ripard
2020-09-30 16:38 ` Nathan Chancellor
2020-09-30 16:52 ` Stefan Wahren
2020-10-01 6:48 ` Maxime Ripard
2020-10-01 8:54 ` Maxime Ripard
2020-10-01 10:15 ` Tim Gover
2020-10-01 16:47 ` Nicolas Saenz Julienne
2020-10-01 19:45 ` Tim Gover
2020-10-02 15:19 ` Maxime Ripard
2020-10-02 15:57 ` Dave Stevenson
2020-10-06 15:26 ` Maxime Ripard
2020-10-06 17:14 ` Dave Stevenson
2020-10-08 9:35 ` Nicolas Saenz Julienne
2020-10-01 9:22 ` Nicolas Saenz Julienne
2020-10-01 9:33 ` Maxime Ripard
2020-10-01 18:09 ` Nathan Chancellor
2020-09-07 11:49 ` [PATCH v5 00/80] drm/vc4: Support BCM2711 Display Pipeline Hoegeun Kwon
2020-09-08 12:00 ` Maxime Ripard
2020-09-14 10:14 ` Hoegeun Kwon
2020-09-16 16:57 ` Maxime Ripard
2020-10-08 11:27 ` Maxime Ripard
2020-09-07 16:22 ` Maxime Ripard
2020-09-07 18:21 ` Nicolas Saenz Julienne
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