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Fri, 27 Aug 2021 08:43:07 +0200 (CEST) Received: from Berlix.phytec.de (172.16.0.117) by Berlix.phytec.de (172.16.0.117) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.8; Fri, 27 Aug 2021 08:43:06 +0200 Received: from Berlix.phytec.de ([fe80::c131:350d:c471:aafd]) by berlix.phytec.de ([fe80::c131:350d:c471:aafd%3]) with mapi id 15.01.2308.008; Fri, 27 Aug 2021 08:43:06 +0200 From: =?utf-8?B?U3RlZmFuIFJpZWRtw7xsbGVy?= To: "festevam@gmail.com" CC: "kernel@pengutronix.de" , "linux-imx@nxp.com" , "s.hauer@pengutronix.de" , "abel.vesa@nxp.com" , "sboyd@kernel.org" , "shawnguo@kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "mturquette@baylibre.com" , "linux-clk@vger.kernel.org" Subject: Re: [PATCH 2/2] clk: imx: imx6ul: Fix csi clk gate register Thread-Topic: [PATCH 2/2] clk: imx: imx6ul: Fix csi clk gate register Thread-Index: AQHXmo30E+AoBfzZwEa6zUYT/fs/1KuGFlQAgACwngA= Date: Fri, 27 Aug 2021 06:43:06 +0000 Message-ID: <1f1b90c7d2dfa2e80f9a0a7c4bc20d99e7177389.camel@phytec.de> References: <20210826152049.4175381-1-s.riedmueller@phytec.de> <20210826152049.4175381-2-s.riedmueller@phytec.de> In-Reply-To: Accept-Language: en-US, de-DE Content-Language: de-DE X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [172.16.0.116] Content-ID: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrHIsWRmVeSWpSXmKPExsWyRoChVLe6UyPR4Pk2AYtll44yWjy86m+x aupOFotNj6+xWnzsucdq0fVrJbPF5V1z2CwunnK1+Lt9E4vFv2sbWSxebBF34PZ4f6OV3WPn rLvsHptWdbJ5bF5S77Hx3Q4mj/6/Bh6fN8kFsEdx2aSk5mSWpRbp2yVwZUx+cJap4ItCxZVN G5kbGDsUuhg5OSQETCQWzlrF1sXIxSEksJxJ4tmdzUwQzkNGic2/utkhnE2MEjPO97CDtLAJ uEh8bvvGBmKLCOhKrDjRxQhiMwvMYJH4OoWji5GDQxioZs6UYogSV4nPk1cyQdhWEjsaD7GA 2CwCqhLLLmwCa+UVcJOY+WE9I8SuPYwSfVP7mUDmcAoESvxuiQGpYRSQlehseMcEsUpcYtOz 76wQHwhILNlznhnCFpV4+fgfVFxBoq2nE2wMs4CmxPpd+hCtFhL3Xj5jhrAVJaZ0P2SHOEFQ 4uTMJywTGMVnIdkwC6F7FpLuWUi6ZyHpXsDIuopRKDczOTu1KDNbryCjsiQ1WS8ldRMjMM4P T1S/tIOxb47HIUYmDsZDjBIczEoivAu+qyUK8aYkVlalFuXHF5XmpBYfYpTmYFES573fw5Qo JJCeWJKanZpakFoEk2Xi4JRqYDT+pRSd4yiwI+90rPv55S/5Huzd+26+XsqyJS7bzhveCo6/ FXkscXLqqu2nrm7azl+/xXJFtcDktb9Pnjc6s+9B9NTjnHc7PrOu+5Ld8VrI4a3wv4ArtxtF /d43sOy8ZLZ9/hl5IYVP+29lrTrZqPo3c1+s85ynEU+X5bsyBXKWJNQf9fXYr3pViaU4I9FQ i7moOBEAYf1HAOECAAA= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210826_234313_973044_5511BAAF X-CRM114-Status: GOOD ( 29.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Fabio, On Thu, 2021-08-26 at 17:10 -0300, Fabio Estevam wrote: > Hi Stefan, > > On Thu, Aug 26, 2021 at 12:20 PM Stefan Riedmueller > wrote: > > According to the imx6ul Reference Manual the csi clk gate register is > > CCM_CCGR3 (offset 0x74) bit 0/1. For the imx6ull on the other hand the > > Reference Manual lists register CCM_CCGR2 (offset 0x70) bit 2/3 as the > > csi clk gate which is the current setting. > > > > Tests have shown though that the correct csi clk gate register for the > > imx6ull is actually CCM_CCGR3 bit 0/1 as well. Thus set the correct > > register for both platforms. > > > > Signed-off-by: Stefan Riedmueller > > I tested the series on an imx6ull-evk with an OV5640 sensor: > > Tested-by: Fabio Estevam > > but in my case, I did not see the problem even without your patch. > > Most likely because the bootloader turned on the CSI clock. thanks for your testing and review. You're right, the csi clock is enabled by default and thus the issue only arises when you try to disable the clock e.g. to save power on a connected sensor. > > > --- > > drivers/clk/imx/clk-imx6ul.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c > > index 206e4c43f68f..5dd222fab01b 100644 > > --- a/drivers/clk/imx/clk-imx6ul.c > > +++ b/drivers/clk/imx/clk-imx6ul.c > > @@ -380,7 +380,6 @@ static void __init imx6ul_clocks_init(struct > > device_node *ccm_node) > > hws[IMX6ULL_CLK_ESAI_IPG] = > > imx_clk_hw_gate2_shared("esai_ipg", "ahb", base + 0x70, 0, > > &share_count_esai); > > hws[IMX6ULL_CLK_ESAI_MEM] = > > imx_clk_hw_gate2_shared("esai_mem", "ahb", base + 0x70, 0, > > &share_count_esai); > > } > > - hws[IMX6UL_CLK_CSI] = > > imx_clk_hw_gate2("csi", "csi_podf", base + > > 0x70, 2); > > hws[IMX6UL_CLK_I2C1] = > > imx_clk_hw_gate2("i2c1", "perclk", base + 0x70, 6); > > hws[IMX6UL_CLK_I2C2] = > > imx_clk_hw_gate2("i2c2", "perclk", base + 0x70, 8); > > hws[IMX6UL_CLK_I2C3] = > > imx_clk_hw_gate2("i2c3", "perclk", base + 0x70, 10); > > @@ -391,6 +390,7 @@ static void __init imx6ul_clocks_init(struct > > device_node *ccm_node) > > hws[IMX6UL_CLK_PXP] = > > imx_clk_hw_gate2("pxp", "axi", base + 0x70, 30); > > > > /* CCGR3 */ > > It would be nice to put a comment here explaining the imx6ull > Reference Manual mismatch. Sure I will prepare something. > > Maybe Abel could help to check internally at NXP? Yes, that would be nice! Regards, Stefan > > > + hws[IMX6UL_CLK_CSI] = > > imx_clk_hw_gate2("csi", "csi_podf", base + 0x74, 0); > > Thanks _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel