[PATCH 0/7] S3C2443/S3C2416: Implement support for ADC

[PATCH 0/7] S3C2443/S3C2416: Implement support for ADC

[Heiko Stübner]

The adc blocks of S3C2443 and S3C2416/2450 differ in some regards
from previous (S3C2410, etc) and later (S3C64XX, S5P) SoCs.

Defining more TYPE_ADCVx types for these SoCs would complicate the
necessary checks a lot. Therefore I opted for the use of quirk
constants which can describe the features of the respective adc
block and can be tested directly against.

This patch series replaces the type checks with checks for specific
quirks and adds support for S3C2443 and S3C2416/2450 on top of this.

Each patch was compile tested, and I tried to only do "equivalent
transforms" for the stuff on lower levels. But as I have only
access to S3C2416 hardware, real life testing happened only there.


Heiko Stuebner (7):
  S3C2443/S3C2416: Add adc registers
  s3c-adc: describe features via quirk constants
  s3c-adc: Replace TYPE_ADCVx conditionals with quirks
  s3c-adc: Fix mux bit modification in s3c_adc_select
  S3C24XX: Allow overriding of adc device name
  s3c-adc: Add support for S3C2443
  s3c-adc: Add support for S3C2416/S3C2450

 arch/arm/mach-s3c2416/mach-smdk2416.c         |    3 +
 arch/arm/mach-s3c2443/mach-smdk2443.c         |    3 +
 arch/arm/plat-samsung/adc.c                   |   89 +++++++++++++++++++-----
 arch/arm/plat-samsung/include/plat/adc-core.h |    2 +-
 arch/arm/plat-samsung/include/plat/regs-adc.h |    3 +
 5 files changed, 80 insertions(+), 20 deletions(-)

-- 
1.7.2.3

[PATCH 1/7] S3C2443/S3C2416: Add adc registers

[Heiko Stübner]

The adc blocks of the S3C2443 and S3C2416 define some
additional registers and bits.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/arm/plat-samsung/include/plat/regs-adc.h |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-samsung/include/plat/regs-adc.h b/arch/arm/plat-samsung/include/plat/regs-adc.h
index 035e8c3..f42c445 100644
--- a/arch/arm/plat-samsung/include/plat/regs-adc.h
+++ b/arch/arm/plat-samsung/include/plat/regs-adc.h
@@ -20,6 +20,7 @@
 #define S3C2410_ADCDAT0	   S3C2410_ADCREG(0x0C)
 #define S3C2410_ADCDAT1	   S3C2410_ADCREG(0x10)
 #define S3C64XX_ADCUPDN		S3C2410_ADCREG(0x14)
+#define S3C2443_ADCMUX		S3C2410_ADCREG(0x18)
 #define S3C64XX_ADCCLRINT	S3C2410_ADCREG(0x18)
 #define S5P_ADCMUX		S3C2410_ADCREG(0x1C)
 #define S3C64XX_ADCCLRINTPNDNUP	S3C2410_ADCREG(0x20)
@@ -33,6 +34,7 @@
 #define S3C2410_ADCCON_PRSCVLMASK	(0xFF<<6)
 #define S3C2410_ADCCON_SELMUX(x)	(((x)&0x7)<<3)
 #define S3C2410_ADCCON_MUXMASK		(0x7<<3)
+#define S3C2416_ADCCON_RESSEL		(1<<3)
 #define S3C2410_ADCCON_STDBM		(1<<2)
 #define S3C2410_ADCCON_READ_START	(1<<1)
 #define S3C2410_ADCCON_ENABLE_START	(1<<0)
@@ -40,6 +42,7 @@
 
 
 /* ADCTSC Register Bits */
+#define S3C2443_ADCTSC_UD_SEN		(1<<8)
 #define S3C2410_ADCTSC_YM_SEN		(1<<7)
 #define S3C2410_ADCTSC_YP_SEN		(1<<6)
 #define S3C2410_ADCTSC_XM_SEN		(1<<5)
-- 
1.7.2.3

[PATCH 2/7] s3c-adc: describe features via quirk constants

[Heiko Stübner]

The adc blocks of S3C2410 through S5P have a multitude of
quirks, i.e. moved bits or whole new registers.

This patch tries to describe these individual features
through constants which can be used to describe an adc.

As SoCs sometimes share only some of these quirks defining
TYPE_ADCVx values for each one wouldn't scale well when
adding more variants.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/arm/plat-samsung/adc.c |   29 +++++++++++++++++++++++++++++
 1 files changed, 29 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c
index ee8deef..ba21b6a 100644
--- a/arch/arm/plat-samsung/adc.c
+++ b/arch/arm/plat-samsung/adc.c
@@ -45,6 +45,35 @@ enum s3c_cpu_type {
 	TYPE_ADCV3, /* S5PV210, S5PC110, EXYNOS4210 */
 };
 
+/*
+ * Resolution of the ADC - 10 or 12 bit
+ */
+#define S3C_ADC_QUIRK_10BIT		0
+#define S3C_ADC_QUIRK_12BIT		(1<<0)
+
+/*
+ * 12bit ADC can switch resolution between 10 bit and 12 bit
+ * ADCCON bit 03 for S3C2416
+ * ADCCON bit 16 for S3C64XX and up
+ */
+#define S3C_ADC_QUIRK_RESSEL03		(1<<1)
+#define S3C_ADC_QUIRK_RESSEL16		(1<<2)
+
+/*
+ * Input channel select can either be in
+ * - reg ADCCON, bit for S3C24XX and S3C64XX
+ * - reg base+0x18 for 2443/2416/2450
+ * - reg base+0x1C for S5P
+ */
+#define S3C_ADC_QUIRK_MUXADCCON		(1<<3)
+#define S3C_ADC_QUIRK_MUX18		(1<<4)
+#define S3C_ADC_QUIRK_MUX1C		(1<<5)
+
+/*
+ * CLRINT register on S3C64xx
+ */
+#define S3C_ADC_QUIRK_CLRINT		(1<<6)
+
 struct s3c_adc_client {
 	struct platform_device	*pdev;
 	struct list_head	 pend;
-- 
1.7.2.3

[PATCH 3/7] s3c-adc: Replace TYPE_ADCVx conditionals with quirks

[Heiko Stübner]

This patch replaces the static TYPE_ADCVs checks with checks for
specific features of an adc block. For this the s3c_cpu_type enum
in driver_data ist int containing containing the bit values
describing the indivial adc block.

This patch contains no functional changes, it merely replaces
the type checks with checks for indidual quirks.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/arm/plat-samsung/adc.c |   33 +++++++++++++++++----------------
 1 files changed, 17 insertions(+), 16 deletions(-)

diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c
index ba21b6a..49769cb 100644
--- a/arch/arm/plat-samsung/adc.c
+++ b/arch/arm/plat-samsung/adc.c
@@ -39,12 +39,6 @@
  * action is required.
  */
 
-enum s3c_cpu_type {
-	TYPE_ADCV1, /* S3C24XX */
-	TYPE_ADCV2, /* S3C64XX, S5P64X0, S5PC100 */
-	TYPE_ADCV3, /* S5PV210, S5PC110, EXYNOS4210 */
-};
-
 /*
  * Resolution of the ADC - 10 or 12 bit
  */
@@ -123,7 +117,7 @@ static inline void s3c_adc_select(struct adc_device *adc,
 				  struct s3c_adc_client *client)
 {
 	unsigned con = readl(adc->regs + S3C2410_ADCCON);
-	enum s3c_cpu_type cpu = platform_get_device_id(adc->pdev)->driver_data;
+	int cpu = platform_get_device_id(adc->pdev)->driver_data;
 
 	client->select_cb(client, 1);
 
@@ -132,7 +126,7 @@ static inline void s3c_adc_select(struct adc_device *adc,
 	con &= ~S3C2410_ADCCON_STARTMASK;
 
 	if (!client->is_ts) {
-		if (cpu == TYPE_ADCV3)
+		if (cpu & S3C_ADC_QUIRK_MUX1C)
 			writel(client->channel & 0xf, adc->regs + S5P_ADCMUX);
 		else
 			con |= S3C2410_ADCCON_SELMUX(client->channel);
@@ -308,7 +302,7 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw)
 {
 	struct adc_device *adc = pw;
 	struct s3c_adc_client *client = adc->cur;
-	enum s3c_cpu_type cpu = platform_get_device_id(adc->pdev)->driver_data;
+	int cpu = platform_get_device_id(adc->pdev)->driver_data;
 	unsigned data0, data1;
 
 	if (!client) {
@@ -322,7 +316,7 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw)
 
 	client->nr_samples--;
 
-	if (cpu != TYPE_ADCV1) {
+	if (cpu & S3C_ADC_QUIRK_12BIT) {
 		/* S3C64XX/S5P ADC resolution is 12-bit */
 		data0 &= 0xfff;
 		data1 &= 0xfff;
@@ -349,7 +343,7 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw)
 	}
 
 exit:
-	if (cpu != TYPE_ADCV1) {
+	if (cpu & S3C_ADC_QUIRK_CLRINT) {
 		/* Clear ADC interrupt */
 		writel(0, adc->regs + S3C64XX_ADCCLRINT);
 	}
@@ -423,7 +417,7 @@ static int s3c_adc_probe(struct platform_device *pdev)
 	clk_enable(adc->clk);
 
 	tmp = adc->prescale | S3C2410_ADCCON_PRSCEN;
-	if (platform_get_device_id(pdev)->driver_data != TYPE_ADCV1) {
+	if (platform_get_device_id(pdev)->driver_data & S3C_ADC_QUIRK_12BIT) {
 		/* Enable 12-bit ADC resolution */
 		tmp |= S3C64XX_ADCCON_RESSEL;
 	}
@@ -504,7 +498,7 @@ static int s3c_adc_resume(struct device *dev)
 
 	tmp = adc->prescale | S3C2410_ADCCON_PRSCEN;
 	/* Enable 12-bit ADC resolution */
-	if (platform_get_device_id(pdev)->driver_data != TYPE_ADCV1)
+	if (platform_get_device_id(pdev)->driver_data & S3C_ADC_QUIRK_12BIT)
 		tmp |= S3C64XX_ADCCON_RESSEL;
 	writel(tmp, adc->regs + S3C2410_ADCCON);
 
@@ -519,13 +513,20 @@ static int s3c_adc_resume(struct device *dev)
 static struct platform_device_id s3c_adc_driver_ids[] = {
 	{
 		.name           = "s3c24xx-adc",
-		.driver_data    = TYPE_ADCV1,
+		.driver_data    = S3C_ADC_QUIRK_10BIT |
+					S3C_ADC_QUIRK_MUXADCCON,
 	}, {
 		.name           = "s3c64xx-adc",
-		.driver_data    = TYPE_ADCV2,
+		.driver_data    = S3C_ADC_QUIRK_12BIT |
+					S3C_ADC_QUIRK_MUXADCCON |
+					S3C_ADC_QUIRK_RESSEL16 |
+					S3C_ADC_QUIRK_CLRINT,
 	}, {
 		.name		= "samsung-adc-v3",
-		.driver_data	= TYPE_ADCV3,
+		.driver_data	= S3C_ADC_QUIRK_12BIT |
+					S3C_ADC_QUIRK_MUX1C |
+					S3C_ADC_QUIRK_RESSEL16 |
+					S3C_ADC_QUIRK_CLRINT,
 	},
 	{ }
 };
-- 
1.7.2.3

[PATCH 4/7] s3c-adc: Fix mux bit modification in s3c_adc_select

[Heiko Stübner]

The mux bits in the adccon register should be cleared only
if muxing is really done in ADCCON and not another register.

This patch introduces a conditional for this.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/arm/plat-samsung/adc.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c
index 49769cb..be4e643 100644
--- a/arch/arm/plat-samsung/adc.c
+++ b/arch/arm/plat-samsung/adc.c
@@ -121,7 +121,8 @@ static inline void s3c_adc_select(struct adc_device *adc,
 
 	client->select_cb(client, 1);
 
-	con &= ~S3C2410_ADCCON_MUXMASK;
+	if (cpu & S3C_ADC_QUIRK_MUXADCCON)
+		con &= ~S3C2410_ADCCON_MUXMASK;
 	con &= ~S3C2410_ADCCON_STDBM;
 	con &= ~S3C2410_ADCCON_STARTMASK;
 
-- 
1.7.2.3

[PATCH 5/7] S3C24XX: Allow overriding of adc device name

[Heiko Stübner]

The adc blocks of S3C2443 and S3C2416 contain quirks not present
in the stock S3C24xx adc. Therefore allow them to alter the
device name via s3c_adc_setname.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/arm/plat-samsung/include/plat/adc-core.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/plat-samsung/include/plat/adc-core.h b/arch/arm/plat-samsung/include/plat/adc-core.h
index a281568..a927bee 100644
--- a/arch/arm/plat-samsung/include/plat/adc-core.h
+++ b/arch/arm/plat-samsung/include/plat/adc-core.h
@@ -20,7 +20,7 @@
 /* re-define device name depending on support. */
 static inline void s3c_adc_setname(char *name)
 {
-#ifdef CONFIG_SAMSUNG_DEV_ADC
+#if defined(CONFIG_SAMSUNG_DEV_ADC) || defined(CONFIG_PLAT_S3C24XX)
 	s3c_device_adc.name = name;
 #endif
 }
-- 
1.7.2.3

[PATCH 6/7] s3c-adc: Add support for S3C2443

[Heiko Stübner]

The S3C2443-adc is 10 bit wide and has its mux-select
in an extra register at base+0x18

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/arm/mach-s3c2443/mach-smdk2443.c |    3 +++
 arch/arm/plat-samsung/adc.c           |    6 ++++++
 2 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s3c2443/mach-smdk2443.c b/arch/arm/mach-s3c2443/mach-smdk2443.c
index bec107e..45d3b93 100644
--- a/arch/arm/mach-s3c2443/mach-smdk2443.c
+++ b/arch/arm/mach-s3c2443/mach-smdk2443.c
@@ -44,6 +44,7 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/adc-core.h>
 
 #include <plat/common-smdk.h>
 
@@ -129,6 +130,8 @@ static void __init smdk2443_machine_init(void)
 {
 	s3c_i2c0_set_platdata(NULL);
 
+	s3c_adc_setname("s3c2443-adc");
+
 #ifdef CONFIG_SND_SOC_SMDK2443_WM9710
 	s3c24xx_ac97_setup_gpio(S3C24XX_AC97_GPE0);
 #endif
diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c
index be4e643..4fb26c6 100644
--- a/arch/arm/plat-samsung/adc.c
+++ b/arch/arm/plat-samsung/adc.c
@@ -129,6 +129,8 @@ static inline void s3c_adc_select(struct adc_device *adc,
 	if (!client->is_ts) {
 		if (cpu & S3C_ADC_QUIRK_MUX1C)
 			writel(client->channel & 0xf, adc->regs + S5P_ADCMUX);
+		else if (cpu & S3C_ADC_QUIRK_MUX18)
+			writel(client->channel & 0xf, adc->regs + S3C2443_ADCMUX);
 		else
 			con |= S3C2410_ADCCON_SELMUX(client->channel);
 	}
@@ -517,6 +519,10 @@ static struct platform_device_id s3c_adc_driver_ids[] = {
 		.driver_data    = S3C_ADC_QUIRK_10BIT |
 					S3C_ADC_QUIRK_MUXADCCON,
 	}, {
+		.name           = "s3c2443-adc",
+		.driver_data    = S3C_ADC_QUIRK_10BIT |
+					S3C_ADC_QUIRK_MUX18,
+	}, {
 		.name           = "s3c64xx-adc",
 		.driver_data    = S3C_ADC_QUIRK_12BIT |
 					S3C_ADC_QUIRK_MUXADCCON |
-- 
1.7.2.3

[PATCH 7/7] s3c-adc: Add support for S3C2416/S3C2450

[Heiko Stübner]

The ADC of the S3C2416/2450 SoC is 10 or 12 bit wide, has its
source selection in the register base+0x18 and its width
selection in bit 03 of the ADCCON register.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/arm/mach-s3c2416/mach-smdk2416.c |    3 +++
 arch/arm/plat-samsung/adc.c           |   24 +++++++++++++++++++-----
 2 files changed, 22 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-s3c2416/mach-smdk2416.c b/arch/arm/mach-s3c2416/mach-smdk2416.c
index a9eee53..deddeb3 100644
--- a/arch/arm/mach-s3c2416/mach-smdk2416.c
+++ b/arch/arm/mach-s3c2416/mach-smdk2416.c
@@ -50,6 +50,7 @@
 #include <plat/nand.h>
 #include <plat/sdhci.h>
 #include <plat/udc.h>
+#include <plat/adc-core.h>
 
 #include <plat/regs-fb-v4.h>
 #include <plat/fb.h>
@@ -225,6 +226,8 @@ static void __init smdk2416_machine_init(void)
 	s3c_i2c0_set_platdata(NULL);
 	s3c_fb_set_platdata(&smdk2416_fb_platdata);
 
+	s3c_adc_setname("s3c2416-adc");
+
 	s3c_sdhci0_set_platdata(&smdk2416_hsmmc0_pdata);
 	s3c_sdhci1_set_platdata(&smdk2416_hsmmc1_pdata);
 
diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c
index 4fb26c6..a5a73a4 100644
--- a/arch/arm/plat-samsung/adc.c
+++ b/arch/arm/plat-samsung/adc.c
@@ -357,6 +357,7 @@ static int s3c_adc_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct adc_device *adc;
+	int cpu = platform_get_device_id(pdev)->driver_data;
 	struct resource *regs;
 	int ret;
 	unsigned tmp;
@@ -420,9 +421,12 @@ static int s3c_adc_probe(struct platform_device *pdev)
 	clk_enable(adc->clk);
 
 	tmp = adc->prescale | S3C2410_ADCCON_PRSCEN;
-	if (platform_get_device_id(pdev)->driver_data & S3C_ADC_QUIRK_12BIT) {
-		/* Enable 12-bit ADC resolution */
-		tmp |= S3C64XX_ADCCON_RESSEL;
+	/* Enable 12-bit ADC resolution */
+	if (cpu & S3C_ADC_QUIRK_12BIT) {
+		if (cpu & S3C_ADC_QUIRK_RESSEL03)
+			tmp |= S3C2416_ADCCON_RESSEL;
+		else
+			tmp |= S3C64XX_ADCCON_RESSEL;
 	}
 	writel(tmp, adc->regs + S3C2410_ADCCON);
 
@@ -490,6 +494,7 @@ static int s3c_adc_resume(struct device *dev)
 	struct platform_device *pdev = container_of(dev,
 			struct platform_device, dev);
 	struct adc_device *adc = platform_get_drvdata(pdev);
+	int cpu = platform_get_device_id(pdev)->driver_data;
 	int ret;
 	unsigned long tmp;
 
@@ -501,8 +506,12 @@ static int s3c_adc_resume(struct device *dev)
 
 	tmp = adc->prescale | S3C2410_ADCCON_PRSCEN;
 	/* Enable 12-bit ADC resolution */
-	if (platform_get_device_id(pdev)->driver_data & S3C_ADC_QUIRK_12BIT)
-		tmp |= S3C64XX_ADCCON_RESSEL;
+	if (cpu & S3C_ADC_QUIRK_12BIT) {
+		if (cpu & S3C_ADC_QUIRK_RESSEL03)
+			tmp |= S3C2416_ADCCON_RESSEL;
+		else
+			tmp |= S3C64XX_ADCCON_RESSEL;
+	}
 	writel(tmp, adc->regs + S3C2410_ADCCON);
 
 	return 0;
@@ -523,6 +532,11 @@ static struct platform_device_id s3c_adc_driver_ids[] = {
 		.driver_data    = S3C_ADC_QUIRK_10BIT |
 					S3C_ADC_QUIRK_MUX18,
 	}, {
+		.name           = "s3c2416-adc",
+		.driver_data    = S3C_ADC_QUIRK_12BIT |
+					S3C_ADC_QUIRK_MUX18 |
+					S3C_ADC_QUIRK_RESSEL03,
+	}, {
 		.name           = "s3c64xx-adc",
 		.driver_data    = S3C_ADC_QUIRK_12BIT |
 					S3C_ADC_QUIRK_MUXADCCON |
-- 
1.7.2.3

[PATCH 2/7] s3c-adc: describe features via quirk constants

[Kukjin Kim]

Heiko St?bner wrote:
> 
> Hi Kgene,
> 
Hi,

(snip)

> > > Thanks for your understanding and please re-send it :)
> >
> > Any re-sending?
> as I'm this in my spare time I'm not sure I will make your "deadline" for
the
> merge-window, but will try to get it sorted today or tomorrow.
> 
OK. I cannot promise now but I think you can do it for upcoming merge window
:)

> Meanwhile please take a look at the armclk series and the hsmmc devname
patch.
> 
OK, sorry still missing.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

[PATCH 2/7] s3c-adc: describe features via quirk constants

[Heiko Stübner]

Hi Kgene,

Am Montag, 10. Oktober 2011, 06:28:19 schrieb Kukjin Kim:
> Kukjin Kim wrote:
> > Heiko St?bner wrote:
> > > Hi Kgene,
> > > 
> > > Am Sonntag 02 Oktober 2011, 09:38:18 schrieb Kukjin Kim:
> > > > How about following? I think following is also not bad...
> > > 
> > > ok, I don't claim to have the right solution, so if keeping the
> > > TYPE_xxx
> 
> enum
> 
> > > is better, I will do a rework of the series according to your solution
> 
> and
> 
> > > resend it.
> > 
> > Thanks for your understanding and please re-send it :)
> 
> Any re-sending?
as I'm this in my spare time I'm not sure I will make your "deadline" for the 
merge-window, but will try to get it sorted today or tomorrow.

Meanwhile please take a look at the armclk series and the hsmmc devname patch.

Heiko

[PATCH 2/7] s3c-adc: describe features via quirk constants

[Kukjin Kim]

Kukjin Kim wrote:
> 
> Heiko St?bner wrote:
> >
> > Hi Kgene,
> >
> > Am Sonntag 02 Oktober 2011, 09:38:18 schrieb Kukjin Kim:
> > > How about following? I think following is also not bad...
> > ok, I don't claim to have the right solution, so if keeping the TYPE_xxx
enum
> > is better, I will do a rework of the series according to your solution
and
> > resend it.
> >
> Thanks for your understanding and please re-send it :)
> 
Any re-sending?

> > Could I meanwhile interest you in the patches for the S3C2416 armclk and
> hsmmc
> > (from 28 Sep 2011) :-) ?
> >
> Sure, will check it soon, maybe tomorrow?
> Anyway, if any problems, let you know.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

[PATCH 2/7] s3c-adc: describe features via quirk constants

[Kukjin Kim]

Heiko St?bner wrote:
> 
> Hi Kgene,
> 
> Am Sonntag 02 Oktober 2011, 09:38:18 schrieb Kukjin Kim:
> > How about following? I think following is also not bad...
> ok, I don't claim to have the right solution, so if keeping the TYPE_xxx
enum
> is better, I will do a rework of the series according to your solution and
> resend it.
> 
Thanks for your understanding and please re-send it :)

> Could I meanwhile interest you in the patches for the S3C2416 armclk and
hsmmc
> (from 28 Sep 2011) :-) ?
> 
Sure, will check it soon, maybe tomorrow?
Anyway, if any problems, let you know.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

[PATCH 2/7] s3c-adc: describe features via quirk constants

[Heiko Stübner]

Hi Kgene,

Am Sonntag 02 Oktober 2011, 09:38:18 schrieb Kukjin Kim:
> How about following? I think following is also not bad...
ok, I don't claim to have the right solution, so if keeping the TYPE_xxx enum 
is better, I will do a rework of the series according to your solution and 
resend it.

Could I meanwhile interest you in the patches for the S3C2416 armclk and hsmmc  
(from 28 Sep 2011) :-) ?

Thanks
Heiko


> diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c
> index ee8deef..f5c6703 100644
> --- a/arch/arm/plat-samsung/adc.c
> +++ b/arch/arm/plat-samsung/adc.c
> @@ -41,6 +41,8 @@
> 
>  enum s3c_cpu_type {
>  	TYPE_ADCV1, /* S3C24XX */
> +	TYPE_ADCV11, /* S3C2416 */
> +	TYPE_ADCV12, /* S3C2443 */
>  	TYPE_ADCV2, /* S3C64XX, S5P64X0, S5PC100 */
>  	TYPE_ADCV3, /* S5PV210, S5PC110, EXYNOS4210 */
>  };
> @@ -98,13 +100,17 @@ static inline void s3c_adc_select(struct adc_device
> *adc,
> 
>  	client->select_cb(client, 1);
> 
> -	con &= ~S3C2410_ADCCON_MUXMASK;
> +	if (cpu == TYPE_ADCV1 || cpu == TYPE_ADCV2)
> +		con &= ~S3C2410_ADCCON_MUXMASK;
>  	con &= ~S3C2410_ADCCON_STDBM;
>  	con &= ~S3C2410_ADCCON_STARTMASK;
> 
>  	if (!client->is_ts) {
>  		if (cpu == TYPE_ADCV3)
>  			writel(client->channel & 0xf, adc->regs +
> S5P_ADCMUX);
> +		elif (cpu == TYPE_ADCV12)
> +			writel(client->channel & 0xf,
> +				adc->regs + S3C2443_ADCMUX);
>  		else
>  			con |= S3C2410_ADCCON_SELMUX(client->channel);
>  	}
> @@ -293,13 +299,13 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw)
> 
>  	client->nr_samples--;
> 
> -	if (cpu != TYPE_ADCV1) {
> -		/* S3C64XX/S5P ADC resolution is 12-bit */
> -		data0 &= 0xfff;
> -		data1 &= 0xfff;
> -	} else {
> +	if (cpu == TYPE_ADCV1 || cpu == TYPE_ADCV12) {
>  		data0 &= 0x3ff;
>  		data1 &= 0x3ff;
> +	} else {
> +		/* S3C2416, S3C64XX/S5P ADC resolution is 12-bit */
> +		data0 &= 0xfff;
> +		data1 &= 0xfff;
>  	}
> 
>  	if (client->convert_cb)
> @@ -320,7 +326,7 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw)
>  	}
> 
>  exit:
> -	if (cpu != TYPE_ADCV1) {
> +	if (cpu == TYPE_ADCV2 || cpu == TYPE_ADCV3) {
>  		/* Clear ADC interrupt */
>  		writel(0, adc->regs + S3C64XX_ADCCLRINT);
>  	}
> @@ -332,6 +338,7 @@ static int s3c_adc_probe(struct platform_device *pdev)
>  	struct device *dev = &pdev->dev;
>  	struct adc_device *adc;
>  	struct resource *regs;
> +	enum s3c_cpu_type cpu = platform_get_device_id(pdev)->driver_data;
>  	int ret;
>  	unsigned tmp;
> 
> @@ -394,10 +401,13 @@ static int s3c_adc_probe(struct platform_device
> *pdev) clk_enable(adc->clk);
> 
>  	tmp = adc->prescale | S3C2410_ADCCON_PRSCEN;
> -	if (platform_get_device_id(pdev)->driver_data != TYPE_ADCV1) {
> -		/* Enable 12-bit ADC resolution */
> +
> +	/* Enable 12-bit ADC resolution */
> +	if (cpu == TYPE_ADCV11)
> +		tmp |= S3C2416_ADCCON_RESSEL;
> +	if (cpu == TYPE_ADCV2 || cpu == TYPE_ADCV3)
>  		tmp |= S3C64XX_ADCCON_RESSEL;
> -	}
> +
>  	writel(tmp, adc->regs + S3C2410_ADCCON);
> 
>  	dev_info(dev, "attached adc driver\n");
> @@ -464,6 +474,7 @@ static int s3c_adc_resume(struct device *dev)
>  	struct platform_device *pdev = container_of(dev,
>  			struct platform_device, dev);
>  	struct adc_device *adc = platform_get_drvdata(pdev);
> +	enum s3c_cpu_type cpu = platform_get_device_id(pdev)->driver_data;
>  	int ret;
>  	unsigned long tmp;
> 
> @@ -474,9 +485,13 @@ static int s3c_adc_resume(struct device *dev)
>  	enable_irq(adc->irq);
> 
>  	tmp = adc->prescale | S3C2410_ADCCON_PRSCEN;
> +
>  	/* Enable 12-bit ADC resolution */
> -	if (platform_get_device_id(pdev)->driver_data != TYPE_ADCV1)
> +	if (cpu == TYPE_ADCV11)
> +		tmp |= S3C2416_ADCCON_RESSEL;
> +	if (cpu == TYPE_ADCV2 || cpu == TYPE_ADCV3)
>  		tmp |= S3C64XX_ADCCON_RESSEL;
> +
>  	writel(tmp, adc->regs + S3C2410_ADCCON);
> 
>  	return 0;
> @@ -492,6 +507,12 @@ static struct platform_device_id s3c_adc_driver_ids[]
> = {
>  		.name           = "s3c24xx-adc",
>  		.driver_data    = TYPE_ADCV1,
>  	}, {
> +		.name		= "s3c2416-adc",
> +		.driver_data	= TYPE_ADCV11
> +	}, {
> +		.name		= "s3c2443-adc",
> +		.driver_data	= TYPE_ADCV12
> +	}, {
>  		.name           = "s3c64xx-adc",
>  		.driver_data    = TYPE_ADCV2,
>  	}, {
> 
> Thanks.
> 
> Best regards,
> Kgene.

[PATCH 2/7] s3c-adc: describe features via quirk constants

[Kukjin Kim]

Heiko St?bner wrote:
> 
> Hi,
> 
> Am Mittwoch, 21. September 2011, 14:32:14 schrieben Sie:
> > Heiko St?bner wrote:
> > > The adc blocks of S3C2410 through S5P have a multitude of
> > > quirks, i.e. moved bits or whole new registers.
> > >
> > > This patch tries to describe these individual features
> > > through constants which can be used to describe an adc.
> > >
> > > As SoCs sometimes share only some of these quirks defining
> > > TYPE_ADCVx values for each one wouldn't scale well when
> > > adding more variants.
> >
> > Hi Heiko,
> >
> > I don't have idea we really need to use QUIRK in this case...as I know,
the
> > QUIRK is used on other situation...
> >
> > In addition, the TYPE_ADCVx can support each Samsung SoCs' ADC...but I
> need
> > to check again.
> The current types could not support the features of the 2443 and 2416/2450
- I
> checked the datasheets.
> 
> The mux register in base+0x18 does not exist on any of the current
platforms.
> Also the bit 3 in ADCCON to select the resolution is specific to the
2416/2450
> (see comments above constants and quirk definitions in patches 6 and 7).
> 
> So to support these SoCs would require the definition of two new types.
> Including these new types in the existing conditionals would introduce a
lot
> of statements like
> 	if ( (TYPE_X || TYPE_Y) && !TYPE_Z)
> 
> In my opinion testing for specific features also describes the difference
> between implementations better if one reads the code later on.
> 
> 
> I will change the styling of the "<<"s but am wondering why checkpatch did
not
> complain, i.e. it complains for all other whitespace mistakes one can make
but
> not these.
> 

Hi Heiko,

How about following? I think following is also not bad...

diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c
index ee8deef..f5c6703 100644
--- a/arch/arm/plat-samsung/adc.c
+++ b/arch/arm/plat-samsung/adc.c
@@ -41,6 +41,8 @@
 
 enum s3c_cpu_type {
 	TYPE_ADCV1, /* S3C24XX */
+	TYPE_ADCV11, /* S3C2416 */
+	TYPE_ADCV12, /* S3C2443 */
 	TYPE_ADCV2, /* S3C64XX, S5P64X0, S5PC100 */
 	TYPE_ADCV3, /* S5PV210, S5PC110, EXYNOS4210 */
 };
@@ -98,13 +100,17 @@ static inline void s3c_adc_select(struct adc_device
*adc,
 
 	client->select_cb(client, 1);
 
-	con &= ~S3C2410_ADCCON_MUXMASK;
+	if (cpu == TYPE_ADCV1 || cpu == TYPE_ADCV2)
+		con &= ~S3C2410_ADCCON_MUXMASK;
 	con &= ~S3C2410_ADCCON_STDBM;
 	con &= ~S3C2410_ADCCON_STARTMASK;
 
 	if (!client->is_ts) {
 		if (cpu == TYPE_ADCV3)
 			writel(client->channel & 0xf, adc->regs +
S5P_ADCMUX);
+		elif (cpu == TYPE_ADCV12)
+			writel(client->channel & 0xf,
+				adc->regs + S3C2443_ADCMUX);
 		else
 			con |= S3C2410_ADCCON_SELMUX(client->channel);
 	}
@@ -293,13 +299,13 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw)
 
 	client->nr_samples--;
 
-	if (cpu != TYPE_ADCV1) {
-		/* S3C64XX/S5P ADC resolution is 12-bit */
-		data0 &= 0xfff;
-		data1 &= 0xfff;
-	} else {
+	if (cpu == TYPE_ADCV1 || cpu == TYPE_ADCV12) {
 		data0 &= 0x3ff;
 		data1 &= 0x3ff;
+	} else {
+		/* S3C2416, S3C64XX/S5P ADC resolution is 12-bit */
+		data0 &= 0xfff;
+		data1 &= 0xfff;
 	}
 
 	if (client->convert_cb)
@@ -320,7 +326,7 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw)
 	}
 
 exit:
-	if (cpu != TYPE_ADCV1) {
+	if (cpu == TYPE_ADCV2 || cpu == TYPE_ADCV3) {
 		/* Clear ADC interrupt */
 		writel(0, adc->regs + S3C64XX_ADCCLRINT);
 	}
@@ -332,6 +338,7 @@ static int s3c_adc_probe(struct platform_device *pdev)
 	struct device *dev = &pdev->dev;
 	struct adc_device *adc;
 	struct resource *regs;
+	enum s3c_cpu_type cpu = platform_get_device_id(pdev)->driver_data;
 	int ret;
 	unsigned tmp;
 
@@ -394,10 +401,13 @@ static int s3c_adc_probe(struct platform_device *pdev)
 	clk_enable(adc->clk);
 
 	tmp = adc->prescale | S3C2410_ADCCON_PRSCEN;
-	if (platform_get_device_id(pdev)->driver_data != TYPE_ADCV1) {
-		/* Enable 12-bit ADC resolution */
+
+	/* Enable 12-bit ADC resolution */
+	if (cpu == TYPE_ADCV11)
+		tmp |= S3C2416_ADCCON_RESSEL;
+	if (cpu == TYPE_ADCV2 || cpu == TYPE_ADCV3)
 		tmp |= S3C64XX_ADCCON_RESSEL;
-	}
+
 	writel(tmp, adc->regs + S3C2410_ADCCON);
 
 	dev_info(dev, "attached adc driver\n");
@@ -464,6 +474,7 @@ static int s3c_adc_resume(struct device *dev)
 	struct platform_device *pdev = container_of(dev,
 			struct platform_device, dev);
 	struct adc_device *adc = platform_get_drvdata(pdev);
+	enum s3c_cpu_type cpu = platform_get_device_id(pdev)->driver_data;
 	int ret;
 	unsigned long tmp;
 
@@ -474,9 +485,13 @@ static int s3c_adc_resume(struct device *dev)
 	enable_irq(adc->irq);
 
 	tmp = adc->prescale | S3C2410_ADCCON_PRSCEN;
+
 	/* Enable 12-bit ADC resolution */
-	if (platform_get_device_id(pdev)->driver_data != TYPE_ADCV1)
+	if (cpu == TYPE_ADCV11)
+		tmp |= S3C2416_ADCCON_RESSEL;
+	if (cpu == TYPE_ADCV2 || cpu == TYPE_ADCV3)
 		tmp |= S3C64XX_ADCCON_RESSEL;
+
 	writel(tmp, adc->regs + S3C2410_ADCCON);
 
 	return 0;
@@ -492,6 +507,12 @@ static struct platform_device_id s3c_adc_driver_ids[] =
{
 		.name           = "s3c24xx-adc",
 		.driver_data    = TYPE_ADCV1,
 	}, {
+		.name		= "s3c2416-adc",
+		.driver_data	= TYPE_ADCV11
+	}, {
+		.name		= "s3c2443-adc",
+		.driver_data	= TYPE_ADCV12
+	}, {
 		.name           = "s3c64xx-adc",
 		.driver_data    = TYPE_ADCV2,
 	}, {

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

> Heiko
> 
> >
> > > Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> > > ---
> > >
> > >  arch/arm/plat-samsung/adc.c |   29 +++++++++++++++++++++++++++++
> > >  1 files changed, 29 insertions(+), 0 deletions(-)
> > >
> > > diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c
> > > index ee8deef..b209d58 100644
> > > --- a/arch/arm/plat-samsung/adc.c
> > > +++ b/arch/arm/plat-samsung/adc.c
> > > @@ -45,6 +45,35 @@ enum s3c_cpu_type {
> > >
> > >  	TYPE_ADCV3, /* S5PV210, S5PC110, EXYNOS4210 */
> > >
> > >  };
> > >
> > > +/*
> > > + * Resolution of the ADC - 10 or 12 bit
> > > + */
> >
> > /* ... */
> >
> > > +#define S3C_ADC_QUIRK_10BIT		0
> > > +#define S3C_ADC_QUIRK_12BIT		(1<<0)
> >
> > According to coding style, should be added blank around <<.
> >
> > > +
> > > +/*
> > > + * 12bit ADC can switch resolution between 10 bit and 12 bit
> > > + * ADCCON bit 03 for S3C2416
> > > + * ADCCON bit 16 for S3C64XX and up
> > > + */
> > > +#define S3C_ADC_QUIRK_RESSEL03		(1<<1)
> > > +#define S3C_ADC_QUIRK_RESSEL16		(1<<2)
> >
> > Same as above.
> >
> > > +
> > > +/*
> > > + * Input channel select can either be in
> > > + * - reg ADCCON, bit for S3C24XX and S3C64XX
> > > + * - reg base+0x18 for 2443/2416/2450
> > > + * - reg base+0x1C for S5P
> > > + */
> > > +#define S3C_ADC_QUIRK_MUXADCCON		(1<<3)
> > > +#define S3C_ADC_QUIRK_MUX18		(1<<4)
> > > +#define S3C_ADC_QUIRK_MUX1C		(1<<5)
> >
> > Same.
> >
> > > +
> > > +/*
> > > + * CLRINT register on S3C64xx
> > > + */
> >
> > /* ... */
> >
> > > +#define S3C_ADC_QUIRK_CLRINT		(1<<6)
> >
> > Same.
> >
> > > +
> > >
> > >  struct s3c_adc_client {
> > >
> > >  	struct platform_device	*pdev;
> > >  	struct list_head	 pend;
> > >
> > > --
> > > 1.7.2.3
> >
> > Thanks.
> >
> > Best regards,
> > Kgene.
> > --
> > Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
> > SW Solution Development Team, Samsung Electronics Co., Ltd.

[PATCH 2/7] s3c-adc: describe features via quirk constants

[Heiko Stübner]

Hi,

Am Mittwoch, 21. September 2011, 14:32:14 schrieben Sie:
> Heiko St?bner wrote:
> > The adc blocks of S3C2410 through S5P have a multitude of
> > quirks, i.e. moved bits or whole new registers.
> > 
> > This patch tries to describe these individual features
> > through constants which can be used to describe an adc.
> > 
> > As SoCs sometimes share only some of these quirks defining
> > TYPE_ADCVx values for each one wouldn't scale well when
> > adding more variants.
> 
> Hi Heiko,
> 
> I don't have idea we really need to use QUIRK in this case...as I know, the
> QUIRK is used on other situation...
> 
> In addition, the TYPE_ADCVx can support each Samsung SoCs' ADC...but I need
> to check again.
The current types could not support the features of the 2443 and 2416/2450 - I 
checked the datasheets.

The mux register in base+0x18 does not exist on any of the current platforms.
Also the bit 3 in ADCCON to select the resolution is specific to the 2416/2450 
(see comments above constants and quirk definitions in patches 6 and 7).

So to support these SoCs would require the definition of two new types. 
Including these new types in the existing conditionals would introduce a lot 
of statements like
	if ( (TYPE_X || TYPE_Y) && !TYPE_Z)

In my opinion testing for specific features also describes the difference 
between implementations better if one reads the code later on.


I will change the styling of the "<<"s but am wondering why checkpatch did not 
complain, i.e. it complains for all other whitespace mistakes one can make but 
not these.

Heiko

> 
> > Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> > ---
> > 
> >  arch/arm/plat-samsung/adc.c |   29 +++++++++++++++++++++++++++++
> >  1 files changed, 29 insertions(+), 0 deletions(-)
> > 
> > diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c
> > index ee8deef..b209d58 100644
> > --- a/arch/arm/plat-samsung/adc.c
> > +++ b/arch/arm/plat-samsung/adc.c
> > @@ -45,6 +45,35 @@ enum s3c_cpu_type {
> > 
> >  	TYPE_ADCV3, /* S5PV210, S5PC110, EXYNOS4210 */
> >  
> >  };
> > 
> > +/*
> > + * Resolution of the ADC - 10 or 12 bit
> > + */
> 
> /* ... */
> 
> > +#define S3C_ADC_QUIRK_10BIT		0
> > +#define S3C_ADC_QUIRK_12BIT		(1<<0)
> 
> According to coding style, should be added blank around <<.
> 
> > +
> > +/*
> > + * 12bit ADC can switch resolution between 10 bit and 12 bit
> > + * ADCCON bit 03 for S3C2416
> > + * ADCCON bit 16 for S3C64XX and up
> > + */
> > +#define S3C_ADC_QUIRK_RESSEL03		(1<<1)
> > +#define S3C_ADC_QUIRK_RESSEL16		(1<<2)
> 
> Same as above.
> 
> > +
> > +/*
> > + * Input channel select can either be in
> > + * - reg ADCCON, bit for S3C24XX and S3C64XX
> > + * - reg base+0x18 for 2443/2416/2450
> > + * - reg base+0x1C for S5P
> > + */
> > +#define S3C_ADC_QUIRK_MUXADCCON		(1<<3)
> > +#define S3C_ADC_QUIRK_MUX18		(1<<4)
> > +#define S3C_ADC_QUIRK_MUX1C		(1<<5)
> 
> Same.
> 
> > +
> > +/*
> > + * CLRINT register on S3C64xx
> > + */
> 
> /* ... */
> 
> > +#define S3C_ADC_QUIRK_CLRINT		(1<<6)
> 
> Same.
> 
> > +
> > 
> >  struct s3c_adc_client {
> >  
> >  	struct platform_device	*pdev;
> >  	struct list_head	 pend;
> > 
> > --
> > 1.7.2.3
> 
> Thanks.
> 
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.

[PATCH 2/7] s3c-adc: describe features via quirk constants

[Kukjin Kim]

Heiko St?bner wrote:
> 
> The adc blocks of S3C2410 through S5P have a multitude of
> quirks, i.e. moved bits or whole new registers.
> 
> This patch tries to describe these individual features
> through constants which can be used to describe an adc.
> 
> As SoCs sometimes share only some of these quirks defining
> TYPE_ADCVx values for each one wouldn't scale well when
> adding more variants.
> 
Hi Heiko,

I don't have idea we really need to use QUIRK in this case...as I know, the
QUIRK is used on other situation...

In addition, the TYPE_ADCVx can support each Samsung SoCs' ADC...but I need
to check again.

> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
>  arch/arm/plat-samsung/adc.c |   29 +++++++++++++++++++++++++++++
>  1 files changed, 29 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c
> index ee8deef..b209d58 100644
> --- a/arch/arm/plat-samsung/adc.c
> +++ b/arch/arm/plat-samsung/adc.c
> @@ -45,6 +45,35 @@ enum s3c_cpu_type {
>  	TYPE_ADCV3, /* S5PV210, S5PC110, EXYNOS4210 */
>  };
> 
> +/*
> + * Resolution of the ADC - 10 or 12 bit
> + */

/* ... */

> +#define S3C_ADC_QUIRK_10BIT		0
> +#define S3C_ADC_QUIRK_12BIT		(1<<0)

According to coding style, should be added blank around <<.

> +
> +/*
> + * 12bit ADC can switch resolution between 10 bit and 12 bit
> + * ADCCON bit 03 for S3C2416
> + * ADCCON bit 16 for S3C64XX and up
> + */
> +#define S3C_ADC_QUIRK_RESSEL03		(1<<1)
> +#define S3C_ADC_QUIRK_RESSEL16		(1<<2)

Same as above.

> +
> +/*
> + * Input channel select can either be in
> + * - reg ADCCON, bit for S3C24XX and S3C64XX
> + * - reg base+0x18 for 2443/2416/2450
> + * - reg base+0x1C for S5P
> + */
> +#define S3C_ADC_QUIRK_MUXADCCON		(1<<3)
> +#define S3C_ADC_QUIRK_MUX18		(1<<4)
> +#define S3C_ADC_QUIRK_MUX1C		(1<<5)

Same.

> +
> +/*
> + * CLRINT register on S3C64xx
> + */

/* ... */

> +#define S3C_ADC_QUIRK_CLRINT		(1<<6)

Same.

> +
>  struct s3c_adc_client {
>  	struct platform_device	*pdev;
>  	struct list_head	 pend;
> --
> 1.7.2.3


Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

[PATCH 2/7] s3c-adc: describe features via quirk constants

[Heiko Stübner]

The adc blocks of S3C2410 through S5P have a multitude of
quirks, i.e. moved bits or whole new registers.

This patch tries to describe these individual features
through constants which can be used to describe an adc.

As SoCs sometimes share only some of these quirks defining
TYPE_ADCVx values for each one wouldn't scale well when
adding more variants.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/arm/plat-samsung/adc.c |   29 +++++++++++++++++++++++++++++
 1 files changed, 29 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c
index ee8deef..b209d58 100644
--- a/arch/arm/plat-samsung/adc.c
+++ b/arch/arm/plat-samsung/adc.c
@@ -45,6 +45,35 @@ enum s3c_cpu_type {
 	TYPE_ADCV3, /* S5PV210, S5PC110, EXYNOS4210 */
 };
 
+/*
+ * Resolution of the ADC - 10 or 12 bit
+ */
+#define S3C_ADC_QUIRK_10BIT		0
+#define S3C_ADC_QUIRK_12BIT		(1<<0)
+
+/*
+ * 12bit ADC can switch resolution between 10 bit and 12 bit
+ * ADCCON bit 03 for S3C2416
+ * ADCCON bit 16 for S3C64XX and up
+ */
+#define S3C_ADC_QUIRK_RESSEL03		(1<<1)
+#define S3C_ADC_QUIRK_RESSEL16		(1<<2)
+
+/*
+ * Input channel select can either be in
+ * - reg ADCCON, bit for S3C24XX and S3C64XX
+ * - reg base+0x18 for 2443/2416/2450
+ * - reg base+0x1C for S5P
+ */
+#define S3C_ADC_QUIRK_MUXADCCON		(1<<3)
+#define S3C_ADC_QUIRK_MUX18		(1<<4)
+#define S3C_ADC_QUIRK_MUX1C		(1<<5)
+
+/*
+ * CLRINT register on S3C64xx
+ */
+#define S3C_ADC_QUIRK_CLRINT		(1<<6)
+
 struct s3c_adc_client {
 	struct platform_device	*pdev;
 	struct list_head	 pend;
-- 
1.7.2.3