From: linux@arm.linux.org.uk (Russell King - ARM Linux)
To: linux-arm-kernel@lists.infradead.org
Subject: some question about Set bit 22 in the PL310 (cache controller) AuxCtlr register
Date: Tue, 10 Mar 2015 16:34:12 +0000 [thread overview]
Message-ID: <20150310163411.GR8656@n2100.arm.linux.org.uk> (raw)
In-Reply-To: <20150310163133.GC13687@e104818-lin.cambridge.arm.com>
On Tue, Mar 10, 2015 at 04:31:34PM +0000, Catalin Marinas wrote:
> It's not entirely safe either. I guess the assumption is that CMA
> allocates from highmem which is not mapped in the kernel linear mapping.
> However, to be able to flush the caches for such highmem pages, they
> need to be mapped (kmap_atomic() in __dma_clear_buffer()) but there is a
> small window between dmac_flush_range() and kunmap_atomic() where
> speculative cache line fills can still happen.
That really ought to be fixed.
--
FTTC broadband for 0.8mile line: currently at 10.5Mbps down 400kbps up
according to speedtest.net.
next prev parent reply other threads:[~2015-03-10 16:34 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-08 12:31 some question about Set bit 22 in the PL310 (cache controller) AuxCtlr register vichy
2015-03-10 16:31 ` Catalin Marinas
2015-03-10 16:34 ` Russell King - ARM Linux [this message]
2015-03-10 17:40 ` Catalin Marinas
2015-03-10 17:48 ` Russell King - ARM Linux
2015-03-10 17:11 ` Krishna Reddy
2015-03-10 17:27 ` Russell King - ARM Linux
2015-03-11 14:35 ` vichy
2015-03-11 21:54 ` vichy
2015-03-13 14:11 ` Catalin Marinas
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