From: maxime.ripard@free-electrons.com (Maxime Ripard)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 3/3] mmc: sunxi: Add support to the Allwinner A83T
Date: Thu, 21 Jul 2016 10:58:38 +0200 [thread overview]
Message-ID: <20160721085838.GH5993@lukather> (raw)
In-Reply-To: <0ddc5f7d9a42515f901c95b8c0c1f5a5e4d575e9.1469082481.git.moinejf@free.fr>
Maxime
On Wed, Jul 20, 2016 at 08:28:47PM +0200, Jean-Francois Moine wrote:
> The rate of the PLL-PERIPH clock is usually set to 1.2GHz in the A83T.
Uh? The datasheet says to set it to 600MHz.
> This patch sets the phase delays of the output and sample clocks
> accordingly.
>
> Signed-off-by: Jean-Francois Moine <moinejf@free.fr>
> ---
> Note: The impacted phase delays are only for 50MHz.
> The phase delays are not used in 50MHz 8 bits DDR (new timing mode).
Actually, they seem to be, in the new timing mode register.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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next prev parent reply other threads:[~2016-07-21 8:58 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-07-21 6:28 [PATCH 0/3] mmc: sunxi: Changes in the host driver Jean-Francois Moine
2016-07-20 18:01 ` [PATCH 1/3] mmc: sunxi: Check the value returned by clk_round_rate Jean-Francois Moine
2016-07-21 8:49 ` Maxime Ripard
2016-07-20 18:16 ` [PATCH 2/3] mmc: sunxi: Set the 'New Timing' register for 8 bits DDR transfers Jean-Francois Moine
2016-07-21 8:56 ` Maxime Ripard
2016-07-21 9:26 ` Jean-Francois Moine
2016-07-29 19:17 ` Maxime Ripard
2016-07-30 5:18 ` Jean-Francois Moine
2016-07-30 10:19 ` [linux-sunxi] " Hans de Goede
2016-08-01 13:52 ` Jean-Francois Moine
2016-08-02 8:37 ` Hans de Goede
2016-07-29 19:36 ` Maxime Ripard
2016-07-30 5:20 ` Jean-Francois Moine
2016-07-20 18:28 ` [PATCH 3/3] mmc: sunxi: Add support to the Allwinner A83T Jean-Francois Moine
2016-07-21 8:58 ` Maxime Ripard [this message]
2016-07-21 9:18 ` Jean-Francois Moine
2016-07-22 19:00 ` Jean-Francois Moine
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