From: maxime.ripard@bootlin.com (Maxime Ripard)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2] drm/sun4i: Handle DRM_BUS_FLAG_PIXDATA_*EDGE
Date: Wed, 14 Mar 2018 10:37:18 +0100 [thread overview]
Message-ID: <20180314093717.glamqbj2curklztd@flea> (raw)
In-Reply-To: <1520963677-124239-1-git-send-email-giulio.benetti@micronovasrl.com>
On Tue, Mar 13, 2018 at 06:54:37PM +0100, Giulio Benetti wrote:
> Handle both positive and negative dclk polarity,
> according to bus_flags, taking care of this:
>
> On A20 and similar SoCs, the only way to achieve Positive Edge
> (Rising Edge), is setting dclk clock phase to 2/3(240?).
> By default TCON works in Negative Edge(Falling Edge), this is why phase
> is set to 0 in that case.
> Unfortunately there's no way to logically invert dclk through IO_POL
> register.
> The only acceptable way to work, triple checked with scope,
> is using clock phase set to 0? for Negative Edge and set to 240? for
> Positive Edge.
> On A33 and similar SoCs there would be a 90? phase option, but it divides
> also dclk by 2.
> This patch is a way to avoid quirks all around TCON and DOTCLOCK drivers
> for using A33 90? phase divided by 2 and consequently increase code
> complexity.
>
> Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com>
Applied, thanks!
Maxime
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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prev parent reply other threads:[~2018-03-14 9:37 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-13 17:54 [PATCH v2] drm/sun4i: Handle DRM_BUS_FLAG_PIXDATA_*EDGE Giulio Benetti
2018-03-14 9:37 ` Maxime Ripard [this message]
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