From: hch@lst.de (Christoph Hellwig)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 3/3] arm64: Force swiotlb bounce buffering for non-coherent DMA with large CWG
Date: Sat, 12 May 2018 14:38:29 +0200 [thread overview]
Message-ID: <20180512123829.GA8024@lst.de> (raw)
In-Reply-To: <20180511135547.34521-4-catalin.marinas@arm.com>
On Fri, May 11, 2018 at 02:55:47PM +0100, Catalin Marinas wrote:
> On systems with a Cache Writeback Granule (CTR_EL0.CWG) greater than
> ARCH_DMA_MINALIGN, DMA cache maintenance on sub-CWG ranges is not safe,
> leading to data corruption. If such configuration is detected, the
> kernel will force swiotlb bounce buffering for all non-coherent devices.
Per the previous discussion I understand that so far this is a
purely theoretical condition. Given that I'd rather avoid commiting
this patch and just refuse too boot in this case.
In a merge window or two I plan to have a noncoherent flag in struct
device, at which point we can handle this entirely in common code.
next prev parent reply other threads:[~2018-05-12 12:38 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-11 13:55 [PATCH v3 0/3] arm64: Revert L1_CACHE_SHIFT back to 6 (64-byte cache line size) Catalin Marinas
2018-05-11 13:55 ` [PATCH v3 1/3] Revert "arm64: Increase the max granular size" Catalin Marinas
2018-05-11 13:55 ` [PATCH v3 2/3] arm64: Increase ARCH_DMA_MINALIGN to 128 Catalin Marinas
2018-05-11 13:55 ` [PATCH v3 3/3] arm64: Force swiotlb bounce buffering for non-coherent DMA with large CWG Catalin Marinas
2018-05-12 12:38 ` Christoph Hellwig [this message]
2018-05-14 14:57 ` Catalin Marinas
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