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Tue, 4 Dec 2018 17:37:07 +0200 (EET) Date: Tue, 4 Dec 2018 17:37:07 +0200 From: Peter De Schrijver To: Joseph Lo Subject: Re: [PATCH 04/19] dt-bindings: cpufreq: tegra124: remove cpu_lp clock from required properties Message-ID: <20181204153707.GB26056@pdeschrijver-desktop.Nvidia.com> References: <20181204092548.3038-1-josephl@nvidia.com> <20181204092548.3038-5-josephl@nvidia.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20181204092548.3038-5-josephl@nvidia.com> X-NVConfidentiality: public User-Agent: Mutt/1.9.4 (2018-02-28) X-Originating-IP: [10.124.1.5] X-ClientProxiedBy: HQMAIL108.nvidia.com (172.18.146.13) To HQMAIL101.nvidia.com (172.20.187.10) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1543937831; bh=suxuU4hx+hDKXy/SxFoGVMGYMNWY+N/hdV6JEtOX8BI=; h=X-PGP-Universal:Date:From:To:CC:Subject:Message-ID:References: MIME-Version:Content-Type:Content-Disposition:In-Reply-To: X-NVConfidentiality:User-Agent:X-Originating-IP:X-ClientProxiedBy; b=dgJ3trRpD8vzFwueidDl2AKZRnXZ7l8M5EHLbp+YHPoPrRycsdXG8XvlnCxlDgjS9 xLZYZfe/bhWvQsTOWELrrwitvvVXmYjAsFW24HQR3jMfT9rSqjlW8FcOFnxGJkPwgJ Es0MXls+DJpDmEHW0XOirF6km6xsFM0iNdq85ZpGfZdALCIlp5Ebrd4p0MniexnJD5 Pc2VvCml+yJ15Jp82jyLqAfNQ41EuLTtSmG/KKe/fiWZgogISneCRAQP1SLxzMswH6 3PhVP/oFF65UkEIMVFUqeBd8ep+69EjyCj9gaOEeFuXk1n3/wgYQEHTTITO+XCpqMW Aem9tzS3ZR74g== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181204_073720_540651_FA61B259 X-CRM114-Status: GOOD ( 15.60 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Jonathan Hunter , Thierry Reding , linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Dec 04, 2018 at 05:25:33PM +0800, Joseph Lo wrote: > The cpu_lp clock property is only needed when the CPUfreq driver > supports CPU cluster switching. But it was not a design for this driver > and it didn't handle that as well. So removing this property. > I would mark it optional. This means current DTs will still be technically compatible with this binding doc. Peter. > Cc: devicetree@vger.kernel.org > Signed-off-by: Joseph Lo > --- > .../devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt | 4 +--- > 1 file changed, 1 insertion(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt > index 031545a29caf..03196d5ea515 100644 > --- a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt > +++ b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt > @@ -9,7 +9,6 @@ Required properties: > See ../clocks/clock-bindings.txt for details. > - clock-names: Must include the following entries: > - cpu_g: Clock mux for the fast CPU cluster. > - - cpu_lp: Clock mux for the low-power CPU cluster. > - pll_x: Fast PLL clocksource. > - pll_p: Auxiliary PLL used during fast PLL rate changes. > - dfll: Fast DFLL clocksource that also automatically scales CPU voltage. > @@ -30,11 +29,10 @@ cpus { > reg = <0>; > > clocks = <&tegra_car TEGRA124_CLK_CCLK_G>, > - <&tegra_car TEGRA124_CLK_CCLK_LP>, > <&tegra_car TEGRA124_CLK_PLL_X>, > <&tegra_car TEGRA124_CLK_PLL_P>, > <&dfll>; > - clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; > + clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; > clock-latency = <300000>; > }; > > -- > 2.19.2 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel