From: Patrick Havelange <patrick.havelange@essensium.com>
To: Shawn Guo <shawnguo@kernel.org>, Li Yang <leoyang.li@nxp.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Borislav Petkov <bp@alien8.de>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
linux-edac@vger.kernel.org
Cc: matthew.weber@rockwellcollins.com,
patrick.havelange@essensium.com,
arnout.vandecappelle@essensium.com
Subject: [PATCH] ARM: dts: ls1021a: Add memory controller
Date: Tue, 11 Dec 2018 16:48:34 +0100 [thread overview]
Message-ID: <20181211154834.4489-1-patrick.havelange@essensium.com> (raw)
The LS1021A has a memory controller that supports EDAC. This commit
adds an entry for it.
Signed-off-by: Patrick Havelange <patrick.havelange@essensium.com>
---
arch/arm/boot/dts/ls1021a.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index bdd6e66a79ad..a877c32bff20 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -125,6 +125,13 @@
interrupt-parent = <&gic>;
ranges;
+ ddr: memory-controller@1080000 {
+ compatible = "fsl,qoriq-memory-controller";
+ reg = <0x0 0x1080000 0x0 0x1000>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ big-endian;
+ };
+
gic: interrupt-controller@1400000 {
compatible = "arm,gic-400", "arm,cortex-a7-gic";
#interrupt-cells = <3>;
--
2.17.1
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next reply other threads:[~2018-12-11 15:49 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-11 15:48 Patrick Havelange [this message]
2019-01-10 7:03 ` [PATCH] ARM: dts: ls1021a: Add memory controller Shawn Guo
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