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* [PATCH 1/6] ARM: dts: imx21: add i.MX21 SoC device tree
@ 2018-12-22 10:51 Alexander Shiyan
  2018-12-22 10:51 ` [PATCH 2/6] ARM i.MX21: Add devicetree support Alexander Shiyan
                   ` (4 more replies)
  0 siblings, 5 replies; 9+ messages in thread
From: Alexander Shiyan @ 2018-12-22 10:51 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Alexander Shiyan, Russell King, NXP Linux Team,
	Pengutronix Kernel Team, Fabio Estevam, Shawn Guo

It adds initial device tree support for Freescale i.MX21 SoC.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
 arch/arm/boot/dts/imx21-pinfunc.h | 441 ++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/imx21.dtsi      | 465 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 906 insertions(+)
 create mode 100644 arch/arm/boot/dts/imx21-pinfunc.h
 create mode 100644 arch/arm/boot/dts/imx21.dtsi

diff --git a/arch/arm/boot/dts/imx21-pinfunc.h b/arch/arm/boot/dts/imx21-pinfunc.h
new file mode 100644
index 0000000..6787b23
--- /dev/null
+++ b/arch/arm/boot/dts/imx21-pinfunc.h
@@ -0,0 +1,441 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/* Author: Alexander Shiyan <shc_work@mail.ru> */
+
+#ifndef __DTS_IMX21_PINFUNC_H
+#define __DTS_IMX21_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <pin mux_id>
+ * mux_id consists of
+ * function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10)
+ *
+ * function:      0 - Primary function
+ *                1 - Alternate function
+ *                2 - GPIO
+ * direction:     0 - Input
+ *                1 - Output
+ * gpio_oconf:    0 - A_IN
+ *                1 - B_IN
+ *                2 - C_IN
+ *                3 - Data Register
+ * gpio_iconfa/b: 0 - GPIO_IN
+ *                1 - Interrupt Status Register
+ *                2 - 0
+ *                3 - 1
+ *
+ * 'pin' is an integer between 5 and 0xb6. i.MX21 has 6 ports with 32 configurable
+ * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is the pin
+ * number on the specific port (between 0 and 31).
+ */
+
+#define MX21_PAD_LSCLK__LSCLK			0x05 0x004
+#define MX21_PAD_LSCLK__BMI_CLK_CS		0x05 0x001
+#define MX21_PAD_LSCLK__GPIO1_5			0x05 0x032
+#define MX21_PAD_LD0__LD0			0x06 0x004
+#define MX21_PAD_LD0__BMI_D0			0x06 0x001
+#define MX21_PAD_LD0__GPIO1_6			0x06 0x032
+#define MX21_PAD_LD0__SLCDC1_DAT0		0x06 0x006
+#define MX21_PAD_LD1__LD1			0x07 0x004
+#define MX21_PAD_LD1__BMI_D1			0x07 0x001
+#define MX21_PAD_LD1__GPIO1_7			0x07 0x032
+#define MX21_PAD_LD1__SLCDC1_DAT1		0x07 0x006
+#define MX21_PAD_LD2__LD2			0x08 0x004
+#define MX21_PAD_LD2__BMI_D2			0x08 0x001
+#define MX21_PAD_LD2__GPIO1_8			0x08 0x032
+#define MX21_PAD_LD2__SLCDC1_DAT2		0x08 0x006
+#define MX21_PAD_LD3__LD3			0x09 0x004
+#define MX21_PAD_LD3__BMI_D3			0x09 0x001
+#define MX21_PAD_LD3__GPIO1_9			0x09 0x032
+#define MX21_PAD_LD3__SLCDC1_DAT3		0x09 0x006
+#define MX21_PAD_LD4__LD4			0x0a 0x004
+#define MX21_PAD_LD4__BMI_D4			0x0a 0x001
+#define MX21_PAD_LD4__GPIO1_10			0x0a 0x032
+#define MX21_PAD_LD4__SLCDC1_DAT4		0x0a 0x006
+#define MX21_PAD_LD5__LD5			0x0b 0x004
+#define MX21_PAD_LD5__BMI_D5			0x0b 0x001
+#define MX21_PAD_LD5__GPIO1_11			0x0b 0x032
+#define MX21_PAD_LD5__SLCDC1_DAT5		0x0b 0x006
+#define MX21_PAD_LD6__LD6			0x0c 0x004
+#define MX21_PAD_LD6__BMI_D6			0x0c 0x001
+#define MX21_PAD_LD6__GPIO1_12			0x0c 0x032
+#define MX21_PAD_LD6__SLCDC1_DAT6		0x0c 0x006
+#define MX21_PAD_LD7__LD7			0x0d 0x004
+#define MX21_PAD_LD7__BMI_D7			0x0d 0x001
+#define MX21_PAD_LD7__GPIO1_13			0x0d 0x032
+#define MX21_PAD_LD7__SLCDC1_DAT7		0x0d 0x006
+#define MX21_PAD_LD8__LD8			0x0e 0x004
+#define MX21_PAD_LD8__BMI_D8			0x0e 0x001
+#define MX21_PAD_LD8__GPIO1_14			0x0e 0x032
+#define MX21_PAD_LD8__SLCDC1_DAT8		0x0e 0x006
+#define MX21_PAD_LD8__SLCDC1_DAT0		0x0e 0x026
+#define MX21_PAD_LD9__LD9			0x0f 0x004
+#define MX21_PAD_LD9__BMI_D9			0x0f 0x001
+#define MX21_PAD_LD9__GPIO1_15			0x0f 0x032
+#define MX21_PAD_LD9__SLCDC1_DAT9		0x0f 0x006
+#define MX21_PAD_LD9__SLCDC1_DAT1		0x0f 0x026
+#define MX21_PAD_LD10__LD10			0x10 0x004
+#define MX21_PAD_LD10__BMI_D10			0x10 0x001
+#define MX21_PAD_LD10__GPIO1_16			0x10 0x032
+#define MX21_PAD_LD10__SLCDC1_DAT10		0x10 0x006
+#define MX21_PAD_LD10__SLCDC1_DAT2		0x10 0x026
+#define MX21_PAD_LD11__LD11			0x11 0x004
+#define MX21_PAD_LD11__BMI_D11			0x11 0x001
+#define MX21_PAD_LD11__GPIO1_17			0x11 0x032
+#define MX21_PAD_LD11__SLCDC1_DAT11		0x11 0x006
+#define MX21_PAD_LD11__SLCDC1_DAT3		0x11 0x026
+#define MX21_PAD_LD12__LD12			0x12 0x004
+#define MX21_PAD_LD12__BMI_D12			0x12 0x001
+#define MX21_PAD_LD12__GPIO1_18			0x12 0x032
+#define MX21_PAD_LD12__SLCDC1_DAT12		0x12 0x006
+#define MX21_PAD_LD12__SLCDC1_DAT4		0x12 0x026
+#define MX21_PAD_LD13__LD13			0x13 0x004
+#define MX21_PAD_LD13__BMI_D13			0x13 0x001
+#define MX21_PAD_LD13__GPIO1_19			0x13 0x032
+#define MX21_PAD_LD13__SLCDC1_DAT13		0x13 0x006
+#define MX21_PAD_LD13__SLCDC1_DAT5		0x13 0x026
+#define MX21_PAD_LD14__LD14			0x14 0x004
+#define MX21_PAD_LD14__BMI_D14			0x14 0x001
+#define MX21_PAD_LD14__GPIO1_20			0x14 0x032
+#define MX21_PAD_LD14__SLCDC1_DAT14		0x14 0x006
+#define MX21_PAD_LD14__SLCDC1_DAT6		0x14 0x026
+#define MX21_PAD_LD15__LD15			0x15 0x004
+#define MX21_PAD_LD15__BMI_D15			0x15 0x001
+#define MX21_PAD_LD15__GPIO1_21			0x15 0x032
+#define MX21_PAD_LD15__SLCDC1_DAT15		0x15 0x006
+#define MX21_PAD_LD15__SLCDC1_DAT7		0x15 0x026
+#define MX21_PAD_LD16__LD16			0x16 0x004
+#define MX21_PAD_LD16__BMI_READ_REQ		0x16 0x005
+#define MX21_PAD_LD16__GPIO1_22			0x16 0x032
+#define MX21_PAD_LD15__EXT_DMAGRANT		0x16 0x006
+#define MX21_PAD_LD17__LD17			0x17 0x004
+#define MX21_PAD_LD17__BMI_WRITE		0x17 0x001
+#define MX21_PAD_LD17__GPIO1_23			0x17 0x032
+#define MX21_PAD_REV__REV			0x18 0x004
+#define MX21_PAD_REV__GPIO1_24			0x18 0x032
+#define MX21_PAD_REV__SLCDC1_D0			0x18 0x006
+#define MX21_PAD_CLS__CLS			0x19 0x004
+#define MX21_PAD_CLS__GPIO1_25			0x19 0x032
+#define MX21_PAD_CLS__SLCDC1_RS			0x19 0x006
+#define MX21_PAD_PS__PS				0x1a 0x004
+#define MX21_PAD_PS__GPIO1_26			0x1a 0x032
+#define MX21_PAD_PS__SLCDC1_CS			0x1a 0x006
+#define MX21_PAD_SPL_SPR__SPL_SPR		0x1b 0x004
+#define MX21_PAD_SPL_SPR__GPIO1_27		0x1b 0x032
+#define MX21_PAD_SPL_SPR__SLCDC1_CLK		0x1b 0x006
+#define MX21_PAD_HSYNC__HSYNC			0x1c 0x004
+#define MX21_PAD_HSYNC__GPIO1_28		0x1c 0x032
+#define MX21_PAD_VSYNC__VSYNC			0x1d 0x004
+#define MX21_PAD_VSYNC__BMI_RXF_FULL		0x1d 0x005
+#define MX21_PAD_VSYNC__GPIO1_29		0x1d 0x032
+#define MX21_PAD_VSYNC__BMI_WAIT		0x1d 0x002
+#define MX21_PAD_CONTRAST__CONTRAST		0x1e 0x004
+#define MX21_PAD_CONTRAST__BMI_READ		0x1e 0x005
+#define MX21_PAD_CONTRAST__GPIO1_30		0x1e 0x032
+#define MX21_PAD_OE_ACD__OE_ACD			0x1f 0x004
+#define MX21_PAD_OE_ACD__GPIO1_31		0x1f 0x032
+#define MX21_PAD_SD2_D0__SD2_D0			0x24 0x000
+#define MX21_PAD_SD2_D0__GPIO2_4		0x24 0x032
+#define MX21_PAD_SD2_D1__SD2_D1			0x25 0x000
+#define MX21_PAD_SD2_D1__GPIO2_5		0x25 0x032
+#define MX21_PAD_SD2_D2__SD2_D2			0x26 0x000
+#define MX21_PAD_SD2_D2__GPIO2_6		0x26 0x032
+#define MX21_PAD_SD2_D2__SLCDC1_D0		0x26 0x006
+#define MX21_PAD_SD2_D3__SD2_D3			0x27 0x000
+#define MX21_PAD_SD2_D3__GPIO2_7		0x27 0x032
+#define MX21_PAD_SD2_D3__SLCDC1_RS		0x27 0x006
+#define MX21_PAD_SD2_CMD__SD2_CMD		0x28 0x000
+#define MX21_PAD_SD2_CMD__GPIO2_8		0x28 0x032
+#define MX21_PAD_SD2_CMD__SLCDC1_CS		0x28 0x006
+#define MX21_PAD_SD2_CLK__SD2_CLK		0x29 0x004
+#define MX21_PAD_SD2_CLK__GPIO2_9		0x29 0x032
+#define MX21_PAD_SD2_CLK__SLCDC1_CLK		0x29 0x006
+#define MX21_PAD_CSI_D0__CSI_D0			0x2a 0x000
+#define MX21_PAD_CSI_D0__GPIO2_10		0x2a 0x032
+#define MX21_PAD_CSI_D1__CSI_D1			0x2b 0x000
+#define MX21_PAD_CSI_D1__GPIO2_11		0x2b 0x032
+#define MX21_PAD_CSI_D2__CSI_D2			0x2c 0x000
+#define MX21_PAD_CSI_D2__GPIO2_12		0x2c 0x032
+#define MX21_PAD_CSI_D3__CSI_D3			0x2d 0x000
+#define MX21_PAD_CSI_D3__GPIO2_13		0x2d 0x032
+#define MX21_PAD_CSI_D4__CSI_D4			0x2e 0x000
+#define MX21_PAD_CSI_D4__GPIO2_14		0x2e 0x032
+#define MX21_PAD_CSI_MCLK__CSI_MCLK		0x2f 0x004
+#define MX21_PAD_CSI_MCLK__GPIO2_15		0x2f 0x032
+#define MX21_PAD_CSI_PIXCLK__CSI_PIXCLK		0x30 0x000
+#define MX21_PAD_CSI_PIXCLK__GPIO2_16		0x30 0x032
+#define MX21_PAD_CSI_D5__CSI_D5			0x31 0x000
+#define MX21_PAD_CSI_D5__GPIO2_17		0x31 0x032
+#define MX21_PAD_CSI_D6__CSI_D6			0x32 0x000
+#define MX21_PAD_CSI_D6__GPIO2_18		0x32 0x032
+#define MX21_PAD_CSI_D7__CSI_D7			0x33 0x000
+#define MX21_PAD_CSI_D7__GPIO2_19		0x33 0x032
+#define MX21_PAD_CSI_VSYNC__CSI_VSYNC		0x34 0x000
+#define MX21_PAD_CSI_VSYNC__GPIO2_20		0x34 0x032
+#define MX21_PAD_CSI_HSYNC__CSI_HSYNC		0x35 0x000
+#define MX21_PAD_CSI_HSYNC__GPIO2_21		0x35 0x032
+#define MX21_PAD_USB_BYP__USB_BYP		0x36 0x000
+#define MX21_PAD_USB_BYP__GPIO2_22		0x36 0x032
+#define MX21_PAD_USB_PWR__USB_PWR		0x37 0x004
+#define MX21_PAD_USB_PWR__GPIO2_23		0x37 0x032
+#define MX21_PAD_USB_OC__USB_OC			0x38 0x000
+#define MX21_PAD_USB_OC__GPIO2_24		0x38 0x032
+#define MX21_PAD_USBH_ON__USBH_ON		0x39 0x004
+#define MX21_PAD_USBH_ON__GPIO2_25		0x39 0x032
+#define MX21_PAD_USBH_ON__SLCDC1_DAT0		0x39 0x006
+#define MX21_PAD_USBH1_FS__USBH1_FS		0x3a 0x004
+#define MX21_PAD_USBH1_FS__UART4_RTS		0x3a 0x001
+#define MX21_PAD_USBH1_FS__GPIO2_26		0x3a 0x032
+#define MX21_PAD_USBH1_FS__SLCDC1_DAT1		0x3a 0x006
+#define MX21_PAD_USBH1_FS__USBH1_RXDAT		0x3a 0x026
+#define MX21_PAD_USBH1_OE__USBH1_OE		0x3b 0x000
+#define MX21_PAD_USBH1_OE__GPIO2_27		0x3b 0x032
+#define MX21_PAD_USBH1_OE__SLCDC1_DAT2		0x3b 0x006
+#define MX21_PAD_USBH1_TXDM__USBH1_TXDM		0x3c 0x004
+#define MX21_PAD_USBH1_TXDM__UART4_TXD		0x3c 0x005
+#define MX21_PAD_USBH1_TXDM__GPIO2_28		0x3c 0x032
+#define MX21_PAD_USBH1_TXDM__SLCDC1_DAT3	0x3c 0x006
+#define MX21_PAD_USBH1_TXDP__USBH1_TXDP		0x3d 0x004
+#define MX21_PAD_USBH1_TXDP__UART4_CTS		0x3d 0x005
+#define MX21_PAD_USBH1_TXDP__GPIO2_29		0x3d 0x032
+#define MX21_PAD_USBH1_TXDP__SLCDC1_DAT4	0x3d 0x006
+#define MX21_PAD_USBH1_TXDP__UART4_RXD		0x3d 0x002
+#define MX21_PAD_USBH1_RXDM__USBH1_RXDM		0x3e 0x000
+#define MX21_PAD_USBH1_RXDM__GPIO2_30		0x3e 0x032
+#define MX21_PAD_USBH1_RXDM__SLCDC1_DAT5	0x3e 0x006
+#define MX21_PAD_USBH1_RXDM__UART4_CTS		0x3e 0x026
+#define MX21_PAD_USBH1_RXDP__USBH1_RXDP		0x3f 0x000
+#define MX21_PAD_USBH1_RXDP__UART4_RXD		0x3f 0x001
+#define MX21_PAD_USBH1_RXDP__GPIO2_31		0x3f 0x032
+#define MX21_PAD_USBH1_RXDP__SLCDC1_DAT6	0x3f 0x006
+#define MX21_PAD_USBH1_RXDP__UART4_RTS		0x3f 0x002
+#define MX21_PAD_USBG_SDA__USBG_SDA		0x45 0x000
+#define MX21_PAD_USBG_SDA__GPIO3_5		0x45 0x032
+#define MX21_PAD_USBG_SDA__SLCDC1_DAT7		0x45 0x006
+#define MX21_PAD_USBG_SCL__USBG_SCL		0x46 0x000
+#define MX21_PAD_USBG_SCL__GPIO3_6		0x46 0x032
+#define MX21_PAD_USBG_SCL__SLCDC1_DAT8		0x46 0x006
+#define MX21_PAD_USBG_ON__USBG_ON		0x47 0x004
+#define MX21_PAD_USBG_ON__GPIO3_7		0x47 0x032
+#define MX21_PAD_USBG_ON__SLCDC1_DAT9		0x47 0x006
+#define MX21_PAD_USBG_FS__USBG_FS		0x48 0x004
+#define MX21_PAD_USBG_FS__GPIO3_8		0x48 0x032
+#define MX21_PAD_USBG_FS__SLCDC1_DAT10		0x48 0x006
+#define MX21_PAD_USBG_FS__USBBG_TXR_INT		0x48 0x002
+#define MX21_PAD_USBG_OE__USBG_OE		0x49 0x004
+#define MX21_PAD_USBG_OE__GPIO3_9		0x49 0x032
+#define MX21_PAD_USBG_OE__SLCDC1_DAT11		0x49 0x006
+#define MX21_PAD_USBG_TXDM__USBG_TXDM		0x4a 0x004
+#define MX21_PAD_USBG_TXDM__GPIO3_10		0x4a 0x032
+#define MX21_PAD_USBG_TXDM__SLCDC1_DAT12	0x4a 0x006
+#define MX21_PAD_USBG_TXDP__USBG_TXDP		0x4b 0x004
+#define MX21_PAD_USBG_TXDP__GPIO3_11		0x4b 0x032
+#define MX21_PAD_USBG_TXDP__SLCDC1_DAT13	0x4b 0x006
+#define MX21_PAD_USBG_RXDM__USBG_RXDM		0x4c 0x000
+#define MX21_PAD_USBG_RXDM__GPIO3_12		0x4c 0x032
+#define MX21_PAD_USBG_RXDM__SLCDC1_DAT14	0x4c 0x006
+#define MX21_PAD_USBG_RXDP__USBG_RXDP		0x4d 0x000
+#define MX21_PAD_USBG_RXDP__GPIO3_13		0x4d 0x032
+#define MX21_PAD_USBG_RXDP__SLCDC1_DAT15	0x4d 0x006
+#define MX21_PAD_TOUT__TOUT			0x4e 0x004
+#define MX21_PAD_TOUT__GPIO3_14			0x4e 0x032
+#define MX21_PAD_TOUT__SYS_CLK			0x4e 0x006
+#define MX21_PAD_TIN__TIN			0x4f 0x000
+#define MX21_PAD_TIN__GPIO3_15			0x4f 0x032
+#define MX21_PAD_TIN__WKGD			0x4f 0x002
+#define MX21_PAD_SAP_FS__SAP_FS			0x50 0x000
+#define MX21_PAD_SAP_FS__GPIO3_16		0x50 0x032
+#define MX21_PAD_SAP_RXD__SAP_RXD		0x51 0x000
+#define MX21_PAD_SAP_RXD__GPIO3_17		0x51 0x032
+#define MX21_PAD_SAP_TXD__SAP_TXD		0x52 0x000
+#define MX21_PAD_SAP_TXD__GPIO3_18		0x52 0x032
+#define MX21_PAD_SAP_CLK__SAP_CLK		0x53 0x000
+#define MX21_PAD_SAP_CLK__GPIO3_19		0x53 0x032
+#define MX21_PAD_SSI1_FS__SSI1_FS		0x54 0x000
+#define MX21_PAD_SSI1_FS__GPIO3_20		0x54 0x032
+#define MX21_PAD_SSI1_RXD__SSI1_RXD		0x55 0x000
+#define MX21_PAD_SSI1_RXD__GPIO3_21		0x55 0x032
+#define MX21_PAD_SSI1_TXD__SSI1_TXD		0x56 0x000
+#define MX21_PAD_SSI1_TXD__GPIO3_22		0x56 0x032
+#define MX21_PAD_SSI1_CLK__SSI1_CLK		0x57 0x000
+#define MX21_PAD_SSI1_CLK__GPIO3_23		0x57 0x032
+#define MX21_PAD_SSI2_FS__SSI2_FS		0x58 0x000
+#define MX21_PAD_SSI2_FS__GPIO3_24		0x58 0x032
+#define MX21_PAD_SSI2_RXD__SSI2_RXD		0x59 0x000
+#define MX21_PAD_SSI2_RXD__GPIO3_25		0x59 0x032
+#define MX21_PAD_SSI2_TXD__SSI2_TXD		0x5a 0x000
+#define MX21_PAD_SSI2_TXD__GPIO3_26		0x5a 0x032
+#define MX21_PAD_SSI2_CLK__SSI2_CLK		0x5b 0x000
+#define MX21_PAD_SSI2_CLK__GPIO3_27		0x5b 0x032
+#define MX21_PAD_SSI3_FS__SSI3_FS		0x5c 0x000
+#define MX21_PAD_SSI3_FS__SLCDC2_D0		0x5c 0x001
+#define MX21_PAD_SSI3_FS__GPIO3_28		0x5c 0x032
+#define MX21_PAD_SSI3_RXD__SSI3_RXD		0x5d 0x000
+#define MX21_PAD_SSI3_RXD__SLCDC2_RS		0x5d 0x001
+#define MX21_PAD_SSI3_RXD__GPIO3_29		0x5d 0x032
+#define MX21_PAD_SSI3_TXD__SSI3_TXD		0x5e 0x000
+#define MX21_PAD_SSI3_TXD__SLCDC2_CS		0x5e 0x001
+#define MX21_PAD_SSI3_TXD__GPIO3_30		0x5e 0x032
+#define MX21_PAD_SSI3_CLK__SSI3_CLK		0x5f 0x000
+#define MX21_PAD_SSI3_CLK__SLCDC2_CLK		0x5f 0x001
+#define MX21_PAD_SSI3_CLK__GPIO3_31		0x5f 0x032
+#define MX21_PAD_I2C_DATA__I2C_DATA		0x71 0x000
+#define MX21_PAD_I2C_DATA__GPIO4_17		0x71 0x032
+#define MX21_PAD_I2C_CLK__I2C_CLK		0x72 0x000
+#define MX21_PAD_I2C_CLK__GPIO4_18		0x72 0x032
+#define MX21_PAD_CSPI2_SS2__CSPI2_SS2		0x73 0x000
+#define MX21_PAD_CSPI2_SS2__GPIO4_19		0x73 0x032
+#define MX21_PAD_CSPI2_SS2__USBH2_RXDM		0x73 0x002
+#define MX21_PAD_CSPI2_SS1__CSPI2_SS1		0x74 0x000
+#define MX21_PAD_CSPI2_SS1__GPIO4_20		0x74 0x032
+#define MX21_PAD_CSPI2_SS1__USBH2_RXDP		0x74 0x002
+#define MX21_PAD_CSPI2_SS0__CSPI2_SS0		0x75 0x000
+#define MX21_PAD_CSPI2_SS0__USBH2_FS		0x75 0x006
+#define MX21_PAD_CSPI2_SS0__GPIO4_21		0x75 0x032
+#define MX21_PAD_CSPI2_SCLK__CSPI2_SCLK		0x76 0x000
+#define MX21_PAD_CSPI2_SCLK__USBH2_OE		0x76 0x006
+#define MX21_PAD_CSPI2_SCLK__GPIO4_22		0x76 0x032
+#define MX21_PAD_CSPI2_MISO__CSPI2_MISO		0x77 0x000
+#define MX21_PAD_CSPI2_MISO__GPIO4_23		0x77 0x032
+#define MX21_PAD_CSPI2_MISO__USBH2_TXDM		0x77 0x006
+#define MX21_PAD_CSPI2_MOSI__CSPI2_MOSI		0x78 0x000
+#define MX21_PAD_CSPI2_MOSI__GPIO4_24		0x78 0x032
+#define MX21_PAD_CSPI2_MOSI__USBH2_TXDP		0x78 0x006
+#define MX21_PAD_CSPI1_RDY__CSPI1_RDY		0x79 0x000
+#define MX21_PAD_CSPI1_RDY__GPIO4_25		0x79 0x032
+#define MX21_PAD_CSPI1_RDY__EXT_DMAREQ		0x79 0x002
+#define MX21_PAD_CSPI1_SS2__CSPI1_SS2		0x7a 0x000
+#define MX21_PAD_CSPI1_SS2__GPIO4_26		0x7a 0x032
+#define MX21_PAD_CSPI1_SS2__USBG_RXDAT		0x7a 0x002
+#define MX21_PAD_CSPI1_SS1__CSPI1_SS1		0x7b 0x000
+#define MX21_PAD_CSPI1_SS1__GPIO4_27		0x7b 0x032
+#define MX21_PAD_CSPI1_SS1__EXT_DMA_GRANT	0x7b 0x016
+#define MX21_PAD_CSPI1_SS0__CSPI1_SS0		0x7c 0x000
+#define MX21_PAD_CSPI1_SS0__GPIO4_28		0x7c 0x032
+#define MX21_PAD_CSPI1_SCLK__CSPI1_SCLK		0x7d 0x000
+#define MX21_PAD_CSPI1_SCLK__GPIO4_29		0x7d 0x032
+#define MX21_PAD_CSPI1_MISO__CSPI1_MISO		0x7e 0x000
+#define MX21_PAD_CSPI1_MISO__GPIO4_30		0x7e 0x032
+#define MX21_PAD_CSPI1_MOSI__CSPI1_MOSI		0x7f 0x000
+#define MX21_PAD_CSPI1_MOSI__GPIO4_31		0x7f 0x032
+#define MX21_PAD_TEST_WB2__TEST_WB2		0x80 0x000
+#define MX21_PAD_TEST_WB2__KP_COL6		0x80 0x001
+#define MX21_PAD_TEST_WB2__GPIO5_0		0x80 0x032
+#define MX21_PAD_TEST_WB1__TEST_WB1		0x81 0x000
+#define MX21_PAD_TEST_WB1__KP_ROW6		0x81 0x001
+#define MX21_PAD_TEST_WB1__GPIO5_1		0x81 0x032
+#define MX21_PAD_TEST_WB0__TEST_WB0		0x82 0x000
+#define MX21_PAD_TEST_WB0__KP_ROW7		0x82 0x001
+#define MX21_PAD_TEST_WB0__GPIO5_2		0x82 0x032
+#define MX21_PAD_UART2_CTS__UART2_CTS		0x83 0x004
+#define MX21_PAD_UART2_CTS__KP_COL7		0x83 0x001
+#define MX21_PAD_UART2_CTS__GPIO5_3		0x83 0x032
+#define MX21_PAD_UART2_RTS__UART2_RTS		0x84 0x000
+#define MX21_PAD_UART2_RTS__KP_ROW7		0x84 0x001
+#define MX21_PAD_UART2_RTS__GPIO5_4		0x84 0x032
+#define MX21_PAD_PWMO__PWMO			0x85 0x004
+#define MX21_PAD_PWMO__GPIO5_5			0x85 0x032
+#define MX21_PAD_PWMO__PC_SPKOUT		0x85 0x006
+#define MX21_PAD_PWMO__TOUT2			0x85 0x016
+#define MX21_PAD_PWMO__TOUT3			0x85 0x026
+#define MX21_PAD_UART2_TXD__UART2_TXD		0x86 0x004
+#define MX21_PAD_UART2_TXD__KP_COL6		0x86 0x001
+#define MX21_PAD_UART2_TXD__GPIO5_6		0x86 0x032
+#define MX21_PAD_UART2_RXD__UART2_RXD		0x87 0x000
+#define MX21_PAD_UART2_RXD__KP_ROW6		0x87 0x001
+#define MX21_PAD_UART2_RXD__GPIO5_7		0x87 0x032
+#define MX21_PAD_UART3_TXD__UART3_TXD		0x88 0x004
+#define MX21_PAD_UART3_TXD__GPIO5_8		0x88 0x032
+#define MX21_PAD_UART3_TXD__IR_TXD		0x88 0x006
+#define MX21_PAD_UART3_RXD__UART3_RXD		0x89 0x000
+#define MX21_PAD_UART3_RXD__GPIO5_9		0x89 0x032
+#define MX21_PAD_UART3_RXD__IR_RXD		0x89 0x002
+#define MX21_PAD_UART3_CTS__UART3_CTS		0x8a 0x004
+#define MX21_PAD_UART3_CTS__GPIO5_10		0x8a 0x032
+#define MX21_PAD_UART3_RTS__UART3_RTS		0x8b 0x000
+#define MX21_PAD_UART3_RTS__GPIO5_11		0x8b 0x032
+#define MX21_PAD_UART1_TXD__UART1_TXD		0x8c 0x004
+#define MX21_PAD_UART1_TXD__GPIO5_12		0x8c 0x032
+#define MX21_PAD_UART1_RXD__UART1_RXD		0x8d 0x000
+#define MX21_PAD_UART1_RXD__GPIO5_13		0x8d 0x032
+#define MX21_PAD_UART1_CTS__UART1_CTS		0x8e 0x004
+#define MX21_PAD_UART1_CTS__GPIO5_14		0x8e 0x032
+#define MX21_PAD_UART1_RTS__UART1_RTS		0x8f 0x000
+#define MX21_PAD_UART1_RTS__GPIO5_15		0x8f 0x032
+#define MX21_PAD_RTCK__RTCK			0x90 0x004
+#define MX21_PAD_RTCK__OWIRE			0x90 0x001
+#define MX21_PAD_RTCK__GPIO5_16			0x90 0x032
+#define MX21_PAD_RESET_OUT__RESET_OUT		0x91 0x004
+#define MX21_PAD_RESET_OUT__GPIO5_17		0x91 0x032
+#define MX21_PAD_SD1_D0__SD1_D0			0x92 0x000
+#define MX21_PAD_SD1_D0__CSPI3_MISO		0x92 0x001
+#define MX21_PAD_SD1_D0__GPIO5_18		0x92 0x032
+#define MX21_PAD_SD1_D1__SD1_D1			0x93 0x000
+#define MX21_PAD_SD1_D1__GPIO5_19		0x93 0x032
+#define MX21_PAD_SD1_D2__SD1_D2			0x94 0x000
+#define MX21_PAD_SD1_D2__GPIO5_20		0x94 0x032
+#define MX21_PAD_SD1_D3__SD1_D3			0x95 0x000
+#define MX21_PAD_SD1_D3__CSPI3_SS		0x95 0x005
+#define MX21_PAD_SD1_D3__GPIO5_21		0x95 0x032
+#define MX21_PAD_SD1_CMD__SD1_CMD		0x96 0x000
+#define MX21_PAD_SD1_CMD__CSPI3_MOSI		0x96 0x005
+#define MX21_PAD_SD1_CMD__GPIO5_22		0x96 0x032
+#define MX21_PAD_SD1_CLK__SD1_CLK		0x97 0x004
+#define MX21_PAD_SD1_CLK__CSPI3_SCLK		0x97 0x005
+#define MX21_PAD_SD1_CLK__GPIO5_23		0x97 0x032
+#define MX21_PAD_NFRB__NFRB			0xa0 0x000
+#define MX21_PAD_NFRB__GPIO6_0			0xa0 0x032
+#define MX21_PAD_NFRB__PC_RST			0xa0 0x006
+#define MX21_PAD_NFCE__NFCE			0xa1 0x004
+#define MX21_PAD_NFCE__GPIO6_1			0xa1 0x032
+#define MX21_PAD_NFCE__PC_CE1			0xa1 0x006
+#define MX21_PAD_NFWP__NFWP			0xa2 0x004
+#define MX21_PAD_NFWP__GPIO6_2			0xa2 0x032
+#define MX21_PAD_NFWP__PC_CE2			0xa2 0x006
+#define MX21_PAD_NFCLE__NFCLE			0xa3 0x004
+#define MX21_PAD_NFCLE__GPIO6_3			0xa3 0x032
+#define MX21_PAD_NFCLE__PC_POE			0xa3 0x006
+#define MX21_PAD_NFALE__NFALE			0xa4 0x004
+#define MX21_PAD_NFALE__GPIO6_4			0xa4 0x032
+#define MX21_PAD_NFALE__PC_OE			0xa4 0x006
+#define MX21_PAD_NFRE__NFRE			0xa5 0x004
+#define MX21_PAD_NFRE__GPIO6_5			0xa5 0x032
+#define MX21_PAD_NFRE__PC_RW			0xa5 0x006
+#define MX21_PAD_NFWE__NFWE			0xa6 0x004
+#define MX21_PAD_NFWE__GPIO6_6			0xa6 0x032
+#define MX21_PAD_NFWE__PC_BVD2			0xa6 0x002
+#define MX21_PAD_NFIO0__NFIO0			0xa7 0x000
+#define MX21_PAD_NFIO0__GPIO6_7			0xa7 0x032
+#define MX21_PAD_NFIO0__PC_BVD2			0xa7 0x002
+#define MX21_PAD_NFIO1__NFIO1			0xa8 0x000
+#define MX21_PAD_NFIO1__GPIO6_8			0xa8 0x032
+#define MX21_PAD_NFIO1__PC_VS2			0xa8 0x002
+#define MX21_PAD_NFIO2__NFIO2			0xa9 0x000
+#define MX21_PAD_NFIO2__GPIO6_9			0xa9 0x032
+#define MX21_PAD_NFIO2__PC_VS1			0xa9 0x002
+#define MX21_PAD_NFIO3__NFIO3			0xaa 0x004
+#define MX21_PAD_NFIO3__GPIO6_10		0xaa 0x032
+#define MX21_PAD_NFIO3__PC_WP			0xaa 0x002
+#define MX21_PAD_NFIO4__NFIO4			0xab 0x000
+#define MX21_PAD_NFIO4__GPIO6_11		0xab 0x032
+#define MX21_PAD_NFIO4__PC_READY		0xab 0x002
+#define MX21_PAD_NFIO5__NFIO5			0xac 0x000
+#define MX21_PAD_NFIO5__GPIO6_12		0xac 0x032
+#define MX21_PAD_NFIO5__PC_WAIT			0xac 0x002
+#define MX21_PAD_NFIO6__NFIO6			0xad 0x000
+#define MX21_PAD_NFIO6__GPIO6_13		0xad 0x032
+#define MX21_PAD_NFIO6__PC_CD2			0xad 0x002
+#define MX21_PAD_NFIO7__NFIO7			0xae 0x000
+#define MX21_PAD_NFIO7__GPIO6_14		0xae 0x032
+#define MX21_PAD_NFIO7__PC_CD1			0xae 0x002
+#define MX21_PAD_CLKO__CLKO			0xaf 0x004
+#define MX21_PAD_CLKO__GPIO6_15			0xaf 0x032
+#define MX21_PAD_RESERVED__RESERVED		0xb0 0x000
+#define MX21_PAD_RESERVED__GPIO6_16		0xb0 0x032
+#define MX21_PAD_CS4__CS4			0xb5 0x004
+#define MX21_PAD_CS4__GPIO6_21			0xb5 0x032
+#define MX21_PAD_CS4__DTACK			0xb5 0x002
+#define MX21_PAD_CS5__CS5			0xb6 0x004
+#define MX21_PAD_CS5__GPIO6_22			0xb6 0x032
+
+#endif
diff --git a/arch/arm/boot/dts/imx21.dtsi b/arch/arm/boot/dts/imx21.dtsi
new file mode 100644
index 0000000..e2f09dd
--- /dev/null
+++ b/arch/arm/boot/dts/imx21.dtsi
@@ -0,0 +1,465 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/* Author: Alexander Shiyan <shc_work@mail.ru> */
+
+#include "imx21-pinfunc.h"
+
+#include <dt-bindings/clock/imx21-clock.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	chosen {};
+
+	memory {
+		device_type = "memory";
+	};
+
+	aliases {
+		gpio0 = &gpio1;
+		gpio1 = &gpio2;
+		gpio2 = &gpio3;
+		gpio3 = &gpio4;
+		gpio4 = &gpio5;
+		gpio5 = &gpio6;
+		i2c0 = &i2c;
+		serial0 = &serial1;
+		serial1 = &serial2;
+		serial2 = &serial3;
+		serial3 = &serial4;
+		spi0 = &cspi1;
+		spi1 = &cspi2;
+		spi2 = &cspi3;
+	};
+
+	aitc: aitc-interrupt-controller@10040000 {
+		compatible = "fsl,imx21-aitc", "fsl,avic";
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		reg = <0x10040000 0x1000>;
+	};
+
+	clocks {
+		clk_ckil: ckil {
+			compatible = "fsl,imx-ckil", "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <32768>;
+		};
+
+		clk_ckih: ckih {
+			compatible = "fsl,imx-ckih", "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <26000000>;
+		};
+	};
+
+	cpus {
+		#size-cells = <0>;
+		#address-cells = <1>;
+
+		cpu: cpu@0 {
+			device_type = "cpu";
+			reg = <0>;
+			compatible = "arm,arm926ej-s";
+			operating-points = <266000 1550000>;
+			clock-latency = <62500>;
+			clocks = <&clks IMX21_CLK_FCLK>;
+			voltage-tolerance = <6>;
+		};
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		interrupt-parent = <&aitc>;
+		ranges;
+
+		aipi1: aipi@10000000 {
+			compatible = "fsl,aipi-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x10000000 0x20000>;
+			ranges;
+
+			dma: dma@10001000 {
+				compatible = "fsl,imx21-dma";
+				reg = <0x10001000 0x1000>;
+				interrupts = <32>;
+				clocks = <&clks IMX21_CLK_DMA_GATE>,
+					 <&clks IMX21_CLK_DMA_HCLK_GATE>;
+				clock-names = "ipg", "ahb";
+				#dma-cells = <1>;
+				#dma-channels = <16>;
+			};
+
+			wdog: wdog@10002000 {
+				compatible = "fsl,imx21-wdt";
+				reg = <0x10002000 0x1000>;
+				interrupts = <27>;
+				clocks = <&clks IMX21_CLK_WDOG_GATE>;
+			};
+
+			gpt1: timer@10003000 {
+				compatible = "fsl,imx21-gpt";
+				reg = <0x10003000 0x1000>;
+				interrupts = <26>;
+				clocks = <&clks IMX21_CLK_GPT1_IPG_GATE>,
+					 <&clks IMX21_CLK_PER1>;
+				clock-names = "ipg", "per";
+			};
+
+			gpt2: timer@10004000 {
+				compatible = "fsl,imx21-gpt";
+				reg = <0x10004000 0x1000>;
+				interrupts = <25>;
+				clocks = <&clks IMX21_CLK_GPT2_IPG_GATE>,
+					 <&clks IMX21_CLK_PER1>;
+				clock-names = "ipg", "per";
+			};
+
+			gpt3: timer@10005000 {
+				compatible = "fsl,imx21-gpt";
+				reg = <0x10005000 0x1000>;
+				interrupts = <24>;
+				clocks = <&clks IMX21_CLK_GPT3_IPG_GATE>,
+					 <&clks IMX21_CLK_PER1>;
+				clock-names = "ipg", "per";
+			};
+
+			pwm: pwm@10006000 {
+				#pwm-cells = <2>;
+				compatible = "fsl,imx21-pwm", "fsl,imx1-pwm";
+				reg = <0x10006000 0x1000>;
+				interrupts = <23>;
+				clocks = <&clks IMX21_CLK_PWM_IPG_GATE>,
+					 <&clks IMX21_CLK_PER1>;
+				clock-names = "ipg", "per";
+			};
+
+			rtc: rtc@10007000 {
+				compatible = "fsl,imx21-rtc";
+				reg = <0x10007000 0x1000>;
+				interrupts = <22>;
+				clocks = <&clks IMX21_CLK_CKIL>,
+					 <&clks IMX21_CLK_RTC_GATE>;
+				clock-names = "ref", "ipg";
+			};
+
+			kpp: kpp@10008000 {
+				compatible = "fsl,imx21-kpp";
+				reg = <0x10008000 0x1000>;
+				interrupts = <21>;
+				clocks = <&clks IMX21_CLK_KPP_GATE>;
+				status = "disabled";
+			};
+
+			owire: owire@10009000 {
+				compatible = "fsl,imx21-owire";
+				reg = <0x10009000 0x1000>;
+				clocks = <&clks IMX21_CLK_OWIRE_GATE>;
+				status = "disabled";
+			};
+
+			serial1: serial@1000a000 {
+				compatible = "fsl,imx21-uart";
+				reg = <0x1000a000 0x1000>;
+				interrupts = <20>;
+				clocks = <&clks IMX21_CLK_UART1_IPG_GATE>,
+					 <&clks IMX21_CLK_PER1>;
+				clock-names = "ipg", "per";
+				dmas = <&dma 26>, <&dma 27>;
+				dma-names = "rx", "tx";
+				status = "disabled";
+			};
+
+			serial2: serial@1000b000 {
+				compatible = "fsl,imx21-uart";
+				reg = <0x1000b000 0x1000>;
+				interrupts = <19>;
+				clocks = <&clks IMX21_CLK_UART2_IPG_GATE>,
+					 <&clks IMX21_CLK_PER1>;
+				clock-names = "ipg", "per";
+				dmas = <&dma 24>, <&dma 25>;
+				dma-names = "rx", "tx";
+				status = "disabled";
+			};
+
+			serial3: serial@1000c000 {
+				compatible = "fsl,imx21-uart";
+				reg = <0x1000c000 0x1000>;
+				interrupts = <18>;
+				clocks = <&clks IMX21_CLK_UART3_IPG_GATE>,
+					 <&clks IMX21_CLK_PER1>;
+				clock-names = "ipg", "per";
+				dmas = <&dma 22>, <&dma 23>;
+				dma-names = "rx", "tx";
+				status = "disabled";
+			};
+
+			serial4: serial@1000d000 {
+				compatible = "fsl,imx21-uart";
+				reg = <0x1000d000 0x1000>;
+				interrupts = <17>;
+				clocks = <&clks IMX21_CLK_UART4_IPG_GATE>,
+					 <&clks IMX21_CLK_PER1>;
+				clock-names = "ipg", "per";
+				dmas = <&dma 20>, <&dma 21>;
+				dma-names = "rx", "tx";
+				status = "disabled";
+			};
+
+			cspi1: spi@1000e000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx21-cspi";
+				reg = <0x1000e000 0x1000>;
+				interrupts = <16>;
+				clocks = <&clks IMX21_CLK_CSPI1_IPG_GATE>,
+					 <&clks IMX21_CLK_PER2>;
+				clock-names = "ipg", "per";
+				dmas = <&dma 18>, <&dma 19>;
+				dma-names = "rx", "tx";
+				status = "disabled";
+			};
+
+			cspi2: spi@1000f000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx21-cspi";
+				reg = <0x1000f000 0x1000>;
+				interrupts = <15>;
+				clocks = <&clks IMX21_CLK_CSPI2_IPG_GATE>,
+					 <&clks IMX21_CLK_PER2>;
+				clock-names = "ipg", "per";
+				dmas = <&dma 16>, <&dma 17>;
+				dma-names = "rx", "tx";
+				status = "disabled";
+			};
+
+			ssi1: ssi@10010000 {
+				#sound-dai-cells = <0>;
+				compatible ="fsl,imx21-ssi";
+				reg = <0x10010000 0x1000>;
+				interrupts = <14>;
+				clocks = <&clks IMX21_CLK_SSI1_BAUD_GATE>;
+				dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>;
+				dma-names = "rx0", "tx0", "rx1", "tx1";
+				fsl,fifo-depth = <8>;
+				status = "disabled";
+			};
+
+			ssi2: ssi@10011000 {
+				#sound-dai-cells = <0>;
+				compatible = "fsl,imx21-ssi";
+				reg = <0x10011000 0x1000>;
+				interrupts = <13>;
+				clocks = <&clks IMX21_CLK_SSI2_BAUD_GATE>;
+				dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>;
+				dma-names = "rx0", "tx0", "rx1", "tx1";
+				fsl,fifo-depth = <8>;
+				status = "disabled";
+			};
+
+			i2c: i2c@10012000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx21-i2c";
+				reg = <0x10012000 0x1000>;
+				interrupts = <12>;
+				clocks = <&clks IMX21_CLK_I2C_GATE>;
+				status = "disabled";
+			};
+
+			sdhci1: sdhci@10013000 {
+				compatible = "fsl,imx21-mmc";
+				reg = <0x10013000 0x1000>;
+				interrupts = <11>;
+				clocks = <&clks IMX21_CLK_SDHC1_IPG_GATE>,
+					 <&clks IMX21_CLK_PER2>;
+				clock-names = "ipg", "per";
+				dmas = <&dma 7>;
+				dma-names = "rx-tx";
+				bus-width = <4>;
+				status = "disabled";
+			};
+
+			sdhci2: sdhci@10014000 {
+				compatible = "fsl,imx21-mmc";
+				reg = <0x10014000 0x1000>;
+				interrupts = <10>;
+				clocks = <&clks IMX21_CLK_SDHC2_IPG_GATE>,
+					 <&clks IMX21_CLK_PER2>;
+				clock-names = "ipg", "per";
+				dmas = <&dma 6>;
+				dma-names = "rx-tx";
+				bus-width = <4>;
+				status = "disabled";
+			};
+
+			iomuxc: iomuxc@10015000 {
+				compatible = "fsl,imx27-iomuxc";
+				reg = <0x10015000 0x600>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges;
+
+				gpio1: gpio@10015000 {
+					compatible = "fsl,imx21-gpio";
+					reg = <0x10015000 0x100>;
+					clocks = <&clks IMX21_CLK_GPIO_GATE>;
+					interrupts = <8>;
+					gpio-controller;
+					#gpio-cells = <2>;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+				};
+
+				gpio2: gpio@10015100 {
+					compatible = "fsl,imx21-gpio";
+					reg = <0x10015100 0x100>;
+					clocks = <&clks IMX21_CLK_GPIO_GATE>;
+					interrupts = <8>;
+					gpio-controller;
+					#gpio-cells = <2>;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+				};
+
+				gpio3: gpio@10015200 {
+					compatible = "fsl,imx21-gpio";
+					reg = <0x10015200 0x100>;
+					clocks = <&clks IMX21_CLK_GPIO_GATE>;
+					interrupts = <8>;
+					gpio-controller;
+					#gpio-cells = <2>;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+				};
+
+				gpio4: gpio@10015300 {
+					compatible = "fsl,imx21-gpio";
+					reg = <0x10015300 0x100>;
+					clocks = <&clks IMX21_CLK_GPIO_GATE>;
+					interrupts = <8>;
+					gpio-controller;
+					#gpio-cells = <2>;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+				};
+
+				gpio5: gpio@10015400 {
+					compatible = "fsl,imx21-gpio";
+					reg = <0x10015400 0x100>;
+					clocks = <&clks IMX21_CLK_GPIO_GATE>;
+					interrupts = <8>;
+					gpio-controller;
+					#gpio-cells = <2>;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+				};
+
+				gpio6: gpio@10015500 {
+					compatible = "fsl,imx21-gpio";
+					reg = <0x10015500 0x100>;
+					clocks = <&clks IMX21_CLK_GPIO_GATE>;
+					interrupts = <8>;
+					gpio-controller;
+					#gpio-cells = <2>;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+				};
+			};
+
+			audmux: audmux@10016000 {
+				compatible = "fsl,imx21-audmux";
+				reg = <0x10016000 0x1000>;
+				clocks = <&clks IMX21_CLK_DUMMY>;
+				clock-names = "audmux";
+				status = "disabled";
+			};
+
+			cspi3: spi@10017000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx21-cspi";
+				reg = <0x10017000 0x1000>;
+				interrupts = <6>;
+				clocks = <&clks IMX21_CLK_CSPI3_IPG_GATE>,
+					 <&clks IMX21_CLK_PER2>;
+				clock-names = "ipg", "per";
+				dmas = <&dma 1>, <&dma 2>;
+				dma-names = "rx", "tx";
+				status = "disabled";
+			};
+		};
+
+		aipi2: aipi@10020000 {
+			compatible = "fsl,aipi-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x10020000 0x20000>;
+			ranges;
+
+
+			fb: lcdc@10021000 {
+				compatible = "fsl,imx21-fb";
+				interrupts = <61>;
+				reg = <0x10021000 0x1000>;
+				clocks = <&clks IMX21_CLK_LCDC_IPG_GATE>,
+					 <&clks IMX21_CLK_LCDC_HCLK_GATE>,
+					 <&clks IMX21_CLK_PER3>;
+				clock-names = "ipg", "ahb", "per";
+				status = "disabled";
+			};
+
+			emmaprp: emmaprp@10026400 {
+				compatible = "fsl,imx21-emmaprp";
+				reg = <0x10026400 0x100>;
+				interrupts = <51>;
+				clocks = <&clks IMX21_CLK_EMMA_GATE>,
+					 <&clks IMX21_CLK_EMMA_HCLK_GATE>;
+				clock-names = "ipg", "ahb";
+				status = "disabled";
+			};
+
+			clks: ccm@10027000{
+				compatible = "fsl,imx21-ccm";
+				reg = <0x10027000 0x1000>;
+				#clock-cells = <1>;
+			};
+		};
+
+		eim: eim@df001000 {
+			#address-cells = <2>;
+			#size-cells = <1>;
+			compatible = "fsl,imx21-weim", "fsl,imx1-weim";
+			reg = <0xdf001000 0x1000>;
+			clocks = <&clks IMX21_CLK_HCLK>;
+			ranges = <
+				0 0 0xc8000000 0x04000000
+				1 0 0xcc000000 0x04000000
+				2 0 0xd0000000 0x01000000
+				3 0 0xd1000000 0x01000000
+				4 0 0xd2000000 0x01000000
+				5 0 0xd3000000 0x01000000
+			>;
+			status = "disabled";
+		};
+
+		nandfc: nand@df003000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "fsl,imx21-nand";
+			reg = <0xdf003000 0x1000>;
+			interrupts = <29>;
+			clocks = <&clks IMX21_CLK_NFC_GATE>;
+			status = "disabled";
+		};
+
+		vram: vram@ffffe800 {
+			compatible = "mmio-sram";
+			reg = <0xffffe800 0x1800>;
+		};
+	};
+};
-- 
2.10.2


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^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH 2/6] ARM i.MX21: Add devicetree support
  2018-12-22 10:51 [PATCH 1/6] ARM: dts: imx21: add i.MX21 SoC device tree Alexander Shiyan
@ 2018-12-22 10:51 ` Alexander Shiyan
  2019-01-12  2:53   ` Shawn Guo
  2018-12-22 10:51 ` [PATCH 3/6] ARM: dts: imx21: Add support for the i.MX21 Freescale ADS board Alexander Shiyan
                   ` (3 subsequent siblings)
  4 siblings, 1 reply; 9+ messages in thread
From: Alexander Shiyan @ 2018-12-22 10:51 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Alexander Shiyan, Russell King, NXP Linux Team,
	Pengutronix Kernel Team, Fabio Estevam, Shawn Guo

This patch adds basic devicetree support for i.MX21 based SoCs.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
 arch/arm/mach-imx/Kconfig      |  7 +++++++
 arch/arm/mach-imx/Makefile     |  1 +
 arch/arm/mach-imx/mach-imx21.c | 31 +++++++++++++++++++++++++++++++
 3 files changed, 39 insertions(+)
 create mode 100644 arch/arm/mach-imx/mach-imx21.c

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index abc3371..abf3c0d 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -91,6 +91,13 @@ config MACH_MX21ADS
 	  Include support for MX21ADS platform. This includes specific
 	  configurations for the board and its peripherals.
 
+config MACH_IMX21_DT
+	bool "Support i.MX21 platforms from device tree"
+	select SOC_IMX21
+	help
+	  Include support for Freescale i.MX21 based platforms
+	  using the device tree for discovery
+
 comment "MX27 platforms:"
 
 config MACH_MX27ADS
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index bae179a..52a9138 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -38,6 +38,7 @@ endif
 
 # i.MX21 based machines
 obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
+obj-$(CONFIG_MACH_IMX21_DT) += mach-imx21.o
 
 # i.MX27 based machines
 obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
diff --git a/arch/arm/mach-imx/mach-imx21.c b/arch/arm/mach-imx/mach-imx21.c
new file mode 100644
index 0000000..7eb7de0
--- /dev/null
+++ b/arch/arm/mach-imx/mach-imx21.c
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/* Author: Alexander Shiyan <shc_work@mail.ru> */
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <linux/of_platform.h>
+
+#include "common.h"
+#include "hardware.h"
+
+#define MX21_AVIC_ADDR	0x10040000
+
+static void __init imx21_init_irq(void)
+{
+	void __iomem *avic = ioremap(MX21_AVIC_ADDR, SZ_4K);
+
+	WARN_ON(!avic);
+
+	mxc_init_irq(avic);
+}
+
+static const char * const imx21_dt_board_compat[] __initconst = {
+	"fsl,imx21",
+	NULL
+};
+
+DT_MACHINE_START(IMX21_DT, "Freescale i.MX21 (Device Tree Support)")
+	.init_early	= imx21_init_early,
+	.init_irq	= imx21_init_irq,
+	.dt_compat	= imx21_dt_board_compat,
+MACHINE_END
-- 
2.10.2


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^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH 3/6] ARM: dts: imx21: Add support for the i.MX21 Freescale ADS board
  2018-12-22 10:51 [PATCH 1/6] ARM: dts: imx21: add i.MX21 SoC device tree Alexander Shiyan
  2018-12-22 10:51 ` [PATCH 2/6] ARM i.MX21: Add devicetree support Alexander Shiyan
@ 2018-12-22 10:51 ` Alexander Shiyan
  2018-12-22 10:51 ` [PATCH 4/6] ARM: i.MX: Remove i.MX21 Freescale ADS board support Alexander Shiyan
                   ` (2 subsequent siblings)
  4 siblings, 0 replies; 9+ messages in thread
From: Alexander Shiyan @ 2018-12-22 10:51 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Alexander Shiyan, Russell King, NXP Linux Team,
	Pengutronix Kernel Team, Fabio Estevam, Shawn Guo

This patch adds support for the i.MX21 ADS from Freescale.
This change is intended to further remove non-DT support for this board.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
 arch/arm/boot/dts/Makefile      |   2 +
 arch/arm/boot/dts/imx21-ads.dts | 242 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 244 insertions(+)
 create mode 100644 arch/arm/boot/dts/imx21-ads.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b0e966d..e71be45 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -338,6 +338,8 @@ dtb-$(CONFIG_ARCH_MOXART) += \
 dtb-$(CONFIG_SOC_IMX1) += \
 	imx1-ads.dtb \
 	imx1-apf9328.dtb
+dtb-$(CONFIG_SOC_IMX21) += \
+	imx21-ads.dtb
 dtb-$(CONFIG_SOC_IMX25) += \
 	imx25-eukrea-mbimxsd25-baseboard.dtb \
 	imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dtb \
diff --git a/arch/arm/boot/dts/imx21-ads.dts b/arch/arm/boot/dts/imx21-ads.dts
new file mode 100644
index 0000000..58c9581
--- /dev/null
+++ b/arch/arm/boot/dts/imx21-ads.dts
@@ -0,0 +1,242 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/* Author: Alexander Shiyan <shc_work@mail.ru> */
+
+/dts-v1/;
+
+#include "imx21.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	model = "Freescale MX21 ADS";
+	compatible = "fsl,imx21ads", "fsl,imx21";
+
+	chosen {
+		stdout-path = &serial1;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0xc0000000 0x04000000>;
+	};
+
+	display: LQ035Q7 {
+		model = "Sharp-LQ035Q7";
+		native-mode = <&timing>;
+		bits-per-pixel = <16>;
+		fsl,pcr = <0xfb108bc7>;
+
+		display-timings {
+			timing: 240x320 {
+				clock-frequency = <5500000>;
+				hactive = <240>;
+				vactive = <320>;
+				hback-porch = <6>;
+				hsync-len = <2>;
+				hfront-porch = <16>;
+				vback-porch = <8>;
+				vsync-len = <1>;
+				vfront-porch = <10>;
+				vsync-active = <0>;
+			};
+		};
+	};
+
+	led3: led3 {
+		compatible = "gpio-leds";
+		label = "system::live";
+		gpios = <&ioreg 15 GPIO_ACTIVE_LOW>;
+		linux,default-trigger = "heartbeat";
+	};
+
+	led4: led4 {
+		compatible = "gpio-leds";
+		label = "system::user";
+		gpios = <&ioreg 14 GPIO_ACTIVE_LOW>;
+	};
+
+	reg_lcd: regulator_lcd {
+		compatible = "regulator-fixed";
+		regulator-name = "lcd";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&ioreg 9 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+};
+
+&eim {
+	status = "okay";
+
+	nor: nor@0,0 {
+		compatible = "cfi-flash";
+		reg = <0 0x00000000 0x02000000>;
+		bank-width = <2>;
+		fsl,weim-cs-timing = <0x00003e00 0x00000e01>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+	};
+
+	ethernet: cs8900a@1,0 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_ethernet>;
+		compatible = "cirrus,cs8900";
+		reg = <1 0x00000000 0x00001000>;
+		interrupt-parent = <&gpio5>;
+		interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+		fsl,weim-cs-timing = <0x00002000 0x11118501>;
+	};
+
+	ioreg: ioreg@1,800000 {
+		compatible = "ti,7416374";
+		reg = <1 0x00800000 0x00000002>;
+		gpio-controller;
+		fsl,weim-cs-timing = <0x00002000 0x11118501>;
+		#gpio-cells = <2>;
+	};
+};
+
+&fb {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fb>;
+	display = <&display>;
+	fsl,dmacr = <0x00020008>;
+	fsl,lscr1 = <0x00120300>;
+	fsl,lpccr = <0x00a903ff>;
+	lcd-supply = <&reg_lcd>;
+	status = "okay";
+};
+
+&nandfc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_nandfc>;
+	nand-bus-width = <8>;
+	nand-ecc-mode = "hw";
+	nand-on-flash-bbt;
+	status = "okay";
+};
+
+&sdhci1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sdhci1>;
+	cd-gpios = <&gpio4 25 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&serial1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_serial1>;
+	uart-has-rtscts;
+	status = "okay";
+};
+
+&serial3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_serial3>;
+	status = "okay";
+};
+
+&serial4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_serial4>;
+	uart-has-rtscts;
+	status = "okay";
+};
+
+&iomuxc {
+	imx21_ads21 {
+		pinctrl_ethernet: ethernetgrp {
+			fsl,pins = <
+				MX21_PAD_UART3_RTS__GPIO5_11	0x0	/* IRQ */
+			>;
+		};
+
+		pinctrl_fb: fbgrp {
+			fsl,pins = <
+				MX21_PAD_LSCLK__LSCLK		0x0
+				MX21_PAD_LD0__LD0		0x0
+				MX21_PAD_LD1__LD1		0x0
+				MX21_PAD_LD2__LD2		0x0
+				MX21_PAD_LD3__LD3		0x0
+				MX21_PAD_LD4__LD4		0x0
+				MX21_PAD_LD5__LD5		0x0
+				MX21_PAD_LD6__LD6		0x0
+				MX21_PAD_LD7__LD7		0x0
+				MX21_PAD_LD8__LD8		0x0
+				MX21_PAD_LD9__LD9		0x0
+				MX21_PAD_LD10__LD10		0x0
+				MX21_PAD_LD11__LD11		0x0
+				MX21_PAD_LD12__LD12		0x0
+				MX21_PAD_LD13__LD13		0x0
+				MX21_PAD_LD14__LD14		0x0
+				MX21_PAD_LD15__LD15		0x0
+				MX21_PAD_REV__REV		0x0
+				MX21_PAD_CLS__CLS		0x0
+				MX21_PAD_PS__PS			0x0
+				MX21_PAD_SPL_SPR__SPL_SPR	0x0
+				MX21_PAD_HSYNC__HSYNC		0x0
+				MX21_PAD_VSYNC__VSYNC		0x0
+				MX21_PAD_CONTRAST__CONTRAST	0x0
+				MX21_PAD_OE_ACD__OE_ACD		0x0
+			>;
+		};
+
+		pinctrl_nandfc: nandfcgrp {
+			fsl,pins = <
+				MX21_PAD_NFRB__NFRB		0x0
+				MX21_PAD_NFCE__NFCE		0x0
+				MX21_PAD_NFWP__NFWP		0x0
+				MX21_PAD_NFCLE__NFCLE		0x0
+				MX21_PAD_NFALE__NFALE		0x0
+				MX21_PAD_NFRE__NFRE		0x0
+				MX21_PAD_NFWE__NFWE		0x0
+				MX21_PAD_NFIO0__NFIO0		0x0
+				MX21_PAD_NFIO1__NFIO1		0x0
+				MX21_PAD_NFIO2__NFIO2		0x0
+				MX21_PAD_NFIO3__NFIO3		0x0
+				MX21_PAD_NFIO4__NFIO4		0x0
+				MX21_PAD_NFIO5__NFIO5		0x0
+				MX21_PAD_NFIO6__NFIO6		0x0
+				MX21_PAD_NFIO7__NFIO7		0x0
+			>;
+		};
+
+		pinctrl_sdhci1: sdhci1grp {
+			fsl,pins = <
+				MX21_PAD_SD1_D0__SD1_D0		0x0
+				MX21_PAD_SD1_D1__SD1_D1		0x0
+				MX21_PAD_SD1_D2__SD1_D2		0x0
+				MX21_PAD_SD1_D3__SD1_D3		0x0
+				MX21_PAD_SD1_CMD__SD1_CMD	0x0
+				MX21_PAD_SD1_CLK__SD1_CLK	0x0
+				MX21_PAD_CSPI1_RDY__GPIO4_25	0x0	/* CD */
+			>;
+		};
+
+		pinctrl_serial1: serial1grp {
+			fsl,pins = <
+				MX21_PAD_UART1_TXD__UART1_TXD	0x0
+				MX21_PAD_UART1_RXD__UART1_RXD	0x0
+				MX21_PAD_UART1_CTS__UART1_CTS	0x0
+				MX21_PAD_UART1_RTS__UART1_RTS	0x0
+			>;
+		};
+
+		pinctrl_serial3: serial3grp {
+			fsl,pins = <
+				MX21_PAD_UART3_TXD__UART3_TXD	0x0
+				MX21_PAD_UART3_RXD__UART3_RXD	0x0
+			>;
+		};
+
+		pinctrl_serial4: serial4grp {
+			fsl,pins = <
+				MX21_PAD_USBH1_TXDM__UART4_TXD	0x0
+				MX21_PAD_USBH1_RXDP__UART4_RXD	0x0
+				MX21_PAD_USBH1_FS__UART4_RTS	0x0
+				MX21_PAD_USBH1_TXDP__UART4_CTS	0x0
+			>;
+		};
+	};
+};
-- 
2.10.2


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^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH 4/6] ARM: i.MX: Remove i.MX21 Freescale ADS board support
  2018-12-22 10:51 [PATCH 1/6] ARM: dts: imx21: add i.MX21 SoC device tree Alexander Shiyan
  2018-12-22 10:51 ` [PATCH 2/6] ARM i.MX21: Add devicetree support Alexander Shiyan
  2018-12-22 10:51 ` [PATCH 3/6] ARM: dts: imx21: Add support for the i.MX21 Freescale ADS board Alexander Shiyan
@ 2018-12-22 10:51 ` Alexander Shiyan
  2018-12-22 10:51 ` [PATCH 5/6] ARM: i.MX: Move SOC_IMX21 into 'Device tree only' Alexander Shiyan
  2018-12-22 10:52 ` [PATCH 6/6] ARM: i.MX: Remove i.MX21 non-DT device registration helpers Alexander Shiyan
  4 siblings, 0 replies; 9+ messages in thread
From: Alexander Shiyan @ 2018-12-22 10:51 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Alexander Shiyan, Russell King, NXP Linux Team,
	Pengutronix Kernel Team, Fabio Estevam, Shawn Guo

mach-mx21ads.c can be replaced with devicetree equivalent: imx21-ads.dts,
so remove the board file.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
 arch/arm/mach-imx/Kconfig        |  11 --
 arch/arm/mach-imx/Makefile       |   1 -
 arch/arm/mach-imx/mach-mx21ads.c | 348 ---------------------------------------
 3 files changed, 360 deletions(-)
 delete mode 100644 arch/arm/mach-imx/mach-mx21ads.c

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index abf3c0d..7b49939 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -80,17 +80,6 @@ if ARCH_MULTI_V5
 
 comment "MX21 platforms:"
 
-config MACH_MX21ADS
-	bool "MX21ADS platform"
-	select IMX_HAVE_PLATFORM_IMX_FB
-	select IMX_HAVE_PLATFORM_IMX_UART
-	select IMX_HAVE_PLATFORM_MXC_MMC
-	select IMX_HAVE_PLATFORM_MXC_NAND
-	select SOC_IMX21
-	help
-	  Include support for MX21ADS platform. This includes specific
-	  configurations for the board and its peripherals.
-
 config MACH_IMX21_DT
 	bool "Support i.MX21 platforms from device tree"
 	select SOC_IMX21
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 52a9138..a629af2 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -37,7 +37,6 @@ obj-y += ssi-fiq-ksym.o
 endif
 
 # i.MX21 based machines
-obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
 obj-$(CONFIG_MACH_IMX21_DT) += mach-imx21.o
 
 # i.MX27 based machines
diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
deleted file mode 100644
index 2e1e540..0000000
--- a/arch/arm/mach-imx/mach-mx21ads.c
+++ /dev/null
@@ -1,348 +0,0 @@
-/*
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
- *  Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/physmap.h>
-#include <linux/gpio/driver.h>
-#include <linux/gpio/machine.h>
-#include <linux/gpio.h>
-#include <linux/regulator/fixed.h>
-#include <linux/regulator/machine.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include "common.h"
-#include "devices-imx21.h"
-#include "hardware.h"
-#include "iomux-mx21.h"
-
-#define MX21ADS_CS8900A_REG		(MX21_CS1_BASE_ADDR + 0x000000)
-#define MX21ADS_ST16C255_IOBASE_REG	(MX21_CS1_BASE_ADDR + 0x200000)
-#define MX21ADS_VERSION_REG		(MX21_CS1_BASE_ADDR + 0x400000)
-#define MX21ADS_IO_REG			(MX21_CS1_BASE_ADDR + 0x800000)
-
-#define MX21ADS_MMC_CD			IMX_GPIO_NR(4, 25)
-#define MX21ADS_CS8900A_IRQ_GPIO	IMX_GPIO_NR(5, 11)
-#define MX21ADS_MMGPIO_BASE		(6 * 32)
-
-/* MX21ADS_IO_REG bit definitions */
-#define MX21ADS_IO_SD_WP		(MX21ADS_MMGPIO_BASE + 0)
-#define MX21ADS_IO_TP6			(MX21ADS_IO_SD_WP)
-#define MX21ADS_IO_SW_SEL		(MX21ADS_MMGPIO_BASE + 1)
-#define MX21ADS_IO_TP7			(MX21ADS_IO_SW_SEL)
-#define MX21ADS_IO_RESET_E_UART		(MX21ADS_MMGPIO_BASE + 2)
-#define MX21ADS_IO_RESET_BASE		(MX21ADS_MMGPIO_BASE + 3)
-#define MX21ADS_IO_CSI_CTL2		(MX21ADS_MMGPIO_BASE + 4)
-#define MX21ADS_IO_CSI_CTL1		(MX21ADS_MMGPIO_BASE + 5)
-#define MX21ADS_IO_CSI_CTL0		(MX21ADS_MMGPIO_BASE + 6)
-#define MX21ADS_IO_UART1_EN		(MX21ADS_MMGPIO_BASE + 7)
-#define MX21ADS_IO_UART4_EN		(MX21ADS_MMGPIO_BASE + 8)
-#define MX21ADS_IO_LCDON		(MX21ADS_MMGPIO_BASE + 9)
-#define MX21ADS_IO_IRDA_EN		(MX21ADS_MMGPIO_BASE + 10)
-#define MX21ADS_IO_IRDA_FIR_SEL		(MX21ADS_MMGPIO_BASE + 11)
-#define MX21ADS_IO_IRDA_MD0_B		(MX21ADS_MMGPIO_BASE + 12)
-#define MX21ADS_IO_IRDA_MD1		(MX21ADS_MMGPIO_BASE + 13)
-#define MX21ADS_IO_LED4_ON		(MX21ADS_MMGPIO_BASE + 14)
-#define MX21ADS_IO_LED3_ON		(MX21ADS_MMGPIO_BASE + 15)
-
-static const int mx21ads_pins[] __initconst = {
-
-	/* CS8900A */
-	(GPIO_PORTE | GPIO_GPIO | GPIO_IN | 11),
-
-	/* UART1 */
-	PE12_PF_UART1_TXD,
-	PE13_PF_UART1_RXD,
-	PE14_PF_UART1_CTS,
-	PE15_PF_UART1_RTS,
-
-	/* UART3 (IrDA) - only TXD and RXD */
-	PE8_PF_UART3_TXD,
-	PE9_PF_UART3_RXD,
-
-	/* UART4 */
-	PB26_AF_UART4_RTS,
-	PB28_AF_UART4_TXD,
-	PB29_AF_UART4_CTS,
-	PB31_AF_UART4_RXD,
-
-	/* LCDC */
-	PA5_PF_LSCLK,
-	PA6_PF_LD0,
-	PA7_PF_LD1,
-	PA8_PF_LD2,
-	PA9_PF_LD3,
-	PA10_PF_LD4,
-	PA11_PF_LD5,
-	PA12_PF_LD6,
-	PA13_PF_LD7,
-	PA14_PF_LD8,
-	PA15_PF_LD9,
-	PA16_PF_LD10,
-	PA17_PF_LD11,
-	PA18_PF_LD12,
-	PA19_PF_LD13,
-	PA20_PF_LD14,
-	PA21_PF_LD15,
-	PA22_PF_LD16,
-	PA24_PF_REV,     /* Sharp panel dedicated signal */
-	PA25_PF_CLS,     /* Sharp panel dedicated signal */
-	PA26_PF_PS,      /* Sharp panel dedicated signal */
-	PA27_PF_SPL_SPR, /* Sharp panel dedicated signal */
-	PA28_PF_HSYNC,
-	PA29_PF_VSYNC,
-	PA30_PF_CONTRAST,
-	PA31_PF_OE_ACD,
-
-	/* MMC/SDHC */
-	PE18_PF_SD1_D0,
-	PE19_PF_SD1_D1,
-	PE20_PF_SD1_D2,
-	PE21_PF_SD1_D3,
-	PE22_PF_SD1_CMD,
-	PE23_PF_SD1_CLK,
-
-	/* NFC */
-	PF0_PF_NRFB,
-	PF1_PF_NFCE,
-	PF2_PF_NFWP,
-	PF3_PF_NFCLE,
-	PF4_PF_NFALE,
-	PF5_PF_NFRE,
-	PF6_PF_NFWE,
-	PF7_PF_NFIO0,
-	PF8_PF_NFIO1,
-	PF9_PF_NFIO2,
-	PF10_PF_NFIO3,
-	PF11_PF_NFIO4,
-	PF12_PF_NFIO5,
-	PF13_PF_NFIO6,
-	PF14_PF_NFIO7,
-};
-
-/* ADS's NOR flash: 2x AM29BDS128HE9VKI on 32-bit bus */
-static struct physmap_flash_data mx21ads_flash_data = {
-	.width = 4,
-};
-
-static struct resource mx21ads_flash_resource =
-	DEFINE_RES_MEM(MX21_CS0_BASE_ADDR, SZ_32M);
-
-static struct platform_device mx21ads_nor_mtd_device = {
-	.name = "physmap-flash",
-	.id = 0,
-	.dev = {
-		.platform_data = &mx21ads_flash_data,
-	},
-	.num_resources = 1,
-	.resource = &mx21ads_flash_resource,
-};
-
-static struct resource mx21ads_cs8900_resources[] __initdata = {
-	DEFINE_RES_MEM(MX21ADS_CS8900A_REG, SZ_1K),
-	/* irq number is run-time assigned */
-	DEFINE_RES_IRQ(-1),
-};
-
-static const struct platform_device_info mx21ads_cs8900_devinfo __initconst = {
-	.name = "cs89x0",
-	.id = 0,
-	.res = mx21ads_cs8900_resources,
-	.num_res = ARRAY_SIZE(mx21ads_cs8900_resources),
-};
-
-static const struct imxuart_platform_data uart_pdata_rts __initconst = {
-	.flags = IMXUART_HAVE_RTSCTS,
-};
-
-static const struct imxuart_platform_data uart_pdata_norts __initconst = {
-};
-
-static struct resource mx21ads_mmgpio_resource =
-	DEFINE_RES_MEM_NAMED(MX21ADS_IO_REG, SZ_2, "dat");
-
-static struct bgpio_pdata mx21ads_mmgpio_pdata = {
-	.label	= "mx21ads-mmgpio",
-	.base	= MX21ADS_MMGPIO_BASE,
-	.ngpio	= 16,
-};
-
-static struct platform_device mx21ads_mmgpio = {
-	.name = "basic-mmio-gpio",
-	.id = PLATFORM_DEVID_AUTO,
-	.resource = &mx21ads_mmgpio_resource,
-	.num_resources = 1,
-	.dev = {
-		.platform_data = &mx21ads_mmgpio_pdata,
-	},
-};
-
-static struct regulator_consumer_supply mx21ads_lcd_regulator_consumer =
-	REGULATOR_SUPPLY("lcd", "imx-fb.0");
-
-static struct regulator_init_data mx21ads_lcd_regulator_init_data = {
-	.constraints = {
-		.valid_ops_mask	= REGULATOR_CHANGE_STATUS,
-	},
-	.consumer_supplies	= &mx21ads_lcd_regulator_consumer,
-	.num_consumer_supplies	= 1,
-};
-
-static struct fixed_voltage_config mx21ads_lcd_regulator_pdata = {
-	.supply_name	= "LCD",
-	.microvolts	= 3300000,
-	.enable_high	= 1,
-	.init_data	= &mx21ads_lcd_regulator_init_data,
-};
-
-static struct platform_device mx21ads_lcd_regulator = {
-	.name = "reg-fixed-voltage",
-	.id = PLATFORM_DEVID_AUTO,
-	.dev = {
-		.platform_data = &mx21ads_lcd_regulator_pdata,
-	},
-};
-
-static struct gpiod_lookup_table mx21ads_lcd_regulator_gpiod_table = {
-	.dev_id = "reg-fixed-voltage.0", /* Let's hope ID 0 is what we get */
-	.table = {
-		GPIO_LOOKUP("mx21ads-mmgpio", 9, NULL, GPIO_ACTIVE_HIGH),
-		{ },
-	},
-};
-
-/*
- * Connected is a portrait Sharp-QVGA display
- * of type: LQ035Q7DB02
- */
-static struct imx_fb_videomode mx21ads_modes[] = {
-	{
-		.mode = {
-			.name		= "Sharp-LQ035Q7",
-			.refresh	= 60,
-			.xres		= 240,
-			.yres		= 320,
-			.pixclock	= 188679, /* in ps (5.3MHz) */
-			.hsync_len	= 2,
-			.left_margin	= 6,
-			.right_margin	= 16,
-			.vsync_len	= 1,
-			.upper_margin	= 8,
-			.lower_margin	= 10,
-		},
-		.pcr		= 0xfb108bc7,
-		.bpp		= 16,
-	},
-};
-
-static const struct imx_fb_platform_data mx21ads_fb_data __initconst = {
-	.mode = mx21ads_modes,
-	.num_modes = ARRAY_SIZE(mx21ads_modes),
-
-	.pwmr		= 0x00a903ff,
-	.lscr1		= 0x00120300,
-	.dmacr		= 0x00020008,
-};
-
-static int mx21ads_sdhc_get_ro(struct device *dev)
-{
-	return gpio_get_value(MX21ADS_IO_SD_WP);
-}
-
-static int mx21ads_sdhc_init(struct device *dev, irq_handler_t detect_irq,
-	void *data)
-{
-	int ret;
-
-	ret = gpio_request(MX21ADS_IO_SD_WP, "mmc-ro");
-	if (ret)
-		return ret;
-
-	return request_irq(gpio_to_irq(MX21ADS_MMC_CD), detect_irq,
-			   IRQF_TRIGGER_FALLING, "mmc-detect", data);
-}
-
-static void mx21ads_sdhc_exit(struct device *dev, void *data)
-{
-	free_irq(gpio_to_irq(MX21ADS_MMC_CD), data);
-	gpio_free(MX21ADS_IO_SD_WP);
-}
-
-static const struct imxmmc_platform_data mx21ads_sdhc_pdata __initconst = {
-	.ocr_avail = MMC_VDD_29_30 | MMC_VDD_30_31, /* 3.0V */
-	.get_ro = mx21ads_sdhc_get_ro,
-	.init = mx21ads_sdhc_init,
-	.exit = mx21ads_sdhc_exit,
-};
-
-static const struct mxc_nand_platform_data
-mx21ads_nand_board_info __initconst = {
-	.width = 1,
-	.hw_ecc = 1,
-};
-
-static struct platform_device *platform_devices[] __initdata = {
-	&mx21ads_mmgpio,
-	&mx21ads_lcd_regulator,
-	&mx21ads_nor_mtd_device,
-};
-
-static void __init mx21ads_board_init(void)
-{
-	imx21_soc_init();
-
-	mxc_gpio_setup_multiple_pins(mx21ads_pins, ARRAY_SIZE(mx21ads_pins),
-			"mx21ads");
-
-	imx21_add_imx_uart0(&uart_pdata_rts);
-	imx21_add_imx_uart2(&uart_pdata_norts);
-	imx21_add_imx_uart3(&uart_pdata_rts);
-	imx21_add_mxc_nand(&mx21ads_nand_board_info);
-
-	imx21_add_imx_fb(&mx21ads_fb_data);
-}
-
-static void __init mx21ads_late_init(void)
-{
-	imx21_add_mxc_mmc(0, &mx21ads_sdhc_pdata);
-
-	gpiod_add_lookup_table(&mx21ads_lcd_regulator_gpiod_table);
-	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
-
-	mx21ads_cs8900_resources[1].start =
-			gpio_to_irq(MX21ADS_CS8900A_IRQ_GPIO);
-	mx21ads_cs8900_resources[1].end =
-			gpio_to_irq(MX21ADS_CS8900A_IRQ_GPIO);
-	platform_device_register_full(&mx21ads_cs8900_devinfo);
-}
-
-static void __init mx21ads_timer_init(void)
-{
-	mx21_clocks_init(32768, 26000000);
-}
-
-MACHINE_START(MX21ADS, "Freescale i.MX21ADS")
-	/* maintainer: Freescale Semiconductor, Inc. */
-	.atag_offset = 0x100,
-	.map_io		= mx21_map_io,
-	.init_early = imx21_init_early,
-	.init_irq = mx21_init_irq,
-	.init_time	= mx21ads_timer_init,
-	.init_machine	= mx21ads_board_init,
-	.init_late	= mx21ads_late_init,
-	.restart	= mxc_restart,
-MACHINE_END
-- 
2.10.2


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^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH 5/6] ARM: i.MX: Move SOC_IMX21 into 'Device tree only'
  2018-12-22 10:51 [PATCH 1/6] ARM: dts: imx21: add i.MX21 SoC device tree Alexander Shiyan
                   ` (2 preceding siblings ...)
  2018-12-22 10:51 ` [PATCH 4/6] ARM: i.MX: Remove i.MX21 Freescale ADS board support Alexander Shiyan
@ 2018-12-22 10:51 ` Alexander Shiyan
  2018-12-22 10:52 ` [PATCH 6/6] ARM: i.MX: Remove i.MX21 non-DT device registration helpers Alexander Shiyan
  4 siblings, 0 replies; 9+ messages in thread
From: Alexander Shiyan @ 2018-12-22 10:51 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Alexander Shiyan, Russell King, NXP Linux Team,
	Pengutronix Kernel Team, Fabio Estevam, Shawn Guo

This patch moves SOC_IMX21 into 'Device tree only' category and
updates imx_v4_v5 and multi_v5 default configs.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
 arch/arm/configs/imx_v4_v5_defconfig |  2 +-
 arch/arm/configs/multi_v5_defconfig  | 22 +++++++++++-----------
 arch/arm/mach-imx/Kconfig            | 23 ++++++++---------------
 arch/arm/mach-imx/Makefile           |  5 +----
 arch/arm/mach-imx/common.h           |  1 -
 arch/arm/mach-imx/mach-imx21.c       |  5 +++++
 6 files changed, 26 insertions(+), 32 deletions(-)

diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig
index 8661dd9..0ce6105 100644
--- a/arch/arm/configs/imx_v4_v5_defconfig
+++ b/arch/arm/configs/imx_v4_v5_defconfig
@@ -15,13 +15,13 @@ CONFIG_ARCH_MULTI_V4T=y
 CONFIG_ARCH_MULTI_V5=y
 # CONFIG_ARCH_MULTI_V7 is not set
 CONFIG_ARCH_MXC=y
-CONFIG_MACH_MX21ADS=y
 CONFIG_MACH_MX27ADS=y
 CONFIG_MACH_MX27_3DS=y
 CONFIG_MACH_IMX27_VISSTRIM_M10=y
 CONFIG_MACH_PCA100=y
 CONFIG_MACH_IMX27_DT=y
 CONFIG_SOC_IMX1=y
+CONFIG_SOC_IMX21=y
 CONFIG_SOC_IMX25=y
 CONFIG_AEABI=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
diff --git a/arch/arm/configs/multi_v5_defconfig b/arch/arm/configs/multi_v5_defconfig
index 318b76f..86b92dd 100644
--- a/arch/arm/configs/multi_v5_defconfig
+++ b/arch/arm/configs/multi_v5_defconfig
@@ -1,26 +1,23 @@
 CONFIG_SYSVIPC=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
 CONFIG_LOG_BUF_SHIFT=19
 CONFIG_CGROUPS=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_PROFILING=y
-CONFIG_OPROFILE=y
-CONFIG_KPROBES=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
 # CONFIG_ARCH_MULTI_V7 is not set
 CONFIG_ARCH_ASPEED=y
 CONFIG_MACH_ASPEED_G4=y
 CONFIG_ARCH_AT91=y
 CONFIG_SOC_AT91SAM9=y
 CONFIG_ARCH_MXC=y
-CONFIG_MACH_MX21ADS=y
 CONFIG_MACH_MX27ADS=y
 CONFIG_MACH_MX27_3DS=y
 CONFIG_MACH_IMX27_VISSTRIM_M10=y
 CONFIG_MACH_PCA100=y
 CONFIG_MACH_IMX27_DT=y
+CONFIG_SOC_IMX21=y
 CONFIG_SOC_IMX25=y
 CONFIG_ARCH_MVEBU=y
 CONFIG_MACH_KIRKWOOD=y
@@ -48,7 +45,6 @@ CONFIG_MACH_RD88F5181L_FXO=y
 CONFIG_MACH_RD88F6183AP_GE=y
 CONFIG_ARCH_U300=y
 CONFIG_PCI_MVEBU=y
-CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 CONFIG_HIGHMEM=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
@@ -60,6 +56,10 @@ CONFIG_CPU_FREQ_STAT=y
 CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
 CONFIG_CPU_IDLE=y
 CONFIG_ARM_KIRKWOOD_CPUIDLE=y
+CONFIG_OPROFILE=y
+CONFIG_KPROBES=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
@@ -275,6 +275,11 @@ CONFIG_NLS_CODEPAGE_850=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_ISO8859_2=y
 CONFIG_NLS_UTF8=y
+CONFIG_CRYPTO_CBC=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_DEV_MARVELL_CESA=y
+CONFIG_CRC_CCITT=y
+CONFIG_LIBCRC32C=y
 CONFIG_DEBUG_INFO=y
 CONFIG_DEBUG_FS=y
 CONFIG_MAGIC_SYSRQ=y
@@ -283,8 +288,3 @@ CONFIG_DEBUG_KERNEL=y
 # CONFIG_DEBUG_PREEMPT is not set
 # CONFIG_FTRACE is not set
 CONFIG_DEBUG_USER=y
-CONFIG_CRYPTO_CBC=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_DEV_MARVELL_CESA=y
-CONFIG_CRC_CCITT=y
-CONFIG_LIBCRC32C=y
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 7b49939..cd928d6 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -52,12 +52,6 @@ config IMX_HAVE_IOMUX_V1
 config ARCH_MXC_IOMUX_V3
 	bool
 
-config SOC_IMX21
-	bool
-	select CPU_ARM926T
-	select IMX_HAVE_IOMUX_V1
-	select MXC_AVIC
-
 config SOC_IMX27
 	bool
 	select CPU_ARM926T
@@ -78,15 +72,6 @@ config SOC_IMX35
 
 if ARCH_MULTI_V5
 
-comment "MX21 platforms:"
-
-config MACH_IMX21_DT
-	bool "Support i.MX21 platforms from device tree"
-	select SOC_IMX21
-	help
-	  Include support for Freescale i.MX21 based platforms
-	  using the device tree for discovery
-
 comment "MX27 platforms:"
 
 config MACH_MX27ADS
@@ -421,6 +406,14 @@ endif
 
 if ARCH_MULTI_V5
 
+config SOC_IMX21
+	bool "i.MX21 support"
+	select CPU_ARM926T
+	select MXC_AVIC
+	select PINCTRL_IMX21
+	help
+	  This enables support for Freescale i.MX21 processor
+
 config SOC_IMX25
 	bool "i.MX25 support"
 	select ARCH_MXC_IOMUX_V3
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index a629af2..1d56728 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 obj-y := cpu.o system.o irq-common.o
 
-obj-$(CONFIG_SOC_IMX21) += mm-imx21.o
+obj-$(CONFIG_SOC_IMX21) += mach-imx21.o
 
 obj-$(CONFIG_SOC_IMX25) += cpu-imx25.o mach-imx25.o pm-imx25.o
 
@@ -36,9 +36,6 @@ obj-y += ssi-fiq.o
 obj-y += ssi-fiq-ksym.o
 endif
 
-# i.MX21 based machines
-obj-$(CONFIG_MACH_IMX21_DT) += mach-imx21.o
-
 # i.MX27 based machines
 obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
 obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 423dd76..acfdb8b 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -25,7 +25,6 @@ void mx21_map_io(void);
 void mx27_map_io(void);
 void mx31_map_io(void);
 void mx35_map_io(void);
-void imx21_init_early(void);
 void imx27_init_early(void);
 void imx31_init_early(void);
 void imx35_init_early(void);
diff --git a/arch/arm/mach-imx/mach-imx21.c b/arch/arm/mach-imx/mach-imx21.c
index 7eb7de0..c841539 100644
--- a/arch/arm/mach-imx/mach-imx21.c
+++ b/arch/arm/mach-imx/mach-imx21.c
@@ -10,6 +10,11 @@
 
 #define MX21_AVIC_ADDR	0x10040000
 
+static void __init imx21_init_early(void)
+{
+	mxc_set_cpu_type(MXC_CPU_MX21);
+}
+
 static void __init imx21_init_irq(void)
 {
 	void __iomem *avic = ioremap(MX21_AVIC_ADDR, SZ_4K);
-- 
2.10.2


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^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH 6/6] ARM: i.MX: Remove i.MX21 non-DT device registration helpers
  2018-12-22 10:51 [PATCH 1/6] ARM: dts: imx21: add i.MX21 SoC device tree Alexander Shiyan
                   ` (3 preceding siblings ...)
  2018-12-22 10:51 ` [PATCH 5/6] ARM: i.MX: Move SOC_IMX21 into 'Device tree only' Alexander Shiyan
@ 2018-12-22 10:52 ` Alexander Shiyan
  4 siblings, 0 replies; 9+ messages in thread
From: Alexander Shiyan @ 2018-12-22 10:52 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Alexander Shiyan, Russell King, NXP Linux Team,
	Pengutronix Kernel Team, Fabio Estevam, Shawn Guo

i.MX21 is DT only platforms, so these non-DT device registration helpers
and functions is used nowhere.  Remove them.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
 arch/arm/mach-imx/common.h                      |   5 -
 arch/arm/mach-imx/devices-imx21.h               |  59 --------
 arch/arm/mach-imx/devices/Kconfig               |   3 -
 arch/arm/mach-imx/devices/Makefile              |   1 -
 arch/arm/mach-imx/devices/devices-common.h      |   9 --
 arch/arm/mach-imx/devices/platform-imx-fb.c     |   5 -
 arch/arm/mach-imx/devices/platform-imx-i2c.c    |   5 -
 arch/arm/mach-imx/devices/platform-imx-keypad.c |   5 -
 arch/arm/mach-imx/devices/platform-imx-ssi.c    |   9 --
 arch/arm/mach-imx/devices/platform-imx-uart.c   |  11 --
 arch/arm/mach-imx/devices/platform-imx2-wdt.c   |   5 -
 arch/arm/mach-imx/devices/platform-imx21-hcd.c  |  41 -----
 arch/arm/mach-imx/devices/platform-mxc-mmc.c    |   9 --
 arch/arm/mach-imx/devices/platform-mxc_nand.c   |   5 -
 arch/arm/mach-imx/devices/platform-mxc_w1.c     |   5 -
 arch/arm/mach-imx/devices/platform-spi_imx.c    |   9 --
 arch/arm/mach-imx/hardware.h                    |   1 -
 arch/arm/mach-imx/iomux-mx21.h                  | 122 ---------------
 arch/arm/mach-imx/mm-imx21.c                    |  99 -------------
 arch/arm/mach-imx/mx21.h                        | 189 ------------------------
 arch/arm/mach-imx/system.c                      |   8 -
 21 files changed, 605 deletions(-)
 delete mode 100644 arch/arm/mach-imx/devices-imx21.h
 delete mode 100644 arch/arm/mach-imx/devices/platform-imx21-hcd.c
 delete mode 100644 arch/arm/mach-imx/iomux-mx21.h
 delete mode 100644 arch/arm/mach-imx/mm-imx21.c
 delete mode 100644 arch/arm/mach-imx/mx21.h

diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index acfdb8b..b342bca 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -21,7 +21,6 @@ struct device_node;
 enum mxc_cpu_pwr_mode;
 struct of_device_id;
 
-void mx21_map_io(void);
 void mx27_map_io(void);
 void mx31_map_io(void);
 void mx35_map_io(void);
@@ -29,15 +28,12 @@ void imx27_init_early(void);
 void imx31_init_early(void);
 void imx35_init_early(void);
 void mxc_init_irq(void __iomem *);
-void mx21_init_irq(void);
 void mx27_init_irq(void);
 void mx31_init_irq(void);
 void mx35_init_irq(void);
-void imx21_soc_init(void);
 void imx27_soc_init(void);
 void imx31_soc_init(void);
 void imx35_soc_init(void);
-int mx21_clocks_init(unsigned long lref, unsigned long fref);
 int mx27_clocks_init(unsigned long fref);
 int mx31_clocks_init(unsigned long fref);
 int mx35_clocks_init(void);
@@ -46,7 +42,6 @@ struct platform_device *mxc_register_gpio(char *name, int id,
 void mxc_set_cpu_type(unsigned int type);
 void mxc_restart(enum reboot_mode, const char *);
 void mxc_arch_reset_init(void __iomem *);
-void imx1_reset_init(void __iomem *);
 void imx_set_aips(void __iomem *);
 void imx_aips_allow_unprivileged_access(const char *compat);
 int mxc_device_init(void);
diff --git a/arch/arm/mach-imx/devices-imx21.h b/arch/arm/mach-imx/devices-imx21.h
deleted file mode 100644
index bd93932..0000000
--- a/arch/arm/mach-imx/devices-imx21.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include "devices/devices-common.h"
-
-extern const struct imx_imx21_hcd_data imx21_imx21_hcd_data;
-#define imx21_add_imx21_hcd(pdata)	\
-	imx_add_imx21_hcd(&imx21_imx21_hcd_data, pdata)
-
-extern const struct imx_imx2_wdt_data imx21_imx2_wdt_data;
-#define imx21_add_imx2_wdt()	\
-	imx_add_imx2_wdt(&imx21_imx2_wdt_data)
-
-extern const struct imx_imx_fb_data imx21_imx_fb_data;
-#define imx21_add_imx_fb(pdata)	\
-	imx_add_imx_fb(&imx21_imx_fb_data, pdata)
-
-extern const struct imx_imx_i2c_data imx21_imx_i2c_data;
-#define imx21_add_imx_i2c(pdata)	\
-	imx_add_imx_i2c(&imx21_imx_i2c_data, pdata)
-
-extern const struct imx_imx_keypad_data imx21_imx_keypad_data;
-#define imx21_add_imx_keypad(pdata)	\
-	imx_add_imx_keypad(&imx21_imx_keypad_data, pdata)
-
-extern const struct imx_imx_ssi_data imx21_imx_ssi_data[];
-#define imx21_add_imx_ssi(id, pdata)	\
-	imx_add_imx_ssi(&imx21_imx_ssi_data[id], pdata)
-
-extern const struct imx_imx_uart_1irq_data imx21_imx_uart_data[];
-#define imx21_add_imx_uart(id, pdata)	\
-	imx_add_imx_uart_1irq(&imx21_imx_uart_data[id], pdata)
-#define imx21_add_imx_uart0(pdata)	imx21_add_imx_uart(0, pdata)
-#define imx21_add_imx_uart1(pdata)	imx21_add_imx_uart(1, pdata)
-#define imx21_add_imx_uart2(pdata)	imx21_add_imx_uart(2, pdata)
-#define imx21_add_imx_uart3(pdata)	imx21_add_imx_uart(3, pdata)
-
-extern const struct imx_mxc_mmc_data imx21_mxc_mmc_data[];
-#define imx21_add_mxc_mmc(id, pdata)	\
-	imx_add_mxc_mmc(&imx21_mxc_mmc_data[id], pdata)
-
-extern const struct imx_mxc_nand_data imx21_mxc_nand_data;
-#define imx21_add_mxc_nand(pdata)	\
-	imx_add_mxc_nand(&imx21_mxc_nand_data, pdata)
-
-extern const struct imx_mxc_w1_data imx21_mxc_w1_data;
-#define imx21_add_mxc_w1()	\
-	imx_add_mxc_w1(&imx21_mxc_w1_data)
-
-extern const struct imx_spi_imx_data imx21_cspi_data[];
-#define imx21_add_cspi(id, pdata)	\
-	imx_add_spi_imx(&imx21_cspi_data[id], pdata)
-#define imx21_add_spi_imx0(pdata)	imx21_add_cspi(0, pdata)
-#define imx21_add_spi_imx1(pdata)	imx21_add_cspi(1, pdata)
diff --git a/arch/arm/mach-imx/devices/Kconfig b/arch/arm/mach-imx/devices/Kconfig
index 6ffe572..fa23275 100644
--- a/arch/arm/mach-imx/devices/Kconfig
+++ b/arch/arm/mach-imx/devices/Kconfig
@@ -11,9 +11,6 @@ config IMX_HAVE_PLATFORM_FSL_USB2_UDC
 config IMX_HAVE_PLATFORM_GPIO_KEYS
 	bool
 
-config IMX_HAVE_PLATFORM_IMX21_HCD
-	bool
-
 config IMX_HAVE_PLATFORM_IMX27_CODA
 	bool
 	default y if SOC_IMX27
diff --git a/arch/arm/mach-imx/devices/Makefile b/arch/arm/mach-imx/devices/Makefile
index e44758a..c365eb9 100644
--- a/arch/arm/mach-imx/devices/Makefile
+++ b/arch/arm/mach-imx/devices/Makefile
@@ -6,7 +6,6 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC) += platform-fsl-usb2-udc.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS) += platform-gpio_keys.o
 obj-y += platform-gpio-mxc.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX21_HCD) += platform-imx21-hcd.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX27_CODA) += platform-imx27-coda.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT) += platform-imx2-wdt.o
 obj-y += platform-imx-dma.o
diff --git a/arch/arm/mach-imx/devices/devices-common.h b/arch/arm/mach-imx/devices/devices-common.h
index 6920e35..169b584 100644
--- a/arch/arm/mach-imx/devices/devices-common.h
+++ b/arch/arm/mach-imx/devices/devices-common.h
@@ -73,15 +73,6 @@ struct platform_device *__init imx_add_fsl_usb2_udc(
 struct platform_device *__init imx_add_gpio_keys(
 		const struct gpio_keys_platform_data *pdata);
 
-#include <linux/platform_data/usb-mx2.h>
-struct imx_imx21_hcd_data {
-	resource_size_t iobase;
-	resource_size_t irq;
-};
-struct platform_device *__init imx_add_imx21_hcd(
-		const struct imx_imx21_hcd_data *data,
-		const struct mx21_usbh_platform_data *pdata);
-
 struct imx_imx27_coda_data {
 	resource_size_t iobase;
 	resource_size_t iosize;
diff --git a/arch/arm/mach-imx/devices/platform-imx-fb.c b/arch/arm/mach-imx/devices/platform-imx-fb.c
index aa00272..4372862 100644
--- a/arch/arm/mach-imx/devices/platform-imx-fb.c
+++ b/arch/arm/mach-imx/devices/platform-imx-fb.c
@@ -19,11 +19,6 @@
 		.irq = soc ## _INT_LCDC,				\
 	}
 
-#ifdef CONFIG_SOC_IMX21
-const struct imx_imx_fb_data imx21_imx_fb_data __initconst =
-	imx_imx_fb_data_entry_single(MX21, "imx21-fb", SZ_4K);
-#endif /* ifdef CONFIG_SOC_IMX21 */
-
 #ifdef CONFIG_SOC_IMX27
 const struct imx_imx_fb_data imx27_imx_fb_data __initconst =
 	imx_imx_fb_data_entry_single(MX27, "imx21-fb", SZ_4K);
diff --git a/arch/arm/mach-imx/devices/platform-imx-i2c.c b/arch/arm/mach-imx/devices/platform-imx-i2c.c
index 9822bed..2d0ebe1 100644
--- a/arch/arm/mach-imx/devices/platform-imx-i2c.c
+++ b/arch/arm/mach-imx/devices/platform-imx-i2c.c
@@ -21,11 +21,6 @@
 #define imx_imx_i2c_data_entry(soc, _devid, _id, _hwid, _size)		\
 	[_id] = imx_imx_i2c_data_entry_single(soc, _devid, _id, _hwid, _size)
 
-#ifdef CONFIG_SOC_IMX21
-const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst =
-	imx_imx_i2c_data_entry_single(MX21, "imx21-i2c", 0, , SZ_4K);
-#endif /* ifdef CONFIG_SOC_IMX21 */
-
 #ifdef CONFIG_SOC_IMX27
 const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = {
 #define imx27_imx_i2c_data_entry(_id, _hwid)				\
diff --git a/arch/arm/mach-imx/devices/platform-imx-keypad.c b/arch/arm/mach-imx/devices/platform-imx-keypad.c
index 479e4d7..74caf1f 100644
--- a/arch/arm/mach-imx/devices/platform-imx-keypad.c
+++ b/arch/arm/mach-imx/devices/platform-imx-keypad.c
@@ -16,11 +16,6 @@
 		.irq = soc ## _INT_KPP,					\
 	}
 
-#ifdef CONFIG_SOC_IMX21
-const struct imx_imx_keypad_data imx21_imx_keypad_data __initconst =
-	imx_imx_keypad_data_entry_single(MX21, SZ_16);
-#endif /* ifdef CONFIG_SOC_IMX21 */
-
 #ifdef CONFIG_SOC_IMX27
 const struct imx_imx_keypad_data imx27_imx_keypad_data __initconst =
 	imx_imx_keypad_data_entry_single(MX27, SZ_16);
diff --git a/arch/arm/mach-imx/devices/platform-imx-ssi.c b/arch/arm/mach-imx/devices/platform-imx-ssi.c
index 6f0e94e..24a44ea 100644
--- a/arch/arm/mach-imx/devices/platform-imx-ssi.c
+++ b/arch/arm/mach-imx/devices/platform-imx-ssi.c
@@ -21,15 +21,6 @@
 		.dmarx1 = soc ## _DMA_REQ_SSI ## _hwid ## _RX1,		\
 	}
 
-#ifdef CONFIG_SOC_IMX21
-const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst = {
-#define imx21_imx_ssi_data_entry(_id, _hwid)				\
-	imx_imx_ssi_data_entry(MX21, _id, _hwid, SZ_4K)
-	imx21_imx_ssi_data_entry(0, 1),
-	imx21_imx_ssi_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX21 */
-
 #ifdef CONFIG_SOC_IMX27
 const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst = {
 #define imx27_imx_ssi_data_entry(_id, _hwid)				\
diff --git a/arch/arm/mach-imx/devices/platform-imx-uart.c b/arch/arm/mach-imx/devices/platform-imx-uart.c
index e3c89e9..25aa6c4 100644
--- a/arch/arm/mach-imx/devices/platform-imx-uart.c
+++ b/arch/arm/mach-imx/devices/platform-imx-uart.c
@@ -27,17 +27,6 @@
 		.irq = soc ## _INT_UART ## _hwid,			\
 	}
 
-#ifdef CONFIG_SOC_IMX21
-const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst = {
-#define imx21_imx_uart_data_entry(_id, _hwid)				\
-	imx_imx_uart_1irq_data_entry(MX21, _id, _hwid, SZ_4K)
-	imx21_imx_uart_data_entry(0, 1),
-	imx21_imx_uart_data_entry(1, 2),
-	imx21_imx_uart_data_entry(2, 3),
-	imx21_imx_uart_data_entry(3, 4),
-};
-#endif
-
 #ifdef CONFIG_SOC_IMX27
 const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst = {
 #define imx27_imx_uart_data_entry(_id, _hwid)				\
diff --git a/arch/arm/mach-imx/devices/platform-imx2-wdt.c b/arch/arm/mach-imx/devices/platform-imx2-wdt.c
index 8c134c8..1f8ce02 100644
--- a/arch/arm/mach-imx/devices/platform-imx2-wdt.c
+++ b/arch/arm/mach-imx/devices/platform-imx2-wdt.c
@@ -20,11 +20,6 @@
 #define imx_imx2_wdt_data_entry(soc, _id, _hwid, _size)			\
 	[_id] = imx_imx2_wdt_data_entry_single(soc, _id, _hwid, _size)
 
-#ifdef CONFIG_SOC_IMX21
-const struct imx_imx2_wdt_data imx21_imx2_wdt_data __initconst =
-	imx_imx2_wdt_data_entry_single(MX21, 0, , SZ_4K);
-#endif /* ifdef CONFIG_SOC_IMX21 */
-
 #ifdef CONFIG_SOC_IMX27
 const struct imx_imx2_wdt_data imx27_imx2_wdt_data __initconst =
 	imx_imx2_wdt_data_entry_single(MX27, 0, , SZ_4K);
diff --git a/arch/arm/mach-imx/devices/platform-imx21-hcd.c b/arch/arm/mach-imx/devices/platform-imx21-hcd.c
deleted file mode 100644
index 30c8161..0000000
--- a/arch/arm/mach-imx/devices/platform-imx21-hcd.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_imx21_hcd_data_entry_single(soc)				\
-	{								\
-		.iobase = soc ## _USBOTG_BASE_ADDR,			\
-		.irq = soc ## _INT_USBHOST,				\
-	}
-
-#ifdef CONFIG_SOC_IMX21
-const struct imx_imx21_hcd_data imx21_imx21_hcd_data __initconst =
-	imx_imx21_hcd_data_entry_single(MX21);
-#endif /* ifdef CONFIG_SOC_IMX21 */
-
-struct platform_device *__init imx_add_imx21_hcd(
-		const struct imx_imx21_hcd_data *data,
-		const struct mx21_usbh_platform_data *pdata)
-{
-	struct resource res[] = {
-		{
-			.start = data->iobase,
-			.end = data->iobase + SZ_8K - 1,
-			.flags = IORESOURCE_MEM,
-		}, {
-			.start = data->irq,
-			.end = data->irq,
-			.flags = IORESOURCE_IRQ,
-		},
-	};
-	return imx_add_platform_device_dmamask("imx21-hcd", 0,
-			res, ARRAY_SIZE(res),
-			pdata, sizeof(*pdata), DMA_BIT_MASK(32));
-}
diff --git a/arch/arm/mach-imx/devices/platform-mxc-mmc.c b/arch/arm/mach-imx/devices/platform-mxc-mmc.c
index b8203c7..c4ef45f 100644
--- a/arch/arm/mach-imx/devices/platform-mxc-mmc.c
+++ b/arch/arm/mach-imx/devices/platform-mxc-mmc.c
@@ -23,15 +23,6 @@
 #define imx_mxc_mmc_data_entry(soc, _devid, _id, _hwid, _size)		\
 	[_id] = imx_mxc_mmc_data_entry_single(soc, _devid, _id, _hwid, _size)
 
-#ifdef CONFIG_SOC_IMX21
-const struct imx_mxc_mmc_data imx21_mxc_mmc_data[] __initconst = {
-#define imx21_mxc_mmc_data_entry(_id, _hwid)				\
-	imx_mxc_mmc_data_entry(MX21, "imx21-mmc", _id, _hwid, SZ_4K)
-	imx21_mxc_mmc_data_entry(0, 1),
-	imx21_mxc_mmc_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX21 */
-
 #ifdef CONFIG_SOC_IMX27
 const struct imx_mxc_mmc_data imx27_mxc_mmc_data[] __initconst = {
 #define imx27_mxc_mmc_data_entry(_id, _hwid)				\
diff --git a/arch/arm/mach-imx/devices/platform-mxc_nand.c b/arch/arm/mach-imx/devices/platform-mxc_nand.c
index 676df49..c628927 100644
--- a/arch/arm/mach-imx/devices/platform-mxc_nand.c
+++ b/arch/arm/mach-imx/devices/platform-mxc_nand.c
@@ -29,11 +29,6 @@
 		.irq = soc ## _INT_NFC					\
 	}
 
-#ifdef CONFIG_SOC_IMX21
-const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst =
-	imx_mxc_nand_data_entry_single(MX21, "imx21-nand", SZ_4K);
-#endif /* ifdef CONFIG_SOC_IMX21 */
-
 #ifdef CONFIG_SOC_IMX27
 const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst =
 	imx_mxc_nand_data_entry_single(MX27, "imx27-nand", SZ_4K);
diff --git a/arch/arm/mach-imx/devices/platform-mxc_w1.c b/arch/arm/mach-imx/devices/platform-mxc_w1.c
index 88c18b7..fefe006 100644
--- a/arch/arm/mach-imx/devices/platform-mxc_w1.c
+++ b/arch/arm/mach-imx/devices/platform-mxc_w1.c
@@ -14,11 +14,6 @@
 		.iobase = soc ## _OWIRE_BASE_ADDR,			\
 	}
 
-#ifdef CONFIG_SOC_IMX21
-const struct imx_mxc_w1_data imx21_mxc_w1_data __initconst =
-	imx_mxc_w1_data_entry_single(MX21);
-#endif /* ifdef CONFIG_SOC_IMX21 */
-
 #ifdef CONFIG_SOC_IMX27
 const struct imx_mxc_w1_data imx27_mxc_w1_data __initconst =
 	imx_mxc_w1_data_entry_single(MX27);
diff --git a/arch/arm/mach-imx/devices/platform-spi_imx.c b/arch/arm/mach-imx/devices/platform-spi_imx.c
index d93c446..21de5bb 100644
--- a/arch/arm/mach-imx/devices/platform-spi_imx.c
+++ b/arch/arm/mach-imx/devices/platform-spi_imx.c
@@ -21,15 +21,6 @@
 #define imx_spi_imx_data_entry(soc, type, devid, id, hwid, size)	\
 	[id] = imx_spi_imx_data_entry_single(soc, type, devid, id, hwid, size)
 
-#ifdef CONFIG_SOC_IMX21
-const struct imx_spi_imx_data imx21_cspi_data[] __initconst = {
-#define imx21_cspi_data_entry(_id, _hwid)                            \
-	imx_spi_imx_data_entry(MX21, CSPI, "imx21-cspi", _id, _hwid, SZ_4K)
-	imx21_cspi_data_entry(0, 1),
-	imx21_cspi_data_entry(1, 2),
-};
-#endif
-
 #ifdef CONFIG_SOC_IMX27
 const struct imx_spi_imx_data imx27_cspi_data[] __initconst = {
 #define imx27_cspi_data_entry(_id, _hwid)				\
diff --git a/arch/arm/mach-imx/hardware.h b/arch/arm/mach-imx/hardware.h
index 90e10cb..8fcb633 100644
--- a/arch/arm/mach-imx/hardware.h
+++ b/arch/arm/mach-imx/hardware.h
@@ -110,7 +110,6 @@
 #include "mx31.h"
 #include "mx35.h"
 #include "mx2x.h"
-#include "mx21.h"
 #include "mx27.h"
 
 #define imx_map_entry(soc, name, _type)	{				\
diff --git a/arch/arm/mach-imx/iomux-mx21.h b/arch/arm/mach-imx/iomux-mx21.h
deleted file mode 100644
index a70cffc..0000000
--- a/arch/arm/mach-imx/iomux-mx21.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-#ifndef __MACH_IOMUX_MX21_H__
-#define __MACH_IOMUX_MX21_H__
-
-#include "iomux-mx2x.h"
-#include "iomux-v1.h"
-
-/* Primary GPIO pin functions */
-
-#define PB22_PF_USBH1_BYP	(GPIO_PORTB | GPIO_PF | 22)
-#define PB25_PF_USBH1_ON	(GPIO_PORTB | GPIO_PF | 25)
-#define PC5_PF_USBOTG_SDA	(GPIO_PORTC | GPIO_PF | 5)
-#define PC6_PF_USBOTG_SCL	(GPIO_PORTC | GPIO_PF | 6)
-#define PC7_PF_USBOTG_ON	(GPIO_PORTC | GPIO_PF | 7)
-#define PC8_PF_USBOTG_FS	(GPIO_PORTC | GPIO_PF | 8)
-#define PC9_PF_USBOTG_OE	(GPIO_PORTC | GPIO_PF | 9)
-#define PC10_PF_USBOTG_TXDM	(GPIO_PORTC | GPIO_PF | 10)
-#define PC11_PF_USBOTG_TXDP	(GPIO_PORTC | GPIO_PF | 11)
-#define PC12_PF_USBOTG_RXDM	(GPIO_PORTC | GPIO_PF | 12)
-#define PC13_PF_USBOTG_RXDP	(GPIO_PORTC | GPIO_PF | 13)
-#define PC16_PF_SAP_FS		(GPIO_PORTC | GPIO_PF | 16)
-#define PC17_PF_SAP_RXD		(GPIO_PORTC | GPIO_PF | 17)
-#define PC18_PF_SAP_TXD		(GPIO_PORTC | GPIO_PF | 18)
-#define PC19_PF_SAP_CLK		(GPIO_PORTC | GPIO_PF | 19)
-#define PE0_PF_TEST_WB2		(GPIO_PORTE | GPIO_PF | 0)
-#define PE1_PF_TEST_WB1		(GPIO_PORTE | GPIO_PF | 1)
-#define PE2_PF_TEST_WB0		(GPIO_PORTE | GPIO_PF | 2)
-#define PF1_PF_NFCE		(GPIO_PORTF | GPIO_PF | 1)
-#define PF3_PF_NFCLE		(GPIO_PORTF | GPIO_PF | 3)
-#define PF7_PF_NFIO0		(GPIO_PORTF | GPIO_PF | 7)
-#define PF8_PF_NFIO1		(GPIO_PORTF | GPIO_PF | 8)
-#define PF9_PF_NFIO2		(GPIO_PORTF | GPIO_PF | 9)
-#define PF10_PF_NFIO3		(GPIO_PORTF | GPIO_PF | 10)
-#define PF11_PF_NFIO4		(GPIO_PORTF | GPIO_PF | 11)
-#define PF12_PF_NFIO5		(GPIO_PORTF | GPIO_PF | 12)
-#define PF13_PF_NFIO6		(GPIO_PORTF | GPIO_PF | 13)
-#define PF14_PF_NFIO7		(GPIO_PORTF | GPIO_PF | 14)
-#define PF16_PF_RES		(GPIO_PORTF | GPIO_PF | 16)
-
-/* Alternate GPIO pin functions */
-
-#define PA5_AF_BMI_CLK_CS	(GPIO_PORTA | GPIO_AF | 5)
-#define PA6_AF_BMI_D0		(GPIO_PORTA | GPIO_AF | 6)
-#define PA7_AF_BMI_D1		(GPIO_PORTA | GPIO_AF | 7)
-#define PA8_AF_BMI_D2		(GPIO_PORTA | GPIO_AF | 8)
-#define PA9_AF_BMI_D3		(GPIO_PORTA | GPIO_AF | 9)
-#define PA10_AF_BMI_D4		(GPIO_PORTA | GPIO_AF | 10)
-#define PA11_AF_BMI_D5		(GPIO_PORTA | GPIO_AF | 11)
-#define PA12_AF_BMI_D6		(GPIO_PORTA | GPIO_AF | 12)
-#define PA13_AF_BMI_D7		(GPIO_PORTA | GPIO_AF | 13)
-#define PA14_AF_BMI_D8		(GPIO_PORTA | GPIO_AF | 14)
-#define PA15_AF_BMI_D9		(GPIO_PORTA | GPIO_AF | 15)
-#define PA16_AF_BMI_D10		(GPIO_PORTA | GPIO_AF | 16)
-#define PA17_AF_BMI_D11		(GPIO_PORTA | GPIO_AF | 17)
-#define PA18_AF_BMI_D12		(GPIO_PORTA | GPIO_AF | 18)
-#define PA19_AF_BMI_D13		(GPIO_PORTA | GPIO_AF | 19)
-#define PA20_AF_BMI_D14		(GPIO_PORTA | GPIO_AF | 20)
-#define PA21_AF_BMI_D15		(GPIO_PORTA | GPIO_AF | 21)
-#define PA22_AF_BMI_READ_REQ	(GPIO_PORTA | GPIO_AF | 22)
-#define PA23_AF_BMI_WRITE	(GPIO_PORTA | GPIO_AF | 23)
-#define PA29_AF_BMI_RX_FULL	(GPIO_PORTA | GPIO_AF | 29)
-#define PA30_AF_BMI_READ	(GPIO_PORTA | GPIO_AF | 30)
-
-/* AIN GPIO pin functions */
-
-#define PC14_AIN_SYS_CLK	(GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14)
-#define PD21_AIN_USBH2_FS	(GPIO_PORTD | GPIO_AIN | GPIO_OUT | 21)
-#define PD22_AIN_USBH2_OE	(GPIO_PORTD | GPIO_AIN | GPIO_OUT | 22)
-#define PD23_AIN_USBH2_TXDM	(GPIO_PORTD | GPIO_AIN | GPIO_OUT | 23)
-#define PD24_AIN_USBH2_TXDP	(GPIO_PORTD | GPIO_AIN | GPIO_OUT | 24)
-#define PE8_AIN_IR_TXD		(GPIO_PORTE | GPIO_AIN | GPIO_OUT | 8)
-#define PF0_AIN_PC_RST		(GPIO_PORTF | GPIO_AIN | GPIO_OUT | 0)
-#define PF1_AIN_PC_CE1		(GPIO_PORTF | GPIO_AIN | GPIO_OUT | 1)
-#define PF2_AIN_PC_CE2		(GPIO_PORTF | GPIO_AIN | GPIO_OUT | 2)
-#define PF3_AIN_PC_POE		(GPIO_PORTF | GPIO_AIN | GPIO_OUT | 3)
-#define PF4_AIN_PC_OE		(GPIO_PORTF | GPIO_AIN | GPIO_OUT | 4)
-#define PF5_AIN_PC_RW		(GPIO_PORTF | GPIO_AIN | GPIO_OUT | 5)
-
-/* BIN GPIO pin functions */
-
-#define PC14_BIN_SYS_CLK	(GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14)
-#define PD27_BIN_EXT_DMA_GRANT	(GPIO_PORTD | GPIO_BIN | GPIO_OUT | 27)
-
-/* CIN GPIO pin functions */
-
-#define PB26_CIN_USBH1_RXDAT	(GPIO_PORTB | GPIO_CIN | GPIO_OUT | 26)
-
-/* AOUT GPIO pin functions */
-
-#define PA29_AOUT_BMI_WAIT	(GPIO_PORTA | GPIO_AOUT | GPIO_IN | 29)
-#define PD19_AOUT_USBH2_RXDM	(GPIO_PORTD | GPIO_AOUT | GPIO_IN | 19)
-#define PD20_AOUT_USBH2_RXDP	(GPIO_PORTD | GPIO_AOUT | GPIO_IN | 20)
-#define PD25_AOUT_EXT_DMAREQ	(GPIO_PORTD | GPIO_AOUT | GPIO_IN | 25)
-#define PD26_AOUT_USBOTG_RXDAT	(GPIO_PORTD | GPIO_AOUT | GPIO_IN | 26)
-#define PE9_AOUT_IR_RXD		(GPIO_PORTE | GPIO_AOUT | GPIO_IN | 9)
-#define PF6_AOUT_PC_BVD2	(GPIO_PORTF | GPIO_AOUT | GPIO_IN | 6)
-#define PF7_AOUT_PC_BVD1	(GPIO_PORTF | GPIO_AOUT | GPIO_IN | 7)
-#define PF8_AOUT_PC_VS2		(GPIO_PORTF | GPIO_AOUT | GPIO_IN | 8)
-#define PF9_AOUT_PC_VS1		(GPIO_PORTF | GPIO_AOUT | GPIO_IN | 9)
-#define PF10_AOUT_PC_WP		(GPIO_PORTF | GPIO_AOUT | GPIO_IN | 10)
-#define PF11_AOUT_PC_READY	(GPIO_PORTF | GPIO_AOUT | GPIO_IN | 11)
-#define PF12_AOUT_PC_WAIT	(GPIO_PORTF | GPIO_AOUT | GPIO_IN | 12)
-#define PF13_AOUT_PC_CD2	(GPIO_PORTF | GPIO_AOUT | GPIO_IN | 13)
-#define PF14_AOUT_PC_CD1	(GPIO_PORTF | GPIO_AOUT | GPIO_IN | 14)
-
-#endif /* ifndef __MACH_IOMUX_MX21_H__ */
diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c
deleted file mode 100644
index 2e91ab2..0000000
--- a/arch/arm/mach-imx/mm-imx21.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * arch/arm/mach-imx/mm-imx21.c
- *
- * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/mm.h>
-#include <linux/init.h>
-#include <linux/pinctrl/machine.h>
-#include <asm/pgtable.h>
-#include <asm/mach/map.h>
-
-#include "common.h"
-#include "devices/devices-common.h"
-#include "hardware.h"
-#include "iomux-v1.h"
-
-/* MX21 memory map definition */
-static struct map_desc imx21_io_desc[] __initdata = {
-	/*
-	 * this fixed mapping covers:
-	 * - AIPI1
-	 * - AIPI2
-	 * - AITC
-	 * - ROM Patch
-	 * - and some reserved space
-	 */
-	imx_map_entry(MX21, AIPI, MT_DEVICE),
-	/*
-	 * this fixed mapping covers:
-	 * - CSI
-	 * - ATA
-	 */
-	imx_map_entry(MX21, SAHB1, MT_DEVICE),
-	/*
-	 * this fixed mapping covers:
-	 * - EMI
-	 */
-	imx_map_entry(MX21, X_MEMC, MT_DEVICE),
-};
-
-/*
- * Initialize the memory map. It is called during the
- * system startup to create static physical to virtual
- * memory map for the IO modules.
- */
-void __init mx21_map_io(void)
-{
-	iotable_init(imx21_io_desc, ARRAY_SIZE(imx21_io_desc));
-}
-
-void __init imx21_init_early(void)
-{
-	mxc_set_cpu_type(MXC_CPU_MX21);
-	imx_iomuxv1_init(MX21_IO_ADDRESS(MX21_GPIO_BASE_ADDR),
-			MX21_NUM_GPIO_PORT);
-}
-
-void __init mx21_init_irq(void)
-{
-	mxc_init_irq(MX21_IO_ADDRESS(MX21_AVIC_BASE_ADDR));
-}
-
-static const struct resource imx21_audmux_res[] __initconst = {
-	DEFINE_RES_MEM(MX21_AUDMUX_BASE_ADDR, SZ_4K),
-};
-
-void __init imx21_soc_init(void)
-{
-	mxc_arch_reset_init(MX21_IO_ADDRESS(MX21_WDOG_BASE_ADDR));
-	mxc_device_init();
-
-	mxc_register_gpio("imx21-gpio", 0, MX21_GPIO1_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
-	mxc_register_gpio("imx21-gpio", 1, MX21_GPIO2_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
-	mxc_register_gpio("imx21-gpio", 2, MX21_GPIO3_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
-	mxc_register_gpio("imx21-gpio", 3, MX21_GPIO4_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
-	mxc_register_gpio("imx21-gpio", 4, MX21_GPIO5_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
-	mxc_register_gpio("imx21-gpio", 5, MX21_GPIO6_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
-
-	pinctrl_provide_dummies();
-	imx_add_imx_dma("imx21-dma", MX21_DMA_BASE_ADDR,
-			MX21_INT_DMACH0, 0); /* No ERR irq */
-	platform_device_register_simple("imx21-audmux", 0, imx21_audmux_res,
-					ARRAY_SIZE(imx21_audmux_res));
-}
diff --git a/arch/arm/mach-imx/mx21.h b/arch/arm/mach-imx/mx21.h
deleted file mode 100644
index 468738a..0000000
--- a/arch/arm/mach-imx/mx21.h
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- * Copyright 2009 Holger Schurig, hs4233@mail.mn-solutions.de
- *
- * This contains i.MX21-specific hardware definitions. For those
- * hardware pieces that are common between i.MX21 and i.MX27, have a
- * look at mx2x.h.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA  02110-1301, USA.
- */
-
-#ifndef __MACH_MX21_H__
-#define __MACH_MX21_H__
-
-#define MX21_AIPI_BASE_ADDR		0x10000000
-#define MX21_AIPI_SIZE			SZ_1M
-#define MX21_DMA_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x01000)
-#define MX21_WDOG_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x02000)
-#define MX21_GPT1_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x03000)
-#define MX21_GPT2_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x04000)
-#define MX21_GPT3_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x05000)
-#define MX21_PWM_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x06000)
-#define MX21_RTC_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x07000)
-#define MX21_KPP_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x08000)
-#define MX21_OWIRE_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x09000)
-#define MX21_UART1_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x0a000)
-#define MX21_UART2_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x0b000)
-#define MX21_UART3_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x0c000)
-#define MX21_UART4_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x0d000)
-#define MX21_CSPI1_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x0e000)
-#define MX21_CSPI2_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x0f000)
-#define MX21_SSI1_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x10000)
-#define MX21_SSI2_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x11000)
-#define MX21_I2C_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x12000)
-#define MX21_SDHC1_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x13000)
-#define MX21_SDHC2_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x14000)
-#define MX21_GPIO_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x15000)
-#define MX21_GPIO1_BASE_ADDR			(MX21_GPIO_BASE_ADDR + 0x000)
-#define MX21_GPIO2_BASE_ADDR			(MX21_GPIO_BASE_ADDR + 0x100)
-#define MX21_GPIO3_BASE_ADDR			(MX21_GPIO_BASE_ADDR + 0x200)
-#define MX21_GPIO4_BASE_ADDR			(MX21_GPIO_BASE_ADDR + 0x300)
-#define MX21_GPIO5_BASE_ADDR			(MX21_GPIO_BASE_ADDR + 0x400)
-#define MX21_GPIO6_BASE_ADDR			(MX21_GPIO_BASE_ADDR + 0x500)
-#define MX21_AUDMUX_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x16000)
-#define MX21_CSPI3_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x17000)
-#define MX21_LCDC_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x21000)
-#define MX21_SLCDC_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x22000)
-#define MX21_USBOTG_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x24000)
-#define MX21_EMMA_PP_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x26000)
-#define MX21_EMMA_PRP_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x26400)
-#define MX21_CCM_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x27000)
-#define MX21_SYSCTRL_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x27800)
-#define MX21_JAM_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x3e000)
-#define MX21_MAX_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x3f000)
-
-#define MX21_AVIC_BASE_ADDR		0x10040000
-
-#define MX21_SAHB1_BASE_ADDR		0x80000000
-#define MX21_SAHB1_SIZE			SZ_1M
-#define MX21_CSI_BASE_ADDR			(MX2x_SAHB1_BASE_ADDR + 0x0000)
-
-/* Memory regions and CS */
-#define MX21_SDRAM_BASE_ADDR		0xc0000000
-#define MX21_CSD1_BASE_ADDR		0xc4000000
-
-#define MX21_CS0_BASE_ADDR		0xc8000000
-#define MX21_CS1_BASE_ADDR		0xcc000000
-#define MX21_CS2_BASE_ADDR		0xd0000000
-#define MX21_CS3_BASE_ADDR		0xd1000000
-#define MX21_CS4_BASE_ADDR		0xd2000000
-#define MX21_PCMCIA_MEM_BASE_ADDR	0xd4000000
-#define MX21_CS5_BASE_ADDR		0xdd000000
-
-/* NAND, SDRAM, WEIM etc controllers */
-#define MX21_X_MEMC_BASE_ADDR		0xdf000000
-#define MX21_X_MEMC_SIZE		SZ_256K
-
-#define MX21_SDRAMC_BASE_ADDR		(MX21_X_MEMC_BASE_ADDR + 0x0000)
-#define MX21_EIM_BASE_ADDR		(MX21_X_MEMC_BASE_ADDR + 0x1000)
-#define MX21_PCMCIA_CTL_BASE_ADDR	(MX21_X_MEMC_BASE_ADDR + 0x2000)
-#define MX21_NFC_BASE_ADDR		(MX21_X_MEMC_BASE_ADDR + 0x3000)
-
-#define MX21_IRAM_BASE_ADDR		0xffffe800	/* internal ram */
-
-#define MX21_IO_P2V(x)			IMX_IO_P2V(x)
-#define MX21_IO_ADDRESS(x)		IOMEM(MX21_IO_P2V(x))
-
-/* fixed interrupt numbers */
-#include <asm/irq.h>
-#define MX21_INT_CSPI3		(NR_IRQS_LEGACY + 6)
-#define MX21_INT_GPIO		(NR_IRQS_LEGACY + 8)
-#define MX21_INT_FIRI		(NR_IRQS_LEGACY + 9)
-#define MX21_INT_SDHC2		(NR_IRQS_LEGACY + 10)
-#define MX21_INT_SDHC1		(NR_IRQS_LEGACY + 11)
-#define MX21_INT_I2C		(NR_IRQS_LEGACY + 12)
-#define MX21_INT_SSI2		(NR_IRQS_LEGACY + 13)
-#define MX21_INT_SSI1		(NR_IRQS_LEGACY + 14)
-#define MX21_INT_CSPI2		(NR_IRQS_LEGACY + 15)
-#define MX21_INT_CSPI1		(NR_IRQS_LEGACY + 16)
-#define MX21_INT_UART4		(NR_IRQS_LEGACY + 17)
-#define MX21_INT_UART3		(NR_IRQS_LEGACY + 18)
-#define MX21_INT_UART2		(NR_IRQS_LEGACY + 19)
-#define MX21_INT_UART1		(NR_IRQS_LEGACY + 20)
-#define MX21_INT_KPP		(NR_IRQS_LEGACY + 21)
-#define MX21_INT_RTC		(NR_IRQS_LEGACY + 22)
-#define MX21_INT_PWM		(NR_IRQS_LEGACY + 23)
-#define MX21_INT_GPT3		(NR_IRQS_LEGACY + 24)
-#define MX21_INT_GPT2		(NR_IRQS_LEGACY + 25)
-#define MX21_INT_GPT1		(NR_IRQS_LEGACY + 26)
-#define MX21_INT_WDOG		(NR_IRQS_LEGACY + 27)
-#define MX21_INT_PCMCIA		(NR_IRQS_LEGACY + 28)
-#define MX21_INT_NFC		(NR_IRQS_LEGACY + 29)
-#define MX21_INT_BMI		(NR_IRQS_LEGACY + 30)
-#define MX21_INT_CSI		(NR_IRQS_LEGACY + 31)
-#define MX21_INT_DMACH0		(NR_IRQS_LEGACY + 32)
-#define MX21_INT_DMACH1		(NR_IRQS_LEGACY + 33)
-#define MX21_INT_DMACH2		(NR_IRQS_LEGACY + 34)
-#define MX21_INT_DMACH3		(NR_IRQS_LEGACY + 35)
-#define MX21_INT_DMACH4		(NR_IRQS_LEGACY + 36)
-#define MX21_INT_DMACH5		(NR_IRQS_LEGACY + 37)
-#define MX21_INT_DMACH6		(NR_IRQS_LEGACY + 38)
-#define MX21_INT_DMACH7		(NR_IRQS_LEGACY + 39)
-#define MX21_INT_DMACH8		(NR_IRQS_LEGACY + 40)
-#define MX21_INT_DMACH9		(NR_IRQS_LEGACY + 41)
-#define MX21_INT_DMACH10	(NR_IRQS_LEGACY + 42)
-#define MX21_INT_DMACH11	(NR_IRQS_LEGACY + 43)
-#define MX21_INT_DMACH12	(NR_IRQS_LEGACY + 44)
-#define MX21_INT_DMACH13	(NR_IRQS_LEGACY + 45)
-#define MX21_INT_DMACH14	(NR_IRQS_LEGACY + 46)
-#define MX21_INT_DMACH15	(NR_IRQS_LEGACY + 47)
-#define MX21_INT_EMMAENC	(NR_IRQS_LEGACY + 49)
-#define MX21_INT_EMMADEC	(NR_IRQS_LEGACY + 50)
-#define MX21_INT_EMMAPRP	(NR_IRQS_LEGACY + 51)
-#define MX21_INT_EMMAPP		(NR_IRQS_LEGACY + 52)
-#define MX21_INT_USBWKUP	(NR_IRQS_LEGACY + 53)
-#define MX21_INT_USBDMA		(NR_IRQS_LEGACY + 54)
-#define MX21_INT_USBHOST	(NR_IRQS_LEGACY + 55)
-#define MX21_INT_USBFUNC	(NR_IRQS_LEGACY + 56)
-#define MX21_INT_USBMNP		(NR_IRQS_LEGACY + 57)
-#define MX21_INT_USBCTRL	(NR_IRQS_LEGACY + 58)
-#define MX21_INT_SLCDC		(NR_IRQS_LEGACY + 60)
-#define MX21_INT_LCDC		(NR_IRQS_LEGACY + 61)
-
-/* fixed DMA request numbers */
-#define MX21_DMA_REQ_CSPI3_RX	1
-#define MX21_DMA_REQ_CSPI3_TX	2
-#define MX21_DMA_REQ_EXT	3
-#define MX21_DMA_REQ_FIRI_RX	4
-#define MX21_DMA_REQ_SDHC2	6
-#define MX21_DMA_REQ_SDHC1	7
-#define MX21_DMA_REQ_SSI2_RX0	8
-#define MX21_DMA_REQ_SSI2_TX0	9
-#define MX21_DMA_REQ_SSI2_RX1	10
-#define MX21_DMA_REQ_SSI2_TX1	11
-#define MX21_DMA_REQ_SSI1_RX0	12
-#define MX21_DMA_REQ_SSI1_TX0	13
-#define MX21_DMA_REQ_SSI1_RX1	14
-#define MX21_DMA_REQ_SSI1_TX1	15
-#define MX21_DMA_REQ_CSPI2_RX	16
-#define MX21_DMA_REQ_CSPI2_TX	17
-#define MX21_DMA_REQ_CSPI1_RX	18
-#define MX21_DMA_REQ_CSPI1_TX	19
-#define MX21_DMA_REQ_UART4_RX	20
-#define MX21_DMA_REQ_UART4_TX	21
-#define MX21_DMA_REQ_UART3_RX	22
-#define MX21_DMA_REQ_UART3_TX	23
-#define MX21_DMA_REQ_UART2_RX	24
-#define MX21_DMA_REQ_UART2_TX	25
-#define MX21_DMA_REQ_UART1_RX	26
-#define MX21_DMA_REQ_UART1_TX	27
-#define MX21_DMA_REQ_BMI_TX	28
-#define MX21_DMA_REQ_BMI_RX	29
-#define MX21_DMA_REQ_CSI_STAT	30
-#define MX21_DMA_REQ_CSI_RX	31
-
-#endif /* ifndef __MACH_MX21_H__ */
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c
index c06af65..8ef3a1b 100644
--- a/arch/arm/mach-imx/system.c
+++ b/arch/arm/mach-imx/system.c
@@ -83,14 +83,6 @@ void __init mxc_arch_reset_init(void __iomem *base)
 		clk_prepare(wdog_clk);
 }
 
-#ifdef CONFIG_SOC_IMX1
-void __init imx1_reset_init(void __iomem *base)
-{
-	wcr_enable = (1 << 0);
-	mxc_arch_reset_init(base);
-}
-#endif
-
 #ifdef CONFIG_CACHE_L2X0
 void __init imx_init_l2cache(void)
 {
-- 
2.10.2


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^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH 2/6] ARM i.MX21: Add devicetree support
  2018-12-22 10:51 ` [PATCH 2/6] ARM i.MX21: Add devicetree support Alexander Shiyan
@ 2019-01-12  2:53   ` Shawn Guo
  2019-01-12  5:17     ` Alexander Shiyan
  0 siblings, 1 reply; 9+ messages in thread
From: Shawn Guo @ 2019-01-12  2:53 UTC (permalink / raw)
  To: Alexander Shiyan
  Cc: Pengutronix Kernel Team, Fabio Estevam, Russell King,
	linux-arm-kernel, NXP Linux Team

On Sat, Dec 22, 2018 at 01:51:56PM +0300, Alexander Shiyan wrote:
> This patch adds basic devicetree support for i.MX21 based SoCs.
> 
> Signed-off-by: Alexander Shiyan <shc_work@mail.ru>

What i.MX21 board are you running devicetree support on?

Shawn

> ---
>  arch/arm/mach-imx/Kconfig      |  7 +++++++
>  arch/arm/mach-imx/Makefile     |  1 +
>  arch/arm/mach-imx/mach-imx21.c | 31 +++++++++++++++++++++++++++++++
>  3 files changed, 39 insertions(+)
>  create mode 100644 arch/arm/mach-imx/mach-imx21.c
> 
> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> index abc3371..abf3c0d 100644
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -91,6 +91,13 @@ config MACH_MX21ADS
>  	  Include support for MX21ADS platform. This includes specific
>  	  configurations for the board and its peripherals.
>  
> +config MACH_IMX21_DT
> +	bool "Support i.MX21 platforms from device tree"
> +	select SOC_IMX21
> +	help
> +	  Include support for Freescale i.MX21 based platforms
> +	  using the device tree for discovery
> +
>  comment "MX27 platforms:"
>  
>  config MACH_MX27ADS
> diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
> index bae179a..52a9138 100644
> --- a/arch/arm/mach-imx/Makefile
> +++ b/arch/arm/mach-imx/Makefile
> @@ -38,6 +38,7 @@ endif
>  
>  # i.MX21 based machines
>  obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
> +obj-$(CONFIG_MACH_IMX21_DT) += mach-imx21.o
>  
>  # i.MX27 based machines
>  obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
> diff --git a/arch/arm/mach-imx/mach-imx21.c b/arch/arm/mach-imx/mach-imx21.c
> new file mode 100644
> index 0000000..7eb7de0
> --- /dev/null
> +++ b/arch/arm/mach-imx/mach-imx21.c
> @@ -0,0 +1,31 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/* Author: Alexander Shiyan <shc_work@mail.ru> */
> +
> +#include <asm/mach/arch.h>
> +#include <asm/mach/map.h>
> +#include <linux/of_platform.h>
> +
> +#include "common.h"
> +#include "hardware.h"
> +
> +#define MX21_AVIC_ADDR	0x10040000
> +
> +static void __init imx21_init_irq(void)
> +{
> +	void __iomem *avic = ioremap(MX21_AVIC_ADDR, SZ_4K);
> +
> +	WARN_ON(!avic);
> +
> +	mxc_init_irq(avic);
> +}
> +
> +static const char * const imx21_dt_board_compat[] __initconst = {
> +	"fsl,imx21",
> +	NULL
> +};
> +
> +DT_MACHINE_START(IMX21_DT, "Freescale i.MX21 (Device Tree Support)")
> +	.init_early	= imx21_init_early,
> +	.init_irq	= imx21_init_irq,
> +	.dt_compat	= imx21_dt_board_compat,
> +MACHINE_END
> -- 
> 2.10.2
> 

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^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH 2/6] ARM i.MX21: Add devicetree support
  2019-01-12  2:53   ` Shawn Guo
@ 2019-01-12  5:17     ` Alexander Shiyan
  2019-01-12  7:04       ` Shawn Guo
  0 siblings, 1 reply; 9+ messages in thread
From: Alexander Shiyan @ 2019-01-12  5:17 UTC (permalink / raw)
  To: Shawn Guo
  Cc: Fabio Estevam, NXP Linux Team, Russell King,
	Pengutronix Kernel Team, linux-arm-kernel

Hello.

>Суббота, 12 января 2019, 5:53 +03:00 от Shawn Guo <shawnguo@kernel.org>:
>
>On Sat, Dec 22, 2018 at 01:51:56PM +0300, Alexander Shiyan wrote:
>> This patch adds basic devicetree support for i.MX21 based SoCs.
>> 
>> Signed-off-by: Alexander Shiyan < shc_work@mail.ru >
>What i.MX21 board are you running devicetree support on?

I don't have any hardware for o.MX21 SoC.
Have any comments or something wrong?

---
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^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH 2/6] ARM i.MX21: Add devicetree support
  2019-01-12  5:17     ` Alexander Shiyan
@ 2019-01-12  7:04       ` Shawn Guo
  0 siblings, 0 replies; 9+ messages in thread
From: Shawn Guo @ 2019-01-12  7:04 UTC (permalink / raw)
  To: Alexander Shiyan
  Cc: Fabio Estevam, NXP Linux Team, Russell King,
	Pengutronix Kernel Team, linux-arm-kernel

On Sat, Jan 12, 2019 at 08:17:04AM +0300, Alexander Shiyan wrote:
> Hello.
> 
> >Суббота, 12 января 2019, 5:53 +03:00 от Shawn Guo <shawnguo@kernel.org>:
> >
> >On Sat, Dec 22, 2018 at 01:51:56PM +0300, Alexander Shiyan wrote:
> >> This patch adds basic devicetree support for i.MX21 based SoCs.
> >> 
> >> Signed-off-by: Alexander Shiyan < shc_work@mail.ru >
> >What i.MX21 board are you running devicetree support on?
> 
> I don't have any hardware for o.MX21 SoC.
> Have any comments or something wrong?

If there is no real users for the hardware, I would leave it as it is
and rather not add new code for it.

Shawn

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^ permalink raw reply	[flat|nested] 9+ messages in thread

end of thread, back to index

Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-12-22 10:51 [PATCH 1/6] ARM: dts: imx21: add i.MX21 SoC device tree Alexander Shiyan
2018-12-22 10:51 ` [PATCH 2/6] ARM i.MX21: Add devicetree support Alexander Shiyan
2019-01-12  2:53   ` Shawn Guo
2019-01-12  5:17     ` Alexander Shiyan
2019-01-12  7:04       ` Shawn Guo
2018-12-22 10:51 ` [PATCH 3/6] ARM: dts: imx21: Add support for the i.MX21 Freescale ADS board Alexander Shiyan
2018-12-22 10:51 ` [PATCH 4/6] ARM: i.MX: Remove i.MX21 Freescale ADS board support Alexander Shiyan
2018-12-22 10:51 ` [PATCH 5/6] ARM: i.MX: Move SOC_IMX21 into 'Device tree only' Alexander Shiyan
2018-12-22 10:52 ` [PATCH 6/6] ARM: i.MX: Remove i.MX21 non-DT device registration helpers Alexander Shiyan

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