[arm-platforms:arm64/spectre-sysfs 8/9] arch/arm64/kernel/cpu_errata.c:499:2: error: unknown type name 'bp_hardening_cb_t'

[kbuild test robot <lkp@intel.com>]

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tree:   https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git arm64/spectre-sysfs
head:   b143f03fae57e6a3656c3024907a840146fc4b3f
commit: 994a3d6b2b6432f3b75bc90e9d6131495ba9e604 [8/9] arm64: Advertise mitigation of Spectre-v2, or lack thereof
config: arm64-allnoconfig (attached as .config)
compiler: aarch64-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        git checkout 994a3d6b2b6432f3b75bc90e9d6131495ba9e604
        # save the attached .config to linux build tree
        GCC_VERSION=7.2.0 make.cross ARCH=arm64 

All errors (new ones prefixed by >>):

   arch/arm64/kernel/cpu_errata.c: In function 'check_branch_predictor':
>> arch/arm64/kernel/cpu_errata.c:499:2: error: unknown type name 'bp_hardening_cb_t'
     bp_hardening_cb_t cb;
     ^~~~~~~~~~~~~~~~~
>> arch/arm64/kernel/cpu_errata.c:533:8: error: 'call_hvc_arch_workaround_1' undeclared (first use in this function)
      cb = call_hvc_arch_workaround_1;
           ^~~~~~~~~~~~~~~~~~~~~~~~~~
   arch/arm64/kernel/cpu_errata.c:533:8: note: each undeclared identifier is reported only once for each function it appears in
>> arch/arm64/kernel/cpu_errata.c:547:8: error: 'call_smc_arch_workaround_1' undeclared (first use in this function); did you mean 'call_hvc_arch_workaround_1'?
      cb = call_smc_arch_workaround_1;
           ^~~~~~~~~~~~~~~~~~~~~~~~~~
           call_hvc_arch_workaround_1
>> arch/arm64/kernel/cpu_errata.c:548:17: error: '__smccc_workaround_1_smc_start' undeclared (first use in this function)
      smccc_start = __smccc_workaround_1_smc_start;
                    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> arch/arm64/kernel/cpu_errata.c:549:15: error: '__smccc_workaround_1_smc_end' undeclared (first use in this function); did you mean '__smccc_workaround_1_smc_start'?
      smccc_end = __smccc_workaround_1_smc_end;
                  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
                  __smccc_workaround_1_smc_start
>> arch/arm64/kernel/cpu_errata.c:561:9: error: 'qcom_link_stack_sanitization' undeclared (first use in this function)
       cb = qcom_link_stack_sanitization;
            ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> arch/arm64/kernel/cpu_errata.c:563:3: error: implicit declaration of function 'install_bp_hardening_cb' [-Werror=implicit-function-declaration]
      install_bp_hardening_cb(entry, cb, smccc_start, smccc_end);
      ^~~~~~~~~~~~~~~~~~~~~~~
   arch/arm64/kernel/cpu_errata.c: In function 'cpu_show_spec_store_bypass':
   arch/arm64/kernel/cpu_errata.c:836:6: error: '__ssb_safe' undeclared (first use in this function); did you mean '__safe'?
     if (__ssb_safe)
         ^~~~~~~~~~
         __safe
   cc1: some warnings being treated as errors

vim +/bp_hardening_cb_t +499 arch/arm64/kernel/cpu_errata.c

   491	
   492	/*
   493	 * Track overall bp hardening for all heterogeneous cores in the machine.
   494	 * We are only considered "safe" if all booted cores are known safe.
   495	 */
   496	static bool __maybe_unused
   497	check_branch_predictor(const struct arm64_cpu_capabilities *entry, int scope)
   498	{
 > 499		bp_hardening_cb_t cb;
   500		void *smccc_start, *smccc_end;
   501		struct arm_smccc_res res;
   502		bool have_wa = false;
   503		u32 midr = read_cpuid_id();
   504	
   505		WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
   506	
   507		/* If the CPU has CSV2 set, we're safe */
   508		if (cpuid_feature_extract_unsigned_field(read_cpuid(ID_AA64PFR0_EL1),
   509							 ID_AA64PFR0_CSV2_SHIFT))
   510			return false;
   511	
   512		/* Alternatively, we have a list of unaffected CPUs */
   513		if (is_midr_in_range_list(midr, spectre_v2_safe_list))
   514			return false;
   515	
   516		/* From this point onward, we assume the worst */
   517		__spectrev2_safe = false;
   518	
   519		if (psci_ops.smccc_version == SMCCC_VERSION_1_0) {
   520			__hardenbp_enab = false;
   521			goto out;
   522		}
   523	
   524		switch (psci_ops.conduit) {
   525		case PSCI_CONDUIT_HVC:
   526			arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
   527					  ARM_SMCCC_ARCH_WORKAROUND_1, &res);
   528			if ((int)res.a0 < 0) {
   529				__hardenbp_enab = false;
   530				break;
   531			}
   532			have_wa = true;
 > 533			cb = call_hvc_arch_workaround_1;
   534			/* This is a guest, no need to patch KVM vectors */
   535			smccc_start = NULL;
   536			smccc_end = NULL;
   537			break;
   538	
   539		case PSCI_CONDUIT_SMC:
   540			arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
   541					  ARM_SMCCC_ARCH_WORKAROUND_1, &res);
   542			if ((int)res.a0 < 0) {
   543				__hardenbp_enab = false;
   544				break;
   545			}
   546			have_wa = true;
 > 547			cb = call_smc_arch_workaround_1;
 > 548			smccc_start = __smccc_workaround_1_smc_start;
 > 549			smccc_end = __smccc_workaround_1_smc_end;
   550			break;
   551	
   552		default:
   553			__hardenbp_enab = false;
   554			break;
   555		}
   556	
   557	out:
   558		if (have_wa) {
   559			if (((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR) ||
   560			    ((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR_V1))
 > 561				cb = qcom_link_stack_sanitization;
   562	
 > 563			install_bp_hardening_cb(entry, cb, smccc_start, smccc_end);
   564		} else {
   565			pr_warn_once("ARM_SMCCC_ARCH_WORKAROUND_1 missing from firmware\n");
   566		}
   567	
   568		arm64_requested_vuln_attrs |= VULN_SPECTREV2;
   569	
   570		return have_wa;
   571	}
   572	

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

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