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* [PATCH 00/10] arm64: dts: allwinner: h5: Enable CPU DVFS (cpufreq)
@ 2019-01-30  8:41 Chen-Yu Tsai
  2019-01-30  8:41 ` [PATCH 01/10] ARM: dts: sunxi: bananapi-m2-plus-v1.2: Fix CPU supply voltages Chen-Yu Tsai
                   ` (10 more replies)
  0 siblings, 11 replies; 16+ messages in thread
From: Chen-Yu Tsai @ 2019-01-30  8:41 UTC (permalink / raw)
  To: Maxime Ripard
  Cc: devicetree, Sergey Matyukevich, Andre Przywara, Chen-Yu Tsai,
	linux-kernel, Emmanuel Vadot, linux-sunxi, Jagan Teki,
	Hauke Mehrtens, linux-arm-kernel, Icenowy Zheng

Hi everyone,

This series enables DVFS for the CPU cores (aka cpufreq) on the
Allwinner H5 SoC. The OPP table was taken from Armbian, with minor
tweaks to the maximum voltage to account for slightly increased voltage
on some of the boards.

This has been tested on the Bananapi M2+ v1.2 and Libre Computer
ALL-H3-CC H5 ver..  I do not have the remaining boards so I've CC-ed
people who did the original submission or have modified the board
specifically later on.

Patch 1 fixes the voltages specified for the GPIO-controlled regulator
on the Bananapi M2+ v1.2. The voltages are slightly higher than what
was originally written.

Patch 2 adds a fixed regulator for the CPU on the original Bananapi M2+.
This is for the retail version, not the engineering samples that had an
even higher voltage setting.

Patch 3 hooks up the CPU regulator supply for H5 boards that already
define the regulator, but were missing the property to tie it to the
CPUs.

Patch 4 ~ 8 adds the CPU regulator for boards that don't have it
defined. This is based on each vendor's schematics. I need people
to test each of these specifically and the whole series.

Patch 9 ties the CPU clock to the CPU cores.

Patch 10 adds the OPP table, based on the one from Armbian.

Please have a look and please help test this.


Regards
ChenYu


Chen-Yu Tsai (10):
  ARM: dts: sunxi: bananapi-m2-plus-v1.2: Fix CPU supply voltages
  ARM: dts: bananapi-m2-plus: Add CPU supply regulator
  arm64: dts: allwinner: h5: Hook up cpu regulator supplies
  arm64: dts: allwinner: h5: nanopi-neo2: Add CPU regulator supply
  arm64: dts: allwinner: h5: orange-pi-zero-plus: Add CPU regulator
    supply
  arm64: dts: allwinner: h5: orange-pi-zero-plus2: Add CPU regulator
    supply
  arm64: dts: allwinner: h5: orange-pi-pc2: Add CPU regulator supply
  arm64: dts: allwinner: h5: orange-pi-prime: Add CPU regulator supply
  arm64: dts: allwinner: h5: Add clock to CPU cores
  arm64: dts: allwinner: h5: Add CPU Operating Performance Points table

 .../boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi | 30 +++-----
 arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi | 14 ++++
 .../sun50i-h5-emlid-neutis-n5-devboard.dts    |  4 +
 .../allwinner/sun50i-h5-nanopi-neo-plus2.dts  |  4 +
 .../dts/allwinner/sun50i-h5-nanopi-neo2.dts   | 20 +++++
 .../dts/allwinner/sun50i-h5-orangepi-pc2.dts  | 28 +++++++
 .../allwinner/sun50i-h5-orangepi-prime.dts    | 28 +++++++
 .../sun50i-h5-orangepi-zero-plus.dts          | 20 +++++
 .../sun50i-h5-orangepi-zero-plus2.dts         | 20 +++++
 arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi  | 75 +++++++++++++++++++
 10 files changed, 224 insertions(+), 19 deletions(-)

-- 
2.20.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [PATCH 01/10] ARM: dts: sunxi: bananapi-m2-plus-v1.2: Fix CPU supply voltages
  2019-01-30  8:41 [PATCH 00/10] arm64: dts: allwinner: h5: Enable CPU DVFS (cpufreq) Chen-Yu Tsai
@ 2019-01-30  8:41 ` Chen-Yu Tsai
  2019-01-30  8:41 ` [PATCH 02/10] ARM: dts: bananapi-m2-plus: Add CPU supply regulator Chen-Yu Tsai
                   ` (9 subsequent siblings)
  10 siblings, 0 replies; 16+ messages in thread
From: Chen-Yu Tsai @ 2019-01-30  8:41 UTC (permalink / raw)
  To: Maxime Ripard
  Cc: devicetree, Sergey Matyukevich, Andre Przywara, Chen-Yu Tsai,
	linux-kernel, Emmanuel Vadot, linux-sunxi, Jagan Teki,
	Hauke Mehrtens, linux-arm-kernel, Icenowy Zheng

The Bananapi M2+ uses a GPIO line to change the effective resistance of
the CPU supply regulator's feedback resistor network. The voltages
described in the device tree were given directly by the vendor. This
turns out to be slightly off compared to the real values.

The updated voltages are based on calculations of the feedback resistor
network, and verified down to three decimal places with a multi-meter.

Fixes: 6eeb4180d4b9 ("ARM: dts: sunxi: h3-h5: Add Bananapi M2+ v1.2 device trees")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi b/arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi
index 53edd1faee99..a567567763f4 100644
--- a/arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi
+++ b/arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi
@@ -16,13 +16,13 @@
 		regulator-type = "voltage";
 		regulator-boot-on;
 		regulator-always-on;
-		regulator-min-microvolt = <1100000>;
-		regulator-max-microvolt = <1300000>;
+		regulator-min-microvolt = <1108475>;
+		regulator-max-microvolt = <1308475>;
 		regulator-ramp-delay = <50>; /* 4ms */
 		gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */
 		gpios-states = <0x1>;
-		states = <1100000 0x0
-			  1300000 0x1>;
+		states = <1108475 0x0
+			  1308475 0x1>;
 	};
 };
 
-- 
2.20.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [PATCH 02/10] ARM: dts: bananapi-m2-plus: Add CPU supply regulator
  2019-01-30  8:41 [PATCH 00/10] arm64: dts: allwinner: h5: Enable CPU DVFS (cpufreq) Chen-Yu Tsai
  2019-01-30  8:41 ` [PATCH 01/10] ARM: dts: sunxi: bananapi-m2-plus-v1.2: Fix CPU supply voltages Chen-Yu Tsai
@ 2019-01-30  8:41 ` Chen-Yu Tsai
  2019-01-30  8:41 ` [PATCH 03/10] arm64: dts: allwinner: h5: Hook up cpu regulator supplies Chen-Yu Tsai
                   ` (8 subsequent siblings)
  10 siblings, 0 replies; 16+ messages in thread
From: Chen-Yu Tsai @ 2019-01-30  8:41 UTC (permalink / raw)
  To: Maxime Ripard
  Cc: devicetree, Sergey Matyukevich, Andre Przywara, Chen-Yu Tsai,
	linux-kernel, Emmanuel Vadot, linux-sunxi, Jagan Teki,
	Hauke Mehrtens, linux-arm-kernel, Icenowy Zheng

The original Bananapi M2+ uses a fixed regulator to supply the CPU
cores. According to Bananapi, the retail v1.1 version is designed to
supply 1.3V. Actual measurements show 1.310V. Earlier engineering
samples had it at 1.4V, but this is not covered here.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 .../boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi | 30 +++++++------------
 arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi | 14 +++++++++
 2 files changed, 25 insertions(+), 19 deletions(-)

diff --git a/arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi b/arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi
index a567567763f4..39834329b6ae 100644
--- a/arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi
+++ b/arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi
@@ -5,27 +5,19 @@
 
 #include "sunxi-bananapi-m2-plus.dtsi"
 
-/ {
+&reg_vdd_cpux {
 	/*
 	 * Bananapi M2+ v1.2 uses a GPIO line to change the effective
 	 * resistance on the CPU regulator's feedback pin.
 	 */
-	reg_vdd_cpux: vdd-cpux {
-		compatible = "regulator-gpio";
-		regulator-name = "vdd-cpux";
-		regulator-type = "voltage";
-		regulator-boot-on;
-		regulator-always-on;
-		regulator-min-microvolt = <1108475>;
-		regulator-max-microvolt = <1308475>;
-		regulator-ramp-delay = <50>; /* 4ms */
-		gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */
-		gpios-states = <0x1>;
-		states = <1108475 0x0
-			  1308475 0x1>;
-	};
-};
-
-&cpu0 {
-	cpu-supply = <&reg_vdd_cpux>;
+	compatible = "regulator-gpio";
+	regulator-type = "voltage";
+	regulator-min-microvolt = <1108475>;
+	regulator-max-microvolt = <1308475>;
+	regulator-ramp-delay = <50>; /* 4ms */
+	enable-gpios =  <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
+	gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */
+	gpios-states = <0x1>;
+	states = <1108475 0x0
+		  1308475 0x1>;
 };
diff --git a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi
index 3bed375b9c03..eb90f53ae958 100644
--- a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi
+++ b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi
@@ -99,6 +99,16 @@
 		      gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
 	};
 
+	reg_vdd_cpux: vdd-cpux {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd-cpux";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <1310000>;
+		regulator-max-microvolt = <1310000>;
+		gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
+	};
+
 	wifi_pwrseq: wifi_pwrseq {
 		compatible = "mmc-pwrseq-simple";
 		pinctrl-names = "default";
@@ -108,6 +118,10 @@
 	};
 };
 
+&cpu0 {
+	cpu-supply = <&reg_vdd_cpux>;
+};
+
 &de {
 	status = "okay";
 };
-- 
2.20.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [PATCH 03/10] arm64: dts: allwinner: h5: Hook up cpu regulator supplies
  2019-01-30  8:41 [PATCH 00/10] arm64: dts: allwinner: h5: Enable CPU DVFS (cpufreq) Chen-Yu Tsai
  2019-01-30  8:41 ` [PATCH 01/10] ARM: dts: sunxi: bananapi-m2-plus-v1.2: Fix CPU supply voltages Chen-Yu Tsai
  2019-01-30  8:41 ` [PATCH 02/10] ARM: dts: bananapi-m2-plus: Add CPU supply regulator Chen-Yu Tsai
@ 2019-01-30  8:41 ` Chen-Yu Tsai
  2019-01-30  8:41 ` [PATCH 04/10] arm64: dts: allwinner: h5: nanopi-neo2: Add CPU regulator supply Chen-Yu Tsai
                   ` (7 subsequent siblings)
  10 siblings, 0 replies; 16+ messages in thread
From: Chen-Yu Tsai @ 2019-01-30  8:41 UTC (permalink / raw)
  To: Maxime Ripard
  Cc: devicetree, Sergey Matyukevich, Andre Przywara, Chen-Yu Tsai,
	linux-kernel, Emmanuel Vadot, linux-sunxi, Jagan Teki,
	Hauke Mehrtens, linux-arm-kernel, Icenowy Zheng

Some of the device trees for H5 boards already have the CPU supply
regulator defined, but they are not referenced in the CPU node.

Add the reference, so CPU DVFS mechanisms can see them.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 .../boot/dts/allwinner/sun50i-h5-emlid-neutis-n5-devboard.dts | 4 ++++
 arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts  | 4 ++++
 2 files changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5-devboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5-devboard.dts
index 85e7993a74e7..0c7b2b3d92f9 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5-devboard.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5-devboard.dts
@@ -71,6 +71,10 @@
 	status = "okay";
 };
 
+&cpu0 {
+	cpu-supply = <&vdd_cpux>;
+};
+
 &de {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts
index 506e25ba028a..10e52b612892 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts
@@ -126,6 +126,10 @@
 	status = "okay";
 };
 
+&cpu0 {
+	cpu-supply = <&vdd_cpux>;
+};
+
 &ehci0 {
 	status = "okay";
 };
-- 
2.20.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [PATCH 04/10] arm64: dts: allwinner: h5: nanopi-neo2: Add CPU regulator supply
  2019-01-30  8:41 [PATCH 00/10] arm64: dts: allwinner: h5: Enable CPU DVFS (cpufreq) Chen-Yu Tsai
                   ` (2 preceding siblings ...)
  2019-01-30  8:41 ` [PATCH 03/10] arm64: dts: allwinner: h5: Hook up cpu regulator supplies Chen-Yu Tsai
@ 2019-01-30  8:41 ` Chen-Yu Tsai
  2019-01-30  8:41 ` [PATCH 05/10] arm64: dts: allwinner: h5: orange-pi-zero-plus: " Chen-Yu Tsai
                   ` (6 subsequent siblings)
  10 siblings, 0 replies; 16+ messages in thread
From: Chen-Yu Tsai @ 2019-01-30  8:41 UTC (permalink / raw)
  To: Maxime Ripard
  Cc: devicetree, Sergey Matyukevich, Andre Przywara, Chen-Yu Tsai,
	linux-kernel, Emmanuel Vadot, linux-sunxi, Jagan Teki,
	Hauke Mehrtens, linux-arm-kernel, Icenowy Zheng

The Nanopi Neo 2 uses a fixed regulator to supply the CPU cores. The
feedback resistor network can be changed by toggling a GPIO line. This
is effectively a GPIO controlled regulator that can change between 1.1V
and 1.3V.

Cc: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>

---

This patch is based on the schematics and has not been tested on an
actual board.
---
 .../dts/allwinner/sun50i-h5-nanopi-neo2.dts   | 20 +++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
index cc268a69786c..08ffdfb78137 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
@@ -99,6 +99,26 @@
 		gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */
 		status = "okay";
 	};
+
+	reg_vdd_cpux: vdd-cpux {
+		compatible = "regulator-gpio";
+		regulator-name = "vdd-cpux";
+		regulator-type = "voltage";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <1100000>;
+		regulator-max-microvolt = <1300000>;
+		regulator-ramp-delay = <50>; /* 4ms */
+		enable-gpios =  <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
+		gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL6 */
+		gpios-states = <0x1>;
+		states = <1100000 0x0
+			  1300000 0x1>;
+	};
+};
+
+&cpu0 {
+	cpu-supply = <&reg_vdd_cpux>;
 };
 
 &ehci0 {
-- 
2.20.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [PATCH 05/10] arm64: dts: allwinner: h5: orange-pi-zero-plus: Add CPU regulator supply
  2019-01-30  8:41 [PATCH 00/10] arm64: dts: allwinner: h5: Enable CPU DVFS (cpufreq) Chen-Yu Tsai
                   ` (3 preceding siblings ...)
  2019-01-30  8:41 ` [PATCH 04/10] arm64: dts: allwinner: h5: nanopi-neo2: Add CPU regulator supply Chen-Yu Tsai
@ 2019-01-30  8:41 ` Chen-Yu Tsai
  2019-01-30  8:41 ` [PATCH 06/10] arm64: dts: allwinner: h5: orange-pi-zero-plus2: " Chen-Yu Tsai
                   ` (5 subsequent siblings)
  10 siblings, 0 replies; 16+ messages in thread
From: Chen-Yu Tsai @ 2019-01-30  8:41 UTC (permalink / raw)
  To: Maxime Ripard
  Cc: devicetree, Sergey Matyukevich, Andre Przywara, Chen-Yu Tsai,
	linux-kernel, Emmanuel Vadot, linux-sunxi, Jagan Teki,
	Hauke Mehrtens, linux-arm-kernel, Icenowy Zheng

The OrangePi Zero Plus uses a fixed regulator to supply the CPU cores.
The feedback resistor network can be changed by toggling a GPIO line.
This is effectively a GPIO controlled regulator that can change between
roughly 1.1V and 1.3V. The actual voltage is slightly higher. The values
used in the device tree description are based on calculations using the
resistor values from the schematics.

Cc: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>

---

This patch is based on the schematics and has not been tested on an
actual board.
---
 .../sun50i-h5-orangepi-zero-plus.dts          | 20 +++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts
index 1238de25a969..3493eea7cf29 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts
@@ -57,6 +57,26 @@
 		enable-active-high;
 		gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
 	};
+
+	reg_vdd_cpux: vdd-cpux {
+		compatible = "regulator-gpio";
+		regulator-name = "vdd-cpux";
+		regulator-type = "voltage";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <1108475>;
+		regulator-max-microvolt = <1307810>;
+		regulator-ramp-delay = <50>; /* 4ms */
+		enable-gpios =  <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
+		gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL6 */
+		gpios-states = <0x1>;
+		states = <1108475 0x0
+			  1307810 0x1>;
+	};
+};
+
+&cpu0 {
+	cpu-supply = <&reg_vdd_cpux>;
 };
 
 &ehci0 {
-- 
2.20.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [PATCH 06/10] arm64: dts: allwinner: h5: orange-pi-zero-plus2: Add CPU regulator supply
  2019-01-30  8:41 [PATCH 00/10] arm64: dts: allwinner: h5: Enable CPU DVFS (cpufreq) Chen-Yu Tsai
                   ` (4 preceding siblings ...)
  2019-01-30  8:41 ` [PATCH 05/10] arm64: dts: allwinner: h5: orange-pi-zero-plus: " Chen-Yu Tsai
@ 2019-01-30  8:41 ` Chen-Yu Tsai
  2019-01-30  8:42 ` [PATCH 07/10] arm64: dts: allwinner: h5: orange-pi-pc2: " Chen-Yu Tsai
                   ` (4 subsequent siblings)
  10 siblings, 0 replies; 16+ messages in thread
From: Chen-Yu Tsai @ 2019-01-30  8:41 UTC (permalink / raw)
  To: Maxime Ripard
  Cc: devicetree, Sergey Matyukevich, Andre Przywara, Chen-Yu Tsai,
	linux-kernel, Emmanuel Vadot, linux-sunxi, Jagan Teki,
	Hauke Mehrtens, linux-arm-kernel, Icenowy Zheng

The OrangePi Zero Plus 2 uses a fixed regulator to supply the CPU cores.
The feedback resistor network can be changed by toggling a GPIO line.
This is effectively a GPIO controlled regulator that can change between
roughly 1.1V and 1.3V. The actual voltage is slightly higher. The values
used in the device tree description are based on calculations using the
resistor values from the schematics.

Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Sergey Matyukevich <geomatsi@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>

---

This patch is based on the schematics and has not been tested on an
actual board.
---
 .../sun50i-h5-orangepi-zero-plus2.dts         | 20 +++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts
index 53c8c11620e0..801c681307ef 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts
@@ -76,6 +76,22 @@
 		regulator-max-microvolt = <3300000>;
 	};
 
+	reg_vdd_cpux: vdd-cpux {
+		compatible = "regulator-gpio";
+		regulator-name = "vdd-cpux";
+		regulator-type = "voltage";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <1108475>;
+		regulator-max-microvolt = <1307810>;
+		regulator-ramp-delay = <50>; /* 4ms */
+		enable-gpios =  <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
+		gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL6 */
+		gpios-states = <0x1>;
+		states = <1108475 0x0
+			  1307810 0x1>;
+	};
+
 	wifi_pwrseq: wifi_pwrseq {
 		compatible = "mmc-pwrseq-simple";
 		pinctrl-names = "default";
@@ -84,6 +100,10 @@
 	};
 };
 
+&cpu0 {
+	cpu-supply = <&reg_vdd_cpux>;
+};
+
 &de {
 	status = "okay";
 };
-- 
2.20.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [PATCH 07/10] arm64: dts: allwinner: h5: orange-pi-pc2: Add CPU regulator supply
  2019-01-30  8:41 [PATCH 00/10] arm64: dts: allwinner: h5: Enable CPU DVFS (cpufreq) Chen-Yu Tsai
                   ` (5 preceding siblings ...)
  2019-01-30  8:41 ` [PATCH 06/10] arm64: dts: allwinner: h5: orange-pi-zero-plus2: " Chen-Yu Tsai
@ 2019-01-30  8:42 ` Chen-Yu Tsai
  2019-01-30  8:42 ` [PATCH 08/10] arm64: dts: allwinner: h5: orange-pi-prime: " Chen-Yu Tsai
                   ` (3 subsequent siblings)
  10 siblings, 0 replies; 16+ messages in thread
From: Chen-Yu Tsai @ 2019-01-30  8:42 UTC (permalink / raw)
  To: Maxime Ripard
  Cc: devicetree, Sergey Matyukevich, Andre Przywara, Chen-Yu Tsai,
	linux-kernel, Emmanuel Vadot, linux-sunxi, Jagan Teki,
	Hauke Mehrtens, linux-arm-kernel, Icenowy Zheng

The OrangePi PC 2 uses a Silergy SY8106A regulator to supply the CPU
cores. The fixed voltage when I2C programmed regulation is not in action
is slightly higher than 1.1V. The value in the device tree description
is based on calculations of the resistor values from the schematics.

Cc: Andre Przywara <andre.przywara@arm.com>
Cc: Icenowy Zheng <icenowy@aosc.io>
Cc: Emmanuel Vadot <manu@freebsd.org>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>

---

This patch is based on the schematics and has not been tested on an
actual board.
---
 .../dts/allwinner/sun50i-h5-orangepi-pc2.dts  | 28 +++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
index 3e0d5a9c096d..23cfad7c78f4 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
@@ -132,6 +132,10 @@
 	status = "okay";
 };
 
+&cpu0 {
+	cpu-supply = <&reg_vdd_cpux>;
+};
+
 &de {
 	status = "okay";
 };
@@ -207,6 +211,30 @@
 	status = "okay";
 };
 
+&r_i2c {
+	status = "okay";
+
+	reg_vdd_cpux: regulator@65 {
+		compatible = "silergy,sy8106a";
+		reg = <0x65>;
+		regulator-name = "vdd-cpux";
+		silergy,fixed-microvolt = <1108474>;
+		/*
+		 * The datasheet uses 1.1V as the minimum value of VDD-CPUX,
+		 * however both the Armbian DVFS table and the official one
+		 * have operating points with voltage under 1.1V, and both
+		 * DVFS table are known to work properly at the lowest
+		 * operating point.
+		 *
+		 * Use 1.0V as the minimum voltage instead.
+		 */
+		regulator-min-microvolt = <1000000>;
+		regulator-max-microvolt = <1300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+};
+
 &spi0  {
 	status = "okay";
 
-- 
2.20.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [PATCH 08/10] arm64: dts: allwinner: h5: orange-pi-prime: Add CPU regulator supply
  2019-01-30  8:41 [PATCH 00/10] arm64: dts: allwinner: h5: Enable CPU DVFS (cpufreq) Chen-Yu Tsai
                   ` (6 preceding siblings ...)
  2019-01-30  8:42 ` [PATCH 07/10] arm64: dts: allwinner: h5: orange-pi-pc2: " Chen-Yu Tsai
@ 2019-01-30  8:42 ` Chen-Yu Tsai
  2019-01-30  8:42 ` [PATCH 09/10] arm64: dts: allwinner: h5: Add clock to CPU cores Chen-Yu Tsai
                   ` (2 subsequent siblings)
  10 siblings, 0 replies; 16+ messages in thread
From: Chen-Yu Tsai @ 2019-01-30  8:42 UTC (permalink / raw)
  To: Maxime Ripard
  Cc: devicetree, Sergey Matyukevich, Andre Przywara, Chen-Yu Tsai,
	linux-kernel, Emmanuel Vadot, linux-sunxi, Jagan Teki,
	Hauke Mehrtens, linux-arm-kernel, Icenowy Zheng

The OrangePi Prime uses a Silergy SY8106A regulator to supply the CPU
cores. The fixed voltage when I2C programmed regulation is not in action
is slightly higher than 1.1V. The value in the device tree description
is based on calculations of the resistor values from the schematics.

Cc: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>

---

This patch is based on the schematics and has not been tested on an
actual board.
---
 .../allwinner/sun50i-h5-orangepi-prime.dts    | 28 +++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
index b75ca4d7d001..e866a0734bb3 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
@@ -139,6 +139,10 @@
 	status = "okay";
 };
 
+&cpu0 {
+	cpu-supply = <&reg_vdd_cpux>;
+};
+
 &de {
 	status = "okay";
 };
@@ -222,6 +226,30 @@
 	status = "okay";
 };
 
+&r_i2c {
+	status = "okay";
+
+	reg_vdd_cpux: regulator@65 {
+		compatible = "silergy,sy8106a";
+		reg = <0x65>;
+		regulator-name = "vdd-cpux";
+		silergy,fixed-microvolt = <1108474>;
+		/*
+		 * The datasheet uses 1.1V as the minimum value of VDD-CPUX,
+		 * however both the Armbian DVFS table and the official one
+		 * have operating points with voltage under 1.1V, and both
+		 * DVFS table are known to work properly at the lowest
+		 * operating point.
+		 *
+		 * Use 1.0V as the minimum voltage instead.
+		 */
+		regulator-min-microvolt = <1000000>;
+		regulator-max-microvolt = <1300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+};
+
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart0_pins_a>;
-- 
2.20.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [PATCH 09/10] arm64: dts: allwinner: h5: Add clock to CPU cores
  2019-01-30  8:41 [PATCH 00/10] arm64: dts: allwinner: h5: Enable CPU DVFS (cpufreq) Chen-Yu Tsai
                   ` (7 preceding siblings ...)
  2019-01-30  8:42 ` [PATCH 08/10] arm64: dts: allwinner: h5: orange-pi-prime: " Chen-Yu Tsai
@ 2019-01-30  8:42 ` Chen-Yu Tsai
  2019-01-30  8:42 ` [PATCH 10/10] arm64: dts: allwinner: h5: Add CPU Operating Performance Points table Chen-Yu Tsai
  2019-09-02 14:03 ` [PATCH 00/10] arm64: dts: allwinner: h5: Enable CPU DVFS (cpufreq) Ondřej Jirman
  10 siblings, 0 replies; 16+ messages in thread
From: Chen-Yu Tsai @ 2019-01-30  8:42 UTC (permalink / raw)
  To: Maxime Ripard
  Cc: devicetree, Sergey Matyukevich, Andre Przywara, Chen-Yu Tsai,
	linux-kernel, Emmanuel Vadot, linux-sunxi, Jagan Teki,
	Hauke Mehrtens, linux-arm-kernel, Icenowy Zheng

The ARM CPU cores are fed by the CPU clock from the CCU. Add a
reference to the clock for each CPU core, along with the clock
transition latency.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
index c22621b4b8e9..25bb8227a6fd 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
@@ -52,6 +52,8 @@
 			device_type = "cpu";
 			reg = <0>;
 			enable-method = "psci";
+			clocks = <&ccu CLK_CPUX>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
 		};
 
 		cpu@1 {
@@ -59,6 +61,8 @@
 			device_type = "cpu";
 			reg = <1>;
 			enable-method = "psci";
+			clocks = <&ccu CLK_CPUX>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
 		};
 
 		cpu@2 {
@@ -66,6 +70,8 @@
 			device_type = "cpu";
 			reg = <2>;
 			enable-method = "psci";
+			clocks = <&ccu CLK_CPUX>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
 		};
 
 		cpu@3 {
@@ -73,6 +79,8 @@
 			device_type = "cpu";
 			reg = <3>;
 			enable-method = "psci";
+			clocks = <&ccu CLK_CPUX>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
 		};
 	};
 
-- 
2.20.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [PATCH 10/10] arm64: dts: allwinner: h5: Add CPU Operating Performance Points table
  2019-01-30  8:41 [PATCH 00/10] arm64: dts: allwinner: h5: Enable CPU DVFS (cpufreq) Chen-Yu Tsai
                   ` (8 preceding siblings ...)
  2019-01-30  8:42 ` [PATCH 09/10] arm64: dts: allwinner: h5: Add clock to CPU cores Chen-Yu Tsai
@ 2019-01-30  8:42 ` Chen-Yu Tsai
  2019-01-30  9:29   ` Maxime Ripard
  2019-09-02 14:03 ` [PATCH 00/10] arm64: dts: allwinner: h5: Enable CPU DVFS (cpufreq) Ondřej Jirman
  10 siblings, 1 reply; 16+ messages in thread
From: Chen-Yu Tsai @ 2019-01-30  8:42 UTC (permalink / raw)
  To: Maxime Ripard
  Cc: devicetree, Sergey Matyukevich, Andre Przywara, Chen-Yu Tsai,
	linux-kernel, Emmanuel Vadot, linux-sunxi, Jagan Teki,
	Hauke Mehrtens, linux-arm-kernel, Icenowy Zheng

Add an OPP (Operating Performance Points) table for the CPU cores to
enable DVFS (Dynamic Voltage & Frequency Scaling) on the H5. The table
originates from Armbian, but the maximum voltage is raised slightly to
account for boards using slightly higher voltages.

This has been tested on the Libre Computer ALL-H3-CC-H5 and the Bananapi
M2+ v1.2 H5, both with adequate cooling. The former has a fixed 1.2V
regulator, while the latter has a GPIO controlled regulator switchable
between 1.1V and 1.3V.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 67 ++++++++++++++++++++
 1 file changed, 67 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
index 25bb8227a6fd..0e83b8a25f9c 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
@@ -54,6 +54,8 @@
 			enable-method = "psci";
 			clocks = <&ccu CLK_CPUX>;
 			clock-latency-ns = <244144>; /* 8 32k periods */
+			operating-points-v2 = <&cpu_opp_table>;
+			#cooling-cells = <2>;
 		};
 
 		cpu@1 {
@@ -63,6 +65,8 @@
 			enable-method = "psci";
 			clocks = <&ccu CLK_CPUX>;
 			clock-latency-ns = <244144>; /* 8 32k periods */
+			operating-points-v2 = <&cpu_opp_table>;
+			#cooling-cells = <2>;
 		};
 
 		cpu@2 {
@@ -72,6 +76,8 @@
 			enable-method = "psci";
 			clocks = <&ccu CLK_CPUX>;
 			clock-latency-ns = <244144>; /* 8 32k periods */
+			operating-points-v2 = <&cpu_opp_table>;
+			#cooling-cells = <2>;
 		};
 
 		cpu@3 {
@@ -81,6 +87,67 @@
 			enable-method = "psci";
 			clocks = <&ccu CLK_CPUX>;
 			clock-latency-ns = <244144>; /* 8 32k periods */
+			operating-points-v2 = <&cpu_opp_table>;
+			#cooling-cells = <2>;
+		};
+	};
+
+	cpu_opp_table: opp_table {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@408000000 {
+			opp-hz = /bits/ 64 <408000000>;
+			opp-microvolt = <1000000 1000000 1310000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+
+		opp@648000000 {
+			opp-hz = /bits/ 64 <648000000>;
+			opp-microvolt = <1040000 1040000 1310000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+
+		opp@816000000 {
+			opp-hz = /bits/ 64 <816000000>;
+			opp-microvolt = <1080000 1080000 1310000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+
+		opp@912000000 {
+			opp-hz = /bits/ 64 <912000000>;
+			opp-microvolt = <1120000 1120000 1310000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+
+		opp@960000000 {
+			opp-hz = /bits/ 64 <960000000>;
+			opp-microvolt = <1160000 1160000 1310000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+
+		opp@1008000000 {
+			opp-hz = /bits/ 64 <1008000000>;
+			opp-microvolt = <1200000 1200000 1310000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+
+		opp@1056000000 {
+			opp-hz = /bits/ 64 <1056000000>;
+			opp-microvolt = <1240000 1240000 1310000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+
+		opp@1104000000 {
+			opp-hz = /bits/ 64 <1104000000>;
+			opp-microvolt = <1260000 1260000 1310000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+
+		opp@1152000000 {
+			opp-hz = /bits/ 64 <1152000000>;
+			opp-microvolt = <1300000 1300000 1310000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
 		};
 	};
 
-- 
2.20.1


_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 16+ messages in thread

* Re: [PATCH 10/10] arm64: dts: allwinner: h5: Add CPU Operating Performance Points table
  2019-01-30  8:42 ` [PATCH 10/10] arm64: dts: allwinner: h5: Add CPU Operating Performance Points table Chen-Yu Tsai
@ 2019-01-30  9:29   ` Maxime Ripard
  2019-01-30  9:41     ` Chen-Yu Tsai
  0 siblings, 1 reply; 16+ messages in thread
From: Maxime Ripard @ 2019-01-30  9:29 UTC (permalink / raw)
  To: Chen-Yu Tsai
  Cc: devicetree, Sergey Matyukevich, Andre Przywara, linux-kernel,
	Emmanuel Vadot, linux-sunxi, Jagan Teki, Hauke Mehrtens,
	linux-arm-kernel, Icenowy Zheng

[-- Attachment #1.1: Type: text/plain, Size: 2401 bytes --]

On Wed, Jan 30, 2019 at 04:42:03PM +0800, Chen-Yu Tsai wrote:
>  			enable-method = "psci";
>  			clocks = <&ccu CLK_CPUX>;
>  			clock-latency-ns = <244144>; /* 8 32k periods */
> +			operating-points-v2 = <&cpu_opp_table>;
> +			#cooling-cells = <2>;
> +		};
> +	};
> +
> +	cpu_opp_table: opp_table {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +
> +		opp@408000000 {
> +			opp-hz = /bits/ 64 <408000000>;
> +			opp-microvolt = <1000000 1000000 1310000>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +
> +		opp@648000000 {
> +			opp-hz = /bits/ 64 <648000000>;
> +			opp-microvolt = <1040000 1040000 1310000>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +
> +		opp@816000000 {
> +			opp-hz = /bits/ 64 <816000000>;
> +			opp-microvolt = <1080000 1080000 1310000>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +
> +		opp@912000000 {
> +			opp-hz = /bits/ 64 <912000000>;
> +			opp-microvolt = <1120000 1120000 1310000>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +
> +		opp@960000000 {
> +			opp-hz = /bits/ 64 <960000000>;
> +			opp-microvolt = <1160000 1160000 1310000>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +
> +		opp@1008000000 {
> +			opp-hz = /bits/ 64 <1008000000>;
> +			opp-microvolt = <1200000 1200000 1310000>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +
> +		opp@1056000000 {
> +			opp-hz = /bits/ 64 <1056000000>;
> +			opp-microvolt = <1240000 1240000 1310000>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +
> +		opp@1104000000 {
> +			opp-hz = /bits/ 64 <1104000000>;
> +			opp-microvolt = <1260000 1260000 1310000>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +
> +		opp@1152000000 {
> +			opp-hz = /bits/ 64 <1152000000>;
> +			opp-microvolt = <1300000 1300000 1310000>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */

What is the frequency and voltage that U-Boot sets up?

We've had the issue with the A33 that it's started at 1008MHz, with
the matching voltage, and ramping up the frequency to 1.2GHz on boards
without PMIC support would increase the frequency but not the voltage,
resulting in a brownout.

Maxime

-- 
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

[-- Attachment #2: Type: text/plain, Size: 176 bytes --]

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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 16+ messages in thread

* Re: [PATCH 10/10] arm64: dts: allwinner: h5: Add CPU Operating Performance Points table
  2019-01-30  9:29   ` Maxime Ripard
@ 2019-01-30  9:41     ` Chen-Yu Tsai
  2019-01-30  9:59       ` Maxime Ripard
  2019-01-31  3:28       ` Chen-Yu Tsai
  0 siblings, 2 replies; 16+ messages in thread
From: Chen-Yu Tsai @ 2019-01-30  9:41 UTC (permalink / raw)
  To: Maxime Ripard
  Cc: devicetree, Sergey Matyukevich, Andre Przywara, linux-kernel,
	Emmanuel Vadot, linux-sunxi, Jagan Teki, Hauke Mehrtens,
	linux-arm-kernel, Icenowy Zheng

On Wed, Jan 30, 2019 at 5:29 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
>
> On Wed, Jan 30, 2019 at 04:42:03PM +0800, Chen-Yu Tsai wrote:
> >                       enable-method = "psci";
> >                       clocks = <&ccu CLK_CPUX>;
> >                       clock-latency-ns = <244144>; /* 8 32k periods */
> > +                     operating-points-v2 = <&cpu_opp_table>;
> > +                     #cooling-cells = <2>;
> > +             };
> > +     };
> > +
> > +     cpu_opp_table: opp_table {
> > +             compatible = "operating-points-v2";
> > +             opp-shared;
> > +
> > +             opp@408000000 {
> > +                     opp-hz = /bits/ 64 <408000000>;
> > +                     opp-microvolt = <1000000 1000000 1310000>;
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +             };
> > +
> > +             opp@648000000 {
> > +                     opp-hz = /bits/ 64 <648000000>;
> > +                     opp-microvolt = <1040000 1040000 1310000>;
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +             };
> > +
> > +             opp@816000000 {
> > +                     opp-hz = /bits/ 64 <816000000>;
> > +                     opp-microvolt = <1080000 1080000 1310000>;
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +             };
> > +
> > +             opp@912000000 {
> > +                     opp-hz = /bits/ 64 <912000000>;
> > +                     opp-microvolt = <1120000 1120000 1310000>;
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +             };
> > +
> > +             opp@960000000 {
> > +                     opp-hz = /bits/ 64 <960000000>;
> > +                     opp-microvolt = <1160000 1160000 1310000>;
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +             };
> > +
> > +             opp@1008000000 {
> > +                     opp-hz = /bits/ 64 <1008000000>;
> > +                     opp-microvolt = <1200000 1200000 1310000>;
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +             };
> > +
> > +             opp@1056000000 {
> > +                     opp-hz = /bits/ 64 <1056000000>;
> > +                     opp-microvolt = <1240000 1240000 1310000>;
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +             };
> > +
> > +             opp@1104000000 {
> > +                     opp-hz = /bits/ 64 <1104000000>;
> > +                     opp-microvolt = <1260000 1260000 1310000>;
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +             };
> > +
> > +             opp@1152000000 {
> > +                     opp-hz = /bits/ 64 <1152000000>;
> > +                     opp-microvolt = <1300000 1300000 1310000>;
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
>
> What is the frequency and voltage that U-Boot sets up?

1008 MHz, and whatever voltage the board design defaults to (typically
the higher setting).

> We've had the issue with the A33 that it's started at 1008MHz, with
> the matching voltage, and ramping up the frequency to 1.2GHz on boards
> without PMIC support would increase the frequency but not the voltage,
> resulting in a brownout.

Which is why I added the regulator to all boards before this patch. At
least for Linux, once the regulator supply is described in the device
tree, if the driver is missing, regulator_get_* and thus cpufreq should
fail with -EPROBE_DEFER.

Or we could drop the extra OPPs.


ChenYu

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 16+ messages in thread

* Re: [PATCH 10/10] arm64: dts: allwinner: h5: Add CPU Operating Performance Points table
  2019-01-30  9:41     ` Chen-Yu Tsai
@ 2019-01-30  9:59       ` Maxime Ripard
  2019-01-31  3:28       ` Chen-Yu Tsai
  1 sibling, 0 replies; 16+ messages in thread
From: Maxime Ripard @ 2019-01-30  9:59 UTC (permalink / raw)
  To: Chen-Yu Tsai
  Cc: devicetree, Sergey Matyukevich, Andre Przywara, linux-kernel,
	Emmanuel Vadot, linux-sunxi, Jagan Teki, Hauke Mehrtens,
	linux-arm-kernel, Icenowy Zheng

[-- Attachment #1.1: Type: text/plain, Size: 4164 bytes --]

On Wed, Jan 30, 2019 at 05:41:16PM +0800, Chen-Yu Tsai wrote:
> On Wed, Jan 30, 2019 at 5:29 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
> >
> > On Wed, Jan 30, 2019 at 04:42:03PM +0800, Chen-Yu Tsai wrote:
> > >                       enable-method = "psci";
> > >                       clocks = <&ccu CLK_CPUX>;
> > >                       clock-latency-ns = <244144>; /* 8 32k periods */
> > > +                     operating-points-v2 = <&cpu_opp_table>;
> > > +                     #cooling-cells = <2>;
> > > +             };
> > > +     };
> > > +
> > > +     cpu_opp_table: opp_table {
> > > +             compatible = "operating-points-v2";
> > > +             opp-shared;
> > > +
> > > +             opp@408000000 {
> > > +                     opp-hz = /bits/ 64 <408000000>;
> > > +                     opp-microvolt = <1000000 1000000 1310000>;
> > > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > > +             };
> > > +
> > > +             opp@648000000 {
> > > +                     opp-hz = /bits/ 64 <648000000>;
> > > +                     opp-microvolt = <1040000 1040000 1310000>;
> > > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > > +             };
> > > +
> > > +             opp@816000000 {
> > > +                     opp-hz = /bits/ 64 <816000000>;
> > > +                     opp-microvolt = <1080000 1080000 1310000>;
> > > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > > +             };
> > > +
> > > +             opp@912000000 {
> > > +                     opp-hz = /bits/ 64 <912000000>;
> > > +                     opp-microvolt = <1120000 1120000 1310000>;
> > > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > > +             };
> > > +
> > > +             opp@960000000 {
> > > +                     opp-hz = /bits/ 64 <960000000>;
> > > +                     opp-microvolt = <1160000 1160000 1310000>;
> > > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > > +             };
> > > +
> > > +             opp@1008000000 {
> > > +                     opp-hz = /bits/ 64 <1008000000>;
> > > +                     opp-microvolt = <1200000 1200000 1310000>;
> > > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > > +             };
> > > +
> > > +             opp@1056000000 {
> > > +                     opp-hz = /bits/ 64 <1056000000>;
> > > +                     opp-microvolt = <1240000 1240000 1310000>;
> > > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > > +             };
> > > +
> > > +             opp@1104000000 {
> > > +                     opp-hz = /bits/ 64 <1104000000>;
> > > +                     opp-microvolt = <1260000 1260000 1310000>;
> > > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > > +             };
> > > +
> > > +             opp@1152000000 {
> > > +                     opp-hz = /bits/ 64 <1152000000>;
> > > +                     opp-microvolt = <1300000 1300000 1310000>;
> > > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> >
> > What is the frequency and voltage that U-Boot sets up?
> 
> 1008 MHz, and whatever voltage the board design defaults to (typically
> the higher setting).
> 
> > We've had the issue with the A33 that it's started at 1008MHz, with
> > the matching voltage, and ramping up the frequency to 1.2GHz on boards
> > without PMIC support would increase the frequency but not the voltage,
> > resulting in a brownout.
> 
> Which is why I added the regulator to all boards before this patch. At
> least for Linux, once the regulator supply is described in the device
> tree, if the driver is missing, regulator_get_* and thus cpufreq should
> fail with -EPROBE_DEFER.
> 
> Or we could drop the extra OPPs.

Ok, if you covered all of them then fine by me. For the whole series,
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>

Maxime

-- 
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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[-- Attachment #2: Type: text/plain, Size: 176 bytes --]

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 16+ messages in thread

* Re: [PATCH 10/10] arm64: dts: allwinner: h5: Add CPU Operating Performance Points table
  2019-01-30  9:41     ` Chen-Yu Tsai
  2019-01-30  9:59       ` Maxime Ripard
@ 2019-01-31  3:28       ` Chen-Yu Tsai
  1 sibling, 0 replies; 16+ messages in thread
From: Chen-Yu Tsai @ 2019-01-31  3:28 UTC (permalink / raw)
  To: Maxime Ripard
  Cc: devicetree, Sergey Matyukevich, Andre Przywara, linux-kernel,
	Emmanuel Vadot, linux-sunxi, Jagan Teki, Hauke Mehrtens,
	linux-arm-kernel, Icenowy Zheng

On Wed, Jan 30, 2019 at 5:41 PM Chen-Yu Tsai <wens@csie.org> wrote:
>
> On Wed, Jan 30, 2019 at 5:29 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
> >
> > On Wed, Jan 30, 2019 at 04:42:03PM +0800, Chen-Yu Tsai wrote:
> > >                       enable-method = "psci";
> > >                       clocks = <&ccu CLK_CPUX>;
> > >                       clock-latency-ns = <244144>; /* 8 32k periods */
> > > +                     operating-points-v2 = <&cpu_opp_table>;
> > > +                     #cooling-cells = <2>;
> > > +             };
> > > +     };
> > > +
> > > +     cpu_opp_table: opp_table {
> > > +             compatible = "operating-points-v2";
> > > +             opp-shared;
> > > +
> > > +             opp@408000000 {
> > > +                     opp-hz = /bits/ 64 <408000000>;
> > > +                     opp-microvolt = <1000000 1000000 1310000>;
> > > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > > +             };
> > > +
> > > +             opp@648000000 {
> > > +                     opp-hz = /bits/ 64 <648000000>;
> > > +                     opp-microvolt = <1040000 1040000 1310000>;
> > > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > > +             };
> > > +
> > > +             opp@816000000 {
> > > +                     opp-hz = /bits/ 64 <816000000>;
> > > +                     opp-microvolt = <1080000 1080000 1310000>;
> > > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > > +             };
> > > +
> > > +             opp@912000000 {
> > > +                     opp-hz = /bits/ 64 <912000000>;
> > > +                     opp-microvolt = <1120000 1120000 1310000>;
> > > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > > +             };
> > > +
> > > +             opp@960000000 {
> > > +                     opp-hz = /bits/ 64 <960000000>;
> > > +                     opp-microvolt = <1160000 1160000 1310000>;
> > > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > > +             };
> > > +
> > > +             opp@1008000000 {
> > > +                     opp-hz = /bits/ 64 <1008000000>;
> > > +                     opp-microvolt = <1200000 1200000 1310000>;
> > > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > > +             };
> > > +
> > > +             opp@1056000000 {
> > > +                     opp-hz = /bits/ 64 <1056000000>;
> > > +                     opp-microvolt = <1240000 1240000 1310000>;
> > > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > > +             };
> > > +
> > > +             opp@1104000000 {
> > > +                     opp-hz = /bits/ 64 <1104000000>;
> > > +                     opp-microvolt = <1260000 1260000 1310000>;
> > > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > > +             };
> > > +
> > > +             opp@1152000000 {
> > > +                     opp-hz = /bits/ 64 <1152000000>;
> > > +                     opp-microvolt = <1300000 1300000 1310000>;
> > > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> >
> > What is the frequency and voltage that U-Boot sets up?
>
> 1008 MHz, and whatever voltage the board design defaults to (typically
> the higher setting).

FYI I got this wrong. U-boot's default is 816 MHz. However it seems even
this is misleading, as cpufreq in Linux reports:

    cpufreq: cpufreq_online: CPU0: Running at unlisted freq: 792000 KHz
    cpufreq: cpufreq_online: CPU0: Unlisted initial frequency changed
to: 816000 KHz

So there seems tp be an off-by-1 error in some multiplier calculation.

>
> > We've had the issue with the A33 that it's started at 1008MHz, with
> > the matching voltage, and ramping up the frequency to 1.2GHz on boards
> > without PMIC support would increase the frequency but not the voltage,
> > resulting in a brownout.
>
> Which is why I added the regulator to all boards before this patch. At
> least for Linux, once the regulator supply is described in the device
> tree, if the driver is missing, regulator_get_* and thus cpufreq should
> fail with -EPROBE_DEFER.

I believe despite the above, this still stands. So we should be OK.

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 16+ messages in thread

* Re: [PATCH 00/10] arm64: dts: allwinner: h5: Enable CPU DVFS (cpufreq)
  2019-01-30  8:41 [PATCH 00/10] arm64: dts: allwinner: h5: Enable CPU DVFS (cpufreq) Chen-Yu Tsai
                   ` (9 preceding siblings ...)
  2019-01-30  8:42 ` [PATCH 10/10] arm64: dts: allwinner: h5: Add CPU Operating Performance Points table Chen-Yu Tsai
@ 2019-09-02 14:03 ` Ondřej Jirman
  10 siblings, 0 replies; 16+ messages in thread
From: Ondřej Jirman @ 2019-09-02 14:03 UTC (permalink / raw)
  To: Chen-Yu Tsai
  Cc: devicetree, Sergey Matyukevich, Maxime Ripard, Andre Przywara,
	linux-kernel, Emmanuel Vadot, linux-sunxi, Jagan Teki,
	Hauke Mehrtens, linux-arm-kernel, Icenowy Zheng

Hi,

On Wed, Jan 30, 2019 at 04:41:53PM +0800, Chen-Yu Tsai wrote:
> Hi everyone,
> 
> This series enables DVFS for the CPU cores (aka cpufreq) on the
> Allwinner H5 SoC. The OPP table was taken from Armbian, with minor
> tweaks to the maximum voltage to account for slightly increased voltage
> on some of the boards.
> 
> This has been tested on the Bananapi M2+ v1.2 and Libre Computer
> ALL-H3-CC H5 ver..  I do not have the remaining boards so I've CC-ed
> people who did the original submission or have modified the board
> specifically later on.
> 
> Patch 1 fixes the voltages specified for the GPIO-controlled regulator
> on the Bananapi M2+ v1.2. The voltages are slightly higher than what
> was originally written.
> 
> Patch 2 adds a fixed regulator for the CPU on the original Bananapi M2+.
> This is for the retail version, not the engineering samples that had an
> even higher voltage setting.
> 
> Patch 3 hooks up the CPU regulator supply for H5 boards that already
> define the regulator, but were missing the property to tie it to the
> CPUs.
> 
> Patch 4 ~ 8 adds the CPU regulator for boards that don't have it
> defined. This is based on each vendor's schematics. I need people
> to test each of these specifically and the whole series.
> 
> Patch 9 ties the CPU clock to the CPU cores.
> 
> Patch 10 adds the OPP table, based on the one from Armbian.
> 
> Please have a look and please help test this.

Looks like this patch series got forgotten. Or is it waiting for some
user testing?

regards,
	o.

> 
> Regards
> ChenYu
> 
> 
> Chen-Yu Tsai (10):
>   ARM: dts: sunxi: bananapi-m2-plus-v1.2: Fix CPU supply voltages
>   ARM: dts: bananapi-m2-plus: Add CPU supply regulator
>   arm64: dts: allwinner: h5: Hook up cpu regulator supplies
>   arm64: dts: allwinner: h5: nanopi-neo2: Add CPU regulator supply
>   arm64: dts: allwinner: h5: orange-pi-zero-plus: Add CPU regulator
>     supply
>   arm64: dts: allwinner: h5: orange-pi-zero-plus2: Add CPU regulator
>     supply
>   arm64: dts: allwinner: h5: orange-pi-pc2: Add CPU regulator supply
>   arm64: dts: allwinner: h5: orange-pi-prime: Add CPU regulator supply
>   arm64: dts: allwinner: h5: Add clock to CPU cores
>   arm64: dts: allwinner: h5: Add CPU Operating Performance Points table
> 
>  .../boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi | 30 +++-----
>  arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi | 14 ++++
>  .../sun50i-h5-emlid-neutis-n5-devboard.dts    |  4 +
>  .../allwinner/sun50i-h5-nanopi-neo-plus2.dts  |  4 +
>  .../dts/allwinner/sun50i-h5-nanopi-neo2.dts   | 20 +++++
>  .../dts/allwinner/sun50i-h5-orangepi-pc2.dts  | 28 +++++++
>  .../allwinner/sun50i-h5-orangepi-prime.dts    | 28 +++++++
>  .../sun50i-h5-orangepi-zero-plus.dts          | 20 +++++
>  .../sun50i-h5-orangepi-zero-plus2.dts         | 20 +++++
>  arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi  | 75 +++++++++++++++++++
>  10 files changed, 224 insertions(+), 19 deletions(-)
> 
> -- 
> 2.20.1
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

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^ permalink raw reply	[flat|nested] 16+ messages in thread

end of thread, back to index

Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-01-30  8:41 [PATCH 00/10] arm64: dts: allwinner: h5: Enable CPU DVFS (cpufreq) Chen-Yu Tsai
2019-01-30  8:41 ` [PATCH 01/10] ARM: dts: sunxi: bananapi-m2-plus-v1.2: Fix CPU supply voltages Chen-Yu Tsai
2019-01-30  8:41 ` [PATCH 02/10] ARM: dts: bananapi-m2-plus: Add CPU supply regulator Chen-Yu Tsai
2019-01-30  8:41 ` [PATCH 03/10] arm64: dts: allwinner: h5: Hook up cpu regulator supplies Chen-Yu Tsai
2019-01-30  8:41 ` [PATCH 04/10] arm64: dts: allwinner: h5: nanopi-neo2: Add CPU regulator supply Chen-Yu Tsai
2019-01-30  8:41 ` [PATCH 05/10] arm64: dts: allwinner: h5: orange-pi-zero-plus: " Chen-Yu Tsai
2019-01-30  8:41 ` [PATCH 06/10] arm64: dts: allwinner: h5: orange-pi-zero-plus2: " Chen-Yu Tsai
2019-01-30  8:42 ` [PATCH 07/10] arm64: dts: allwinner: h5: orange-pi-pc2: " Chen-Yu Tsai
2019-01-30  8:42 ` [PATCH 08/10] arm64: dts: allwinner: h5: orange-pi-prime: " Chen-Yu Tsai
2019-01-30  8:42 ` [PATCH 09/10] arm64: dts: allwinner: h5: Add clock to CPU cores Chen-Yu Tsai
2019-01-30  8:42 ` [PATCH 10/10] arm64: dts: allwinner: h5: Add CPU Operating Performance Points table Chen-Yu Tsai
2019-01-30  9:29   ` Maxime Ripard
2019-01-30  9:41     ` Chen-Yu Tsai
2019-01-30  9:59       ` Maxime Ripard
2019-01-31  3:28       ` Chen-Yu Tsai
2019-09-02 14:03 ` [PATCH 00/10] arm64: dts: allwinner: h5: Enable CPU DVFS (cpufreq) Ondřej Jirman

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