[PATCH 1/2] ARM: dts: pfla02: prepare storage devices to add paritions

[PATCH 1/2] ARM: dts: pfla02: prepare storage devices to add paritions

[Marco Felsch]

Partitions in the NOR and EEPROM are application specific. Prepare the
SoM device tree so platform device tree's can add partitions.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
 arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
index 1bfa41e01a0c..35d56e25c4a0 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
@@ -79,7 +79,7 @@
 	status = "okay";
 	cs-gpios = <&gpio4 24 0>;
 
-	flash@0 {
+	som_flash: flash@0 {
 		compatible = "m25p80", "jedec,spi-nor";
 		spi-max-frequency = <20000000>;
 		reg = <0>;
@@ -107,7 +107,7 @@
 	pinctrl-0 = <&pinctrl_i2c1>;
 	status = "okay";
 
-	eeprom@50 {
+	som_eeprom: eeprom@50 {
 		compatible = "atmel,24c32";
 		reg = <0x50>;
 	};
-- 
2.20.1


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[PATCH 2/2] ARM: dts: pfla02: add ksz9031 clock skew values

[Marco Felsch]

From: Philipp Zabel <p.zabel@pengutronix.de>

The pfla02 SoM has a Micrel KSZ9031RNX ethernet phy connected to the FEC,
which needs RX and TX clock skew settings to compensate for differences
in line length. The skew values are taken from barebox commit
4c65c20f1071 ("ARM: pfla02: Set new ethernet phy tx timings"), which
is based on patches originally provided by Phytec:

    TX_CLK line is approx. 54mm longer than other TX lines which adds
    a delay of 0.36ns. RGMII need a delay of min. 1.0ns. This mean we
    have to add a delay of 0.64ns. We choose 0.78 to have a little gap.
    This can be done by setting GTX pad skew value to 11100
    Also add a delay for the RX delay lines, needed for the Duallite
    variant.  => Set register 2.8 (RGMII Clock Pad Skew) to 0x039F.

Cc: Christian Hemp <c.hemp@phytec.de>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
 arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
index 35d56e25c4a0..673711f445b6 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
@@ -89,10 +89,23 @@
 &fec {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet>;
+	phy-handle = <&ethphy>;
 	phy-mode = "rgmii";
 	phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
 	phy-supply = <&vdd_eth_io_reg>;
 	status = "disabled";
+
+	fec_mdio: mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+			txc-skew-ps = <1680>;
+			rxc-skew-ps = <1860>;
+		};
+	};
 };
 
 &gpmi {
-- 
2.20.1


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Re: [PATCH 2/2] ARM: dts: pfla02: add ksz9031 clock skew values

[Shawn Guo]

On Mon, Feb 04, 2019 at 04:29:56PM +0100, Marco Felsch wrote:
> From: Philipp Zabel <p.zabel@pengutronix.de>
> 
> The pfla02 SoM has a Micrel KSZ9031RNX ethernet phy connected to the FEC,
> which needs RX and TX clock skew settings to compensate for differences
> in line length. The skew values are taken from barebox commit
> 4c65c20f1071 ("ARM: pfla02: Set new ethernet phy tx timings"), which
> is based on patches originally provided by Phytec:
> 
>     TX_CLK line is approx. 54mm longer than other TX lines which adds
>     a delay of 0.36ns. RGMII need a delay of min. 1.0ns. This mean we
>     have to add a delay of 0.64ns. We choose 0.78 to have a little gap.
>     This can be done by setting GTX pad skew value to 11100
>     Also add a delay for the RX delay lines, needed for the Duallite
>     variant.  => Set register 2.8 (RGMII Clock Pad Skew) to 0x039F.
> 
> Cc: Christian Hemp <c.hemp@phytec.de>
> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
> Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>

Applied, thanks.

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Re: [PATCH 2/2] ARM: dts: pfla02: add ksz9031 clock skew values

[Marco Felsch]

Hi Shawn,

On 19-02-11 10:36, Shawn Guo wrote:
> On Mon, Feb 04, 2019 at 04:29:56PM +0100, Marco Felsch wrote:
> > From: Philipp Zabel <p.zabel@pengutronix.de>
> > 
> > The pfla02 SoM has a Micrel KSZ9031RNX ethernet phy connected to the FEC,
> > which needs RX and TX clock skew settings to compensate for differences
> > in line length. The skew values are taken from barebox commit
> > 4c65c20f1071 ("ARM: pfla02: Set new ethernet phy tx timings"), which
> > is based on patches originally provided by Phytec:
> > 
> >     TX_CLK line is approx. 54mm longer than other TX lines which adds
> >     a delay of 0.36ns. RGMII need a delay of min. 1.0ns. This mean we
> >     have to add a delay of 0.64ns. We choose 0.78 to have a little gap.
> >     This can be done by setting GTX pad skew value to 11100
> >     Also add a delay for the RX delay lines, needed for the Duallite
> >     variant.  => Set register 2.8 (RGMII Clock Pad Skew) to 0x039F.
> > 
> > Cc: Christian Hemp <c.hemp@phytec.de>
> > Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
> > Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
> 
> Applied, thanks.

Thanks, for applying. Just for me, is something wrong with the first
patch?

Regards,
Marco

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Re: [PATCH 1/2] ARM: dts: pfla02: prepare storage devices to add paritions

[Uwe Kleine-König]

Hello,

On Mon, Feb 04, 2019 at 04:29:55PM +0100, Marco Felsch wrote:
> Partitions in the NOR and EEPROM are application specific. Prepare the
> SoM device tree so platform device tree's can add partitions.

Even though there is no in-tree user (and maybe there will never be) I
would like to see this kind of patch applied.

Our usecase is that the paritioning is defined in the bootloader (here:
barebox) and before jumping into Linux the (maybe) provided dts is fixed
up to contain the right partitioning. So the Linux device tree doesn't
usually include the partitioning, but as barebox contains a copy of the
the device tree files from Linux it helps here to simplify the board
specific device tree. So:

Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>

-- 
Pengutronix e.K.                           | Uwe Kleine-König            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

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Re: [PATCH 2/2] ARM: dts: pfla02: add ksz9031 clock skew values

[Shawn Guo]

On Mon, Feb 11, 2019 at 11:36:52AM +0100, Marco Felsch wrote:
> Hi Shawn,
> 
> On 19-02-11 10:36, Shawn Guo wrote:
> > On Mon, Feb 04, 2019 at 04:29:56PM +0100, Marco Felsch wrote:
> > > From: Philipp Zabel <p.zabel@pengutronix.de>
> > > 
> > > The pfla02 SoM has a Micrel KSZ9031RNX ethernet phy connected to the FEC,
> > > which needs RX and TX clock skew settings to compensate for differences
> > > in line length. The skew values are taken from barebox commit
> > > 4c65c20f1071 ("ARM: pfla02: Set new ethernet phy tx timings"), which
> > > is based on patches originally provided by Phytec:
> > > 
> > >     TX_CLK line is approx. 54mm longer than other TX lines which adds
> > >     a delay of 0.36ns. RGMII need a delay of min. 1.0ns. This mean we
> > >     have to add a delay of 0.64ns. We choose 0.78 to have a little gap.
> > >     This can be done by setting GTX pad skew value to 11100
> > >     Also add a delay for the RX delay lines, needed for the Duallite
> > >     variant.  => Set register 2.8 (RGMII Clock Pad Skew) to 0x039F.
> > > 
> > > Cc: Christian Hemp <c.hemp@phytec.de>
> > > Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
> > > Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
> > 
> > Applied, thanks.
> 
> Thanks, for applying. Just for me, is something wrong with the first
> patch?

No.  Something is wrong on my side - the patch went to Spam folder for
some reason.

Shawn

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Re: [PATCH 1/2] ARM: dts: pfla02: prepare storage devices to add paritions

[Shawn Guo]

On Mon, Feb 04, 2019 at 04:29:55PM +0100, Marco Felsch wrote:
> Partitions in the NOR and EEPROM are application specific. Prepare the
> SoM device tree so platform device tree's can add partitions.
> 
> Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>

Applied, thanks.

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