* [PATCH 1/2] ARM: dts: Add devicetree for Eckelmann CI4x10
@ 2019-01-11 16:49 Uwe Kleine-König
2019-01-11 16:49 ` [PATCH 2/2] ARM: imx_v6_v7_defconfig: Enable SIOX bus Uwe Kleine-König
2019-01-14 1:39 ` [PATCH 1/2] ARM: dts: Add devicetree for Eckelmann CI4x10 Shawn Guo
0 siblings, 2 replies; 12+ messages in thread
From: Uwe Kleine-König @ 2019-01-11 16:49 UTC (permalink / raw)
To: Shawn Guo
Cc: Fabio Estevam, Gavin Schenk, NXP Linux Team,
Pengutronix Kernel Team, linux-arm-kernel
This is one of two boards that make use of the recently introduced SIOX
bus. Apart from the devices described in the dts it features a display
with touch that I didn't include here because it needs some non-mainline
change to operate correctly.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts | 390 ++++++++++++++++++
2 files changed, 391 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index bd40148a15b2..b60d759e39c0 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -397,6 +397,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-cubox-i-emmc-som-v15.dtb \
imx6dl-cubox-i-som-v15.dtb \
imx6dl-dfi-fs700-m60.dtb \
+ imx6dl-eckelmann-ci4x10.dtb \
imx6dl-emcon-avari.dtb \
imx6dl-gw51xx.dtb \
imx6dl-gw52xx.dtb \
diff --git a/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts b/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts
new file mode 100644
index 000000000000..ef7a7c9d55c3
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts
@@ -0,0 +1,390 @@
+/*
+ * Copyright (C) 2016 Eckelmann AG.
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "imx6dl.dtsi"
+
+/ {
+ model = "Freescale i.MX6 DualLite Eckelmann CI 4X10 Board";
+ compatible = "eckelmann,imx6dl-ci4x10", "fsl,imx6dl";
+
+ chosen {
+ stdout-path = &uart3;
+ };
+
+ memory {
+ reg = <0x10000000 0x40000000>;
+ };
+
+ clocks {
+ rmii_clk: rmii-clock {
+ /* This clock is provided by the phy (KSZ8091RNB) */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ };
+ };
+
+ reg_usb_h1_vbus: regulator@1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usb_h1_vbus>;
+
+ compatible = "regulator-fixed";
+ regulator-name = "usb_h1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio3 31 0>;
+ enable-active-high;
+ };
+
+ siox {
+ compatible = "eckelmann,siox-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_siox>;
+
+ din-gpios = <&gpio6 11 0>;
+ dout-gpios = <&gpio6 8 0>;
+ dclk-gpios = <&gpio6 9 0>;
+ dld-gpios = <&gpio6 10 0>;
+ };
+};
+
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ status = "okay";
+};
+
+&can2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ status = "okay";
+};
+
+&ecspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2>;
+ status = "okay";
+ cs-gpios = <&gpio5 12 GPIO_ACTIVE_HIGH>;
+
+ mram: mr25h256@0 {
+ compatible = "everspin,mr25h256";
+ reg = <0>;
+ spi-max-frequency = <15000000>;
+ };
+};
+
+&ecspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ status = "okay";
+ cs-gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>;
+
+ tpm_spi_tis@0 {
+ compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ temp@49 {
+ compatible = "ad,ad7414";
+ reg = <0x49>;
+ };
+
+ rtc@51 {
+ compatible = "nxp,pcf2127";
+ reg = <0x51>;
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_hog: hog {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x00000018 /* buzzer */
+ MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x00000018 /* OUT_1 */
+ MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x00000018 /* OUT_2 */
+ MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x00000018 /* OUT_3 */
+ MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x00000000 /* In1 */
+ MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x00000000 /* In2 */
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x00000018 /* unused watchdog pin */
+ MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x00000018 /* unused watchdog pin */
+
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x000100a0
+ MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x000100a0
+ MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x000100a0
+ MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000100a0
+ >;
+ };
+
+ pinctrl_ecspi2: ecspi2grp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x000100b1
+ MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x000100b1
+ MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x000100b1
+ MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000100b1
+ >;
+ };
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x0001b098
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x0001b098
+ MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x0001b098
+ MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x0001b098
+ MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x0001b098
+ MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x0001b0b0
+ MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x0001b0b0
+ MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x0001b0b0
+ MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x0001b0b0
+ MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x00000018
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x0001b020
+ MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x0001b0b0
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x0001b020
+ MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x0001b0b0
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ /* without SION i2c doesn't detect bus busy */
+ MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b820
+ MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b820
+ >;
+ };
+
+ pinctrl_pcie: pciegrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x00000018
+ >;
+ };
+
+ pinctrl_reg_usb_h1_vbus: reg_usb_h1_vbusgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0001b0b0
+ >;
+ };
+
+ pinctrl_siox: sioxgrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x0001b010 /* DIN */
+ MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0001b010 /* DOUT */
+ MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0001b010 /* DCLK */
+ MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x0001b010 /* DLD */
+ >;
+ };
+
+ pinctrl_uart1_dte: uart1grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x0001b010
+ MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x0001b010
+ MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x0001b010
+ MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x0001b010
+ MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0001b010 /* DCD */
+ MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x0001b010 /* DTR */
+ MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x0001b010 /* DSR */
+ >;
+ };
+
+ pinctrl_uart2_dte: uart2grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x0001b010
+ MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x0001b010
+ MX6QDL_PAD_EIM_D28__UART2_RTS_B 0x0001b010
+ MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x0001b010
+ MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001b010 /* DCD */
+ MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b010 /* DTR */
+ MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x0001b010 /* DSR */
+ >;
+ };
+
+ pinctrl_uart3_dce: uart3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x0001b010
+ MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x0001b010
+ >;
+ };
+
+ pinctrl_uart4_dce: uart4grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x0001b010
+ MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x0001b010
+ MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x0001b010
+ >;
+ };
+
+ pinctrl_uart5_dce: uart5grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x0001b010
+ MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x0001b010
+ MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x0001b010 /* RTS */
+ >;
+ };
+
+ pinctrl_usbh1: usbh1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D30__USB_H1_OC 0x80000000
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x00017059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x00010059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x00017059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x00017059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x00017059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x00017059
+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x00017059
+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x00017059
+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x00017059
+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x00017059
+ >;
+ };
+};
+
+&gpio2 {
+ gpio-line-names = "buzzer", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio4 {
+ gpio-line-names = "", "", "", "", "", "", "", "in2",
+ "prio2", "prio1", "aux", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio6 {
+ gpio-line-names = "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "in1",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rmii";
+ phy-reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
+ phy-handle = <&phy>;
+ clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&rmii_clk>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+ };
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie>;
+ reset-gpio = <&gpio1 20 0>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_dte>;
+ status = "okay";
+
+ uart-has-rtscts;
+ fsl,dte-mode;
+ dcd-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
+ dtr-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
+ dsr-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2_dte>;
+ status = "okay";
+
+ uart-has-rtscts;
+ fsl,dte-mode;
+ dcd-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
+ dtr-gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
+ dsr-gpios = <&gpio6 16 GPIO_ACTIVE_LOW>;
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3_dce>;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4_dce>;
+ status = "okay";
+ rts-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>;
+};
+
+&uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart5_dce>;
+ status = "okay";
+ rts-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>;
+};
+
+&usbh1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh1>;
+
+ vbus-supply = <®_usb_h1_vbus>;
+ status = "okay";
+};
+
+&usbotg {
+ status = "okay";
+ dr_mode = "peripheral";
+};
+
+&usdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
--
2.20.1
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^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 2/2] ARM: imx_v6_v7_defconfig: Enable SIOX bus
2019-01-11 16:49 [PATCH 1/2] ARM: dts: Add devicetree for Eckelmann CI4x10 Uwe Kleine-König
@ 2019-01-11 16:49 ` Uwe Kleine-König
2019-01-14 1:40 ` Shawn Guo
2019-01-14 1:39 ` [PATCH 1/2] ARM: dts: Add devicetree for Eckelmann CI4x10 Shawn Guo
1 sibling, 1 reply; 12+ messages in thread
From: Uwe Kleine-König @ 2019-01-11 16:49 UTC (permalink / raw)
To: Shawn Guo
Cc: Fabio Estevam, Gavin Schenk, NXP Linux Team,
Pengutronix Kernel Team, linux-arm-kernel
Now that there is a board making use of this bus is available
enable the siox code to increase compile coverage.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
arch/arm/configs/imx_v6_v7_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 5586a5074a96..05680adc355e 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -211,6 +211,7 @@ CONFIG_SPI_GPIO=y
CONFIG_SPI_IMX=y
CONFIG_SPI_FSL_DSPI=y
CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_SIOX=m
CONFIG_GPIO_MAX732X=y
CONFIG_GPIO_MC9S08DZ60=y
CONFIG_GPIO_PCA953X=y
@@ -404,6 +405,8 @@ CONFIG_NVMEM_VF610_OCOTP=y
CONFIG_TEE=y
CONFIG_OPTEE=y
CONFIG_MUX_MMIO=y
+CONFIG_SIOX=m
+CONFIG_SIOX_BUS_GPIO=m
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
--
2.20.1
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] ARM: imx_v6_v7_defconfig: Enable SIOX bus
2019-01-11 16:49 ` [PATCH 2/2] ARM: imx_v6_v7_defconfig: Enable SIOX bus Uwe Kleine-König
@ 2019-01-14 1:40 ` Shawn Guo
2019-02-05 6:17 ` Uwe Kleine-König
0 siblings, 1 reply; 12+ messages in thread
From: Shawn Guo @ 2019-01-14 1:40 UTC (permalink / raw)
To: Uwe Kleine-König
Cc: Fabio Estevam, Gavin Schenk, NXP Linux Team,
Pengutronix Kernel Team, linux-arm-kernel
On Fri, Jan 11, 2019 at 05:49:36PM +0100, Uwe Kleine-König wrote:
> Now that there is a board making use of this bus is available
> enable the siox code to increase compile coverage.
>
> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Applied, thanks.
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] ARM: imx_v6_v7_defconfig: Enable SIOX bus
2019-01-14 1:40 ` Shawn Guo
@ 2019-02-05 6:17 ` Uwe Kleine-König
2019-02-11 1:28 ` Shawn Guo
0 siblings, 1 reply; 12+ messages in thread
From: Uwe Kleine-König @ 2019-02-05 6:17 UTC (permalink / raw)
To: Shawn Guo
Cc: Fabio Estevam, Gavin Schenk, NXP Linux Team,
Pengutronix Kernel Team, linux-arm-kernel
Hello Shawn,
On Mon, Jan 14, 2019 at 09:40:35AM +0800, Shawn Guo wrote:
> On Fri, Jan 11, 2019 at 05:49:36PM +0100, Uwe Kleine-König wrote:
> > Now that there is a board making use of this bus is available
> > enable the siox code to increase compile coverage.
> >
> > Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
>
> Applied, thanks.
As you dropped patch 1 the commit log of this patch is wrong. There is
no board that makes use of siox without the first patch. If you consider
it important enough to care, we can reword to:
To increase compile coverage enable SIOX bus which is used on a
not-yet-mainlined i.MX6 machine.
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | http://www.pengutronix.de/ |
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] ARM: imx_v6_v7_defconfig: Enable SIOX bus
2019-02-05 6:17 ` Uwe Kleine-König
@ 2019-02-11 1:28 ` Shawn Guo
0 siblings, 0 replies; 12+ messages in thread
From: Shawn Guo @ 2019-02-11 1:28 UTC (permalink / raw)
To: Uwe Kleine-König
Cc: Fabio Estevam, Gavin Schenk, NXP Linux Team,
Pengutronix Kernel Team, linux-arm-kernel
On Tue, Feb 05, 2019 at 07:17:46AM +0100, Uwe Kleine-König wrote:
> Hello Shawn,
>
> On Mon, Jan 14, 2019 at 09:40:35AM +0800, Shawn Guo wrote:
> > On Fri, Jan 11, 2019 at 05:49:36PM +0100, Uwe Kleine-König wrote:
> > > Now that there is a board making use of this bus is available
> > > enable the siox code to increase compile coverage.
> > >
> > > Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
> >
> > Applied, thanks.
>
> As you dropped patch 1 the commit log of this patch is wrong. There is
> no board that makes use of siox without the first patch. If you consider
> it important enough to care, we can reword to:
>
> To increase compile coverage enable SIOX bus which is used on a
> not-yet-mainlined i.MX6 machine.
Okay, I dropped this one from my tree.
Shawn
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] ARM: dts: Add devicetree for Eckelmann CI4x10
2019-01-11 16:49 [PATCH 1/2] ARM: dts: Add devicetree for Eckelmann CI4x10 Uwe Kleine-König
2019-01-11 16:49 ` [PATCH 2/2] ARM: imx_v6_v7_defconfig: Enable SIOX bus Uwe Kleine-König
@ 2019-01-14 1:39 ` Shawn Guo
2019-02-05 8:18 ` Uwe Kleine-König
1 sibling, 1 reply; 12+ messages in thread
From: Shawn Guo @ 2019-01-14 1:39 UTC (permalink / raw)
To: Uwe Kleine-König
Cc: Fabio Estevam, Gavin Schenk, NXP Linux Team,
Pengutronix Kernel Team, linux-arm-kernel
On Fri, Jan 11, 2019 at 05:49:35PM +0100, Uwe Kleine-König wrote:
> This is one of two boards that make use of the recently introduced SIOX
> bus. Apart from the devices described in the dts it features a display
> with touch that I didn't include here because it needs some non-mainline
> change to operate correctly.
>
> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
> ---
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts | 390 ++++++++++++++++++
> 2 files changed, 391 insertions(+)
> create mode 100644 arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index bd40148a15b2..b60d759e39c0 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -397,6 +397,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
> imx6dl-cubox-i-emmc-som-v15.dtb \
> imx6dl-cubox-i-som-v15.dtb \
> imx6dl-dfi-fs700-m60.dtb \
> + imx6dl-eckelmann-ci4x10.dtb \
> imx6dl-emcon-avari.dtb \
> imx6dl-gw51xx.dtb \
> imx6dl-gw52xx.dtb \
> diff --git a/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts b/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts
> new file mode 100644
> index 000000000000..ef7a7c9d55c3
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts
> @@ -0,0 +1,390 @@
> +/*
> + * Copyright (C) 2016 Eckelmann AG.
> + * Copyright (C) 2013 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
Please use SPDX-License-Identifier.
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +
> +#include "imx6dl.dtsi"
> +
> +/ {
> + model = "Freescale i.MX6 DualLite Eckelmann CI 4X10 Board";
It's not a board produced by Freescale, right?
> + compatible = "eckelmann,imx6dl-ci4x10", "fsl,imx6dl";
Document the compatible.
> +
> + chosen {
> + stdout-path = &uart3;
> + };
> +
> + memory {
device_type = "memory";
> + reg = <0x10000000 0x40000000>;
> + };
> +
> + clocks {
> + rmii_clk: rmii-clock {
clock-rmii for node name, and put it directly under root.
> + /* This clock is provided by the phy (KSZ8091RNB) */
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <50000000>;
> + };
> + };
> +
> + reg_usb_h1_vbus: regulator@1 {
reg_xxx: regulator-xxx {
...
};
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_reg_usb_h1_vbus>;
> +
Drop the newline.
> + compatible = "regulator-fixed";
> + regulator-name = "usb_h1_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + gpio = <&gpio3 31 0>;
Use the defines in include/dt-bindings/gpio/gpio.h.
> + enable-active-high;
> + };
> +
> + siox {
> + compatible = "eckelmann,siox-gpio";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_siox>;
> +
Ditto
> + din-gpios = <&gpio6 11 0>;
> + dout-gpios = <&gpio6 8 0>;
> + dclk-gpios = <&gpio6 9 0>;
> + dld-gpios = <&gpio6 10 0>;
Ditto
> + };
> +};
> +
> +&can1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flexcan1>;
> + status = "okay";
> +};
> +
> +&can2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flexcan2>;
> + status = "okay";
> +};
> +
> +&ecspi2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_ecspi2>;
> + status = "okay";
Put the 'status' at end of property list.
> + cs-gpios = <&gpio5 12 GPIO_ACTIVE_HIGH>;
> +
> + mram: mr25h256@0 {
Use a generic node name.
> + compatible = "everspin,mr25h256";
Undocumented compatible.
> + reg = <0>;
> + spi-max-frequency = <15000000>;
> + };
> +};
> +
> +&ecspi1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_ecspi1>;
> + status = "okay";
Ditto.
> + cs-gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>;
> +
> + tpm_spi_tis@0 {
Just 'tpm' for name maybe?
> + compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
> + reg = <0>;
> + spi-max-frequency = <10000000>;
> + };
> +};
> +
> +&i2c1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c1>;
> + status = "okay";
> +
> + temp@49 {
temperature-sensor
> + compatible = "ad,ad7414";
> + reg = <0x49>;
> + };
> +
> + rtc@51 {
> + compatible = "nxp,pcf2127";
> + reg = <0x51>;
> + };
> +};
> +
> +&iomuxc {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_hog>;
> +
> + pinctrl_hog: hog {
> + fsl,pins = <
> + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x00000018 /* buzzer */
> + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x00000018 /* OUT_1 */
> + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x00000018 /* OUT_2 */
> + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x00000018 /* OUT_3 */
> + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x00000000 /* In1 */
> + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x00000000 /* In2 */
> + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x00000018 /* unused watchdog pin */
> + MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x00000018 /* unused watchdog pin */
> +
> + >;
> + };
> +
> + pinctrl_ecspi1: ecspi1grp {
> + fsl,pins = <
> + MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x000100a0
> + MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x000100a0
> + MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x000100a0
> + MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000100a0
> + >;
> + };
> +
> + pinctrl_ecspi2: ecspi2grp {
> + fsl,pins = <
> + MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x000100b1
> + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x000100b1
> + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x000100b1
> + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000100b1
> + >;
> + };
> +
> + pinctrl_enet: enetgrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
> + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x0001b098
> + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x0001b098
> + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x0001b098
> + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x0001b098
> + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x0001b098
> + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x0001b0b0
> + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x0001b0b0
> + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x0001b0b0
> + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x0001b0b0
> + MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x00000018
> + >;
> + };
> +
> + pinctrl_flexcan1: flexcan1grp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x0001b020
> + MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x0001b0b0
> + >;
> + };
> +
> + pinctrl_flexcan2: flexcan2grp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x0001b020
> + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x0001b0b0
> + >;
> + };
> +
> + pinctrl_i2c1: i2c1grp {
> + fsl,pins = <
> + /* without SION i2c doesn't detect bus busy */
> + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b820
> + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b820
> + >;
> + };
> +
> + pinctrl_pcie: pciegrp {
> + fsl,pins = <
> + MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x00000018
> + >;
> + };
> +
> + pinctrl_reg_usb_h1_vbus: reg_usb_h1_vbusgrp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0001b0b0
> + >;
> + };
> +
> + pinctrl_siox: sioxgrp {
> + fsl,pins = <
> + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x0001b010 /* DIN */
> + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0001b010 /* DOUT */
> + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0001b010 /* DCLK */
> + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x0001b010 /* DLD */
> + >;
> + };
> +
> + pinctrl_uart1_dte: uart1grp {
> + fsl,pins = <
> + MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x0001b010
> + MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x0001b010
> + MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x0001b010
> + MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x0001b010
> + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0001b010 /* DCD */
> + MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x0001b010 /* DTR */
> + MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x0001b010 /* DSR */
> + >;
> + };
> +
> + pinctrl_uart2_dte: uart2grp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x0001b010
> + MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x0001b010
> + MX6QDL_PAD_EIM_D28__UART2_RTS_B 0x0001b010
> + MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x0001b010
> + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001b010 /* DCD */
> + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b010 /* DTR */
> + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x0001b010 /* DSR */
> + >;
> + };
> +
> + pinctrl_uart3_dce: uart3grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x0001b010
> + MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x0001b010
> + >;
> + };
> +
> + pinctrl_uart4_dce: uart4grp {
> + fsl,pins = <
> + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x0001b010
> + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x0001b010
> + MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x0001b010
> + >;
> + };
> +
> + pinctrl_uart5_dce: uart5grp {
> + fsl,pins = <
> + MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x0001b010
> + MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x0001b010
> + MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x0001b010 /* RTS */
> + >;
> + };
> +
> + pinctrl_usbh1: usbh1grp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x80000000
> + >;
> + };
> +
> + pinctrl_usdhc3: usdhc3grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x00017059
> + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x00010059
> + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x00017059
> + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x00017059
> + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x00017059
> + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x00017059
> + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x00017059
> + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x00017059
> + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x00017059
> + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x00017059
> + >;
> + };
> +};
> +
> +&gpio2 {
Out of alphabetic order.
> + gpio-line-names = "buzzer", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "";
> +};
> +
> +&gpio4 {
> + gpio-line-names = "", "", "", "", "", "", "", "in2",
> + "prio2", "prio1", "aux", "", "", "", "", "",
> + "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "";
> +};
> +
> +&gpio6 {
> + gpio-line-names = "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "in1",
> + "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "";
> +};
> +
> +&fec {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_enet>;
> + phy-mode = "rmii";
> + phy-reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
> + phy-handle = <&phy>;
> + clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&rmii_clk>;
> + status = "okay";
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + phy: ethernet-phy@1 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <1>;
> + };
> + };
> +};
> +
> +&pcie {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pcie>;
> + reset-gpio = <&gpio1 20 0>;
GPIO_ACTIVE_XXX
> + status = "okay";
> +};
> +
> +&uart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart1_dte>;
> + status = "okay";
> +
Drop the newline and move 'status' to end of list.
> + uart-has-rtscts;
> + fsl,dte-mode;
> + dcd-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
> + dtr-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
> + dsr-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
> +};
> +
> +&uart2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart2_dte>;
> + status = "okay";
> +
Ditto
> + uart-has-rtscts;
> + fsl,dte-mode;
> + dcd-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
> + dtr-gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
> + dsr-gpios = <&gpio6 16 GPIO_ACTIVE_LOW>;
> +};
> +
> +&uart3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart3_dce>;
> + status = "okay";
> +};
> +
> +&uart4 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart4_dce>;
> + status = "okay";
Move to end of list.
> + rts-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>;
> +};
> +
> +&uart5 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart5_dce>;
> + status = "okay";
Ditto
> + rts-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>;
> +};
> +
> +&usbh1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usbh1>;
> +
Drop the newline.
> + vbus-supply = <®_usb_h1_vbus>;
> + status = "okay";
> +};
> +
> +&usbotg {
> + status = "okay";
Move to end of list.
Shawn
> + dr_mode = "peripheral";
> +};
> +
> +&usdhc3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc3>;
> + bus-width = <8>;
> + non-removable;
> + status = "okay";
> +};
> --
> 2.20.1
>
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^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 1/2] ARM: dts: Add devicetree for Eckelmann CI4x10
2019-01-14 1:39 ` [PATCH 1/2] ARM: dts: Add devicetree for Eckelmann CI4x10 Shawn Guo
@ 2019-02-05 8:18 ` Uwe Kleine-König
2019-02-08 9:33 ` [PATCH v2] " Uwe Kleine-König
2019-02-11 1:38 ` [PATCH 1/2] " Shawn Guo
0 siblings, 2 replies; 12+ messages in thread
From: Uwe Kleine-König @ 2019-02-05 8:18 UTC (permalink / raw)
To: Shawn Guo
Cc: Fabio Estevam, Gavin Schenk, NXP Linux Team,
Pengutronix Kernel Team, linux-arm-kernel
Hello,
On Mon, Jan 14, 2019 at 09:39:11AM +0800, Shawn Guo wrote:
> On Fri, Jan 11, 2019 at 05:49:35PM +0100, Uwe Kleine-König wrote:
> > + model = "Freescale i.MX6 DualLite Eckelmann CI 4X10 Board";
>
> It's not a board produced by Freescale, right?
Right, it's only the CPU that is produced by Freescale. So the implicit
associativity is: (Freescale i.MX6 DualLite) Eckelmann CI 4X10 Board :-)
I will make this "Eckelmann CI 4X10 Board".
> > + compatible = "eckelmann,imx6dl-ci4x10", "fsl,imx6dl";
>
> Document the compatible.
Where is this supposed to be documented? I found
Documentation/devicetree/bindings/arm/fsl.txt but that only seems to
list Freescale reference boards and e.g. wand,imx6q-wandboard isn't
there (or anywhere else).
> > + mram: mr25h256@0 {
> > + compatible = "everspin,mr25h256";
>
> Undocumented compatible.
Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt documents:
compatible : May include a device-specific string consisting of the
manufacturer and name of the chip. A list of supported chip
names follows.
"everspin" is a documented manufacturer and "mr25h256" is included in
the referenced list. So it's unclear to me what is missing here.
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | http://www.pengutronix.de/ |
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^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v2] ARM: dts: Add devicetree for Eckelmann CI4x10
2019-02-05 8:18 ` Uwe Kleine-König
@ 2019-02-08 9:33 ` Uwe Kleine-König
2019-02-08 10:48 ` Fabio Estevam
2019-02-11 1:38 ` [PATCH 1/2] " Shawn Guo
1 sibling, 1 reply; 12+ messages in thread
From: Uwe Kleine-König @ 2019-02-08 9:33 UTC (permalink / raw)
To: Shawn Guo
Cc: Fabio Estevam, Gavin Schenk, NXP Linux Team,
Pengutronix Kernel Team, linux-arm-kernel
This is one of two boards that make use of the recently introduced SIOX
bus. Apart from the devices described in the dts it features a display
with touch that I didn't include here because it needs some non-mainline
change to operate correctly.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
Hello,
this addresses all but the two issued raised by Shawn that I didn't
understand. I use this patch as a reminder that my questions regarding
these are still open. :-)
Best regards
Uwe
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts | 381 ++++++++++++++++++
2 files changed, 382 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index bd40148a15b2..b60d759e39c0 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -397,6 +397,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-cubox-i-emmc-som-v15.dtb \
imx6dl-cubox-i-som-v15.dtb \
imx6dl-dfi-fs700-m60.dtb \
+ imx6dl-eckelmann-ci4x10.dtb \
imx6dl-emcon-avari.dtb \
imx6dl-gw51xx.dtb \
imx6dl-gw52xx.dtb \
diff --git a/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts b/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts
new file mode 100644
index 000000000000..5b85e0cce210
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts
@@ -0,0 +1,381 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016 Eckelmann AG.
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "imx6dl.dtsi"
+
+/ {
+ model = "Eckelmann CI 4X10 Board";
+ compatible = "eckelmann,imx6dl-ci4x10", "fsl,imx6dl";
+
+ chosen {
+ stdout-path = &uart3;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x10000000 0x40000000>;
+ };
+
+ rmii_clk: clock-rmii {
+ /* This clock is provided by the phy (KSZ8091RNB) */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ };
+
+ reg_usb_h1_vbus: regulator-usb-h1-vbus {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usb_h1_vbus>;
+ compatible = "regulator-fixed";
+ regulator-name = "usb_h1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio3 31 0>;
+ enable-active-high;
+ };
+
+ siox {
+ compatible = "eckelmann,siox-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_siox>;
+ din-gpios = <&gpio6 11 0>;
+ dout-gpios = <&gpio6 8 0>;
+ dclk-gpios = <&gpio6 9 0>;
+ dld-gpios = <&gpio6 10 0>;
+ };
+};
+
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ status = "okay";
+};
+
+&can2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ status = "okay";
+};
+
+&ecspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2>;
+ cs-gpios = <&gpio5 12 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ mram: flash@0 {
+ compatible = "everspin,mr25h256";
+ reg = <0>;
+ spi-max-frequency = <15000000>;
+ };
+};
+
+&ecspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ cs-gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ tpm@0 {
+ compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ };
+};
+
+&gpio2 {
+ gpio-line-names = "buzzer", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio4 {
+ gpio-line-names = "", "", "", "", "", "", "", "in2",
+ "prio2", "prio1", "aux", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio6 {
+ gpio-line-names = "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "in1",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ temperature-sensor@49 {
+ compatible = "ad,ad7414";
+ reg = <0x49>;
+ };
+
+ rtc@51 {
+ compatible = "nxp,pcf2127";
+ reg = <0x51>;
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_hog: hog {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x00000018 /* buzzer */
+ MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x00000018 /* OUT_1 */
+ MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x00000018 /* OUT_2 */
+ MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x00000018 /* OUT_3 */
+ MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x00000000 /* In1 */
+ MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x00000000 /* In2 */
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x00000018 /* unused watchdog pin */
+ MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x00000018 /* unused watchdog pin */
+
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x000100a0
+ MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x000100a0
+ MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x000100a0
+ MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000100a0
+ >;
+ };
+
+ pinctrl_ecspi2: ecspi2grp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x000100b1
+ MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x000100b1
+ MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x000100b1
+ MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000100b1
+ >;
+ };
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x0001b098
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x0001b098
+ MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x0001b098
+ MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x0001b098
+ MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x0001b098
+ MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x0001b0b0
+ MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x0001b0b0
+ MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x0001b0b0
+ MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x0001b0b0
+ MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x00000018
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x0001b020
+ MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x0001b0b0
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x0001b020
+ MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x0001b0b0
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ /* without SION i2c doesn't detect bus busy */
+ MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b820
+ MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b820
+ >;
+ };
+
+ pinctrl_pcie: pciegrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x00000018
+ >;
+ };
+
+ pinctrl_reg_usb_h1_vbus: reg_usb_h1_vbusgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0001b0b0
+ >;
+ };
+
+ pinctrl_siox: sioxgrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x0001b010 /* DIN */
+ MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0001b010 /* DOUT */
+ MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0001b010 /* DCLK */
+ MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x0001b010 /* DLD */
+ >;
+ };
+
+ pinctrl_uart1_dte: uart1grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x0001b010
+ MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x0001b010
+ MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x0001b010
+ MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x0001b010
+ MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0001b010 /* DCD */
+ MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x0001b010 /* DTR */
+ MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x0001b010 /* DSR */
+ >;
+ };
+
+ pinctrl_uart2_dte: uart2grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x0001b010
+ MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x0001b010
+ MX6QDL_PAD_EIM_D28__UART2_RTS_B 0x0001b010
+ MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x0001b010
+ MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001b010 /* DCD */
+ MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b010 /* DTR */
+ MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x0001b010 /* DSR */
+ >;
+ };
+
+ pinctrl_uart3_dce: uart3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x0001b010
+ MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x0001b010
+ >;
+ };
+
+ pinctrl_uart4_dce: uart4grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x0001b010
+ MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x0001b010
+ MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x0001b010
+ >;
+ };
+
+ pinctrl_uart5_dce: uart5grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x0001b010
+ MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x0001b010
+ MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x0001b010 /* RTS */
+ >;
+ };
+
+ pinctrl_usbh1: usbh1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D30__USB_H1_OC 0x80000000
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x00017059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x00010059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x00017059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x00017059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x00017059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x00017059
+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x00017059
+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x00017059
+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x00017059
+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x00017059
+ >;
+ };
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rmii";
+ phy-reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
+ phy-handle = <&phy>;
+ clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&rmii_clk>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+ };
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie>;
+ reset-gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_dte>;
+ uart-has-rtscts;
+ fsl,dte-mode;
+ dcd-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
+ dtr-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
+ dsr-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2_dte>;
+ uart-has-rtscts;
+ fsl,dte-mode;
+ dcd-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
+ dtr-gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
+ dsr-gpios = <&gpio6 16 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3_dce>;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4_dce>;
+ rts-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart5_dce>;
+ status = "okay";
+ rts-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>;
+};
+
+&usbh1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh1>;
+ vbus-supply = <®_usb_h1_vbus>;
+ status = "okay";
+};
+
+&usbotg {
+ status = "okay";
+ dr_mode = "peripheral";
+};
+
+&usdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
--
2.20.1
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^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v2] ARM: dts: Add devicetree for Eckelmann CI4x10
2019-02-08 9:33 ` [PATCH v2] " Uwe Kleine-König
@ 2019-02-08 10:48 ` Fabio Estevam
2019-02-11 10:50 ` Uwe Kleine-König
0 siblings, 1 reply; 12+ messages in thread
From: Fabio Estevam @ 2019-02-08 10:48 UTC (permalink / raw)
To: Uwe Kleine-König
Cc: Gavin Schenk, NXP Linux Team, Pengutronix Kernel Team,
Fabio Estevam, Shawn Guo,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
Hi Uwe,
On Fri, Feb 8, 2019 at 7:33 AM Uwe Kleine-König
<u.kleine-koenig@pengutronix.de> wrote:
> + reg_usb_h1_vbus: regulator-usb-h1-vbus {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_reg_usb_h1_vbus>;
> + compatible = "regulator-fixed";
> + regulator-name = "usb_h1_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + gpio = <&gpio3 31 0>;
Please use GPIO_ACTIVE_HIGH label for better readability.
> + enable-active-high;
> + };
> +
> + siox {
> + compatible = "eckelmann,siox-gpio";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_siox>;
> + din-gpios = <&gpio6 11 0>;
> + dout-gpios = <&gpio6 8 0>;
> + dclk-gpios = <&gpio6 9 0>;
> + dld-gpios = <&gpio6 10 0>;
Same here.
> + pinctrl_usbh1: usbh1grp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x80000000
No 0x80000000 please. Use the real IOMUX setting here so that we don't
rely on the bootloader.
> +&pcie {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pcie>;
> + reset-gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>;
I guess you meant GPIO_ACTIVE_LOW here instead?
The reset-gpio polarity is ignored by the imx6 PCI driver and assumed
to be active low unless the "reset-gpio-active-high" is present.
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^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v2] ARM: dts: Add devicetree for Eckelmann CI4x10
2019-02-08 10:48 ` Fabio Estevam
@ 2019-02-11 10:50 ` Uwe Kleine-König
0 siblings, 0 replies; 12+ messages in thread
From: Uwe Kleine-König @ 2019-02-11 10:50 UTC (permalink / raw)
To: Fabio Estevam
Cc: Gavin Schenk, NXP Linux Team, Pengutronix Kernel Team,
Fabio Estevam, Shawn Guo,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
Hello Fabio,
On Fri, Feb 08, 2019 at 08:48:02AM -0200, Fabio Estevam wrote:
> On Fri, Feb 8, 2019 at 7:33 AM Uwe Kleine-König
> <u.kleine-koenig@pengutronix.de> wrote:
> > + pinctrl_usbh1: usbh1grp {
> > + fsl,pins = <
> > + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x80000000
>
> No 0x80000000 please. Use the real IOMUX setting here so that we don't
> rely on the bootloader.
>
> > +&pcie {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_pcie>;
> > + reset-gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>;
>
> I guess you meant GPIO_ACTIVE_LOW here instead?
>
> The reset-gpio polarity is ignored by the imx6 PCI driver and assumed
> to be active low unless the "reset-gpio-active-high" is present.
I improved my tooling to catch these two problems. I found quite some
offenders, will send fixes after lunch.
Thanks for catching these.
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | http://www.pengutronix.de/ |
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] ARM: dts: Add devicetree for Eckelmann CI4x10
2019-02-05 8:18 ` Uwe Kleine-König
2019-02-08 9:33 ` [PATCH v2] " Uwe Kleine-König
@ 2019-02-11 1:38 ` Shawn Guo
2019-02-11 10:59 ` Uwe Kleine-König
1 sibling, 1 reply; 12+ messages in thread
From: Shawn Guo @ 2019-02-11 1:38 UTC (permalink / raw)
To: Uwe Kleine-König
Cc: Fabio Estevam, Gavin Schenk, NXP Linux Team,
Pengutronix Kernel Team, linux-arm-kernel
On Tue, Feb 05, 2019 at 09:18:25AM +0100, Uwe Kleine-König wrote:
> > > + compatible = "eckelmann,imx6dl-ci4x10", "fsl,imx6dl";
> >
> > Document the compatible.
>
> Where is this supposed to be documented? I found
> Documentation/devicetree/bindings/arm/fsl.txt but that only seems to
> list Freescale reference boards and e.g. wand,imx6q-wandboard isn't
> there (or anywhere else).
You need to patch Documentation/devicetree/bindings/arm/fsl.yaml on my
imx/bindings (merged into for-next) branch. Reminder - please keep
bindings change as a separate patch.
>
> > > + mram: mr25h256@0 {
Just spot it - please use a generic node name.
> > > + compatible = "everspin,mr25h256";
> >
> > Undocumented compatible.
>
> Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt documents:
>
> compatible : May include a device-specific string consisting of the
> manufacturer and name of the chip. A list of supported chip
> names follows.
>
> "everspin" is a documented manufacturer and "mr25h256" is included in
> the referenced list. So it's unclear to me what is missing here.
Ah, okay. It will make my searching of compatible much harder then.
Shawn
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^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2019-02-11 10:59 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-01-11 16:49 [PATCH 1/2] ARM: dts: Add devicetree for Eckelmann CI4x10 Uwe Kleine-König
2019-01-11 16:49 ` [PATCH 2/2] ARM: imx_v6_v7_defconfig: Enable SIOX bus Uwe Kleine-König
2019-01-14 1:40 ` Shawn Guo
2019-02-05 6:17 ` Uwe Kleine-König
2019-02-11 1:28 ` Shawn Guo
2019-01-14 1:39 ` [PATCH 1/2] ARM: dts: Add devicetree for Eckelmann CI4x10 Shawn Guo
2019-02-05 8:18 ` Uwe Kleine-König
2019-02-08 9:33 ` [PATCH v2] " Uwe Kleine-König
2019-02-08 10:48 ` Fabio Estevam
2019-02-11 10:50 ` Uwe Kleine-König
2019-02-11 1:38 ` [PATCH 1/2] " Shawn Guo
2019-02-11 10:59 ` Uwe Kleine-König
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