From: Tony Lindgren <tony@atomide.com>
To: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Nishanth Menon <nm@ti.com>,
Device Tree Mailing List <devicetree@vger.kernel.org>,
jason@lakedaemon.net, Peter Ujfalusi <peter.ujfalusi@ti.com>,
marc.zyngier@arm.com, Sekhar Nori <nsekhar@ti.com>,
linux-kernel@vger.kernel.org, Tero Kristo <t-kristo@ti.com>,
Rob Herring <robh+dt@kernel.org>,
Santosh Shilimkar <ssantosh@kernel.org>,
tglx@linutronix.de,
Linux ARM Mailing List <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v5 05/10] dt-bindings: irqchip: Introduce TISCI Interrupt router bindings
Date: Tue, 12 Feb 2019 08:30:18 -0800 [thread overview]
Message-ID: <20190212163018.GL5720@atomide.com> (raw)
In-Reply-To: <20190212074237.2875-6-lokeshvutla@ti.com>
Hi,
* Lokesh Vutla <lokeshvutla@ti.com> [190212 07:43]:
> +The Interrupt Router (INTR) module provides a mechanism to route M
> +interrupt inputs to N interrupt outputs, where all M inputs are selectable
> +to be driven per N output. There is one register per output (MUXCNTL_N) that
> +controls the selection.
> +
> +
> + Interrupt Router
> + +----------------------+
> + | Inputs Outputs |
> + +-------+ | +------+ |
> + | GPIO |----------->| | irq0 | | Host IRQ
> + +-------+ | +------+ | controller
> + | . +-----+ | +-------+
> + +-------+ | . | 0 | |----->| IRQ |
> + | INTA |----------->| . +-----+ | +-------+
> + +-------+ | . . |
> + | +------+ . |
> + | | irqM | +-----+ |
> + | +------+ | N | |
> + | +-----+ |
> + +----------------------+
Is this always one-to-one mapping or can the same interrupt be routed to
multiple targets like to the SoC and some coprocessor?
> +Configuration of these MUXCNTL_N registers is done by a system controller
> +(like the Device Memory and Security Controller on K3 AM654 SoC). System
> +controller will keep track of the used and unused registers within the Router.
> +Driver should request the system controller to get the range of GIC IRQs
> +assigned to the requesting hosts. It is the drivers responsibility to keep
> +track of Host IRQs.
> +
> +Communication between the host processor running an OS and the system
> +controller happens through a protocol called TI System Control Interface
> +(TISCI protocol). For more details refer:
> +Documentation/devicetree/bindings/arm/keystone/ti,sci.txt
Care to describe a bit why the interrupts need to be routed by a system
controller?
Regards,
Tony
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-02-12 16:30 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-12 7:42 [PATCH v5 00/10] Add support for TISCI irqchip drivers Lokesh Vutla
2019-02-12 7:42 ` [PATCH v5 01/10] firmware: ti_sci: Add support to get TISCI handle using of_phandle Lokesh Vutla
2019-02-12 7:42 ` [PATCH v5 02/10] firmware: ti_sci: Add support for RM core ops Lokesh Vutla
2019-02-12 7:42 ` [PATCH v5 03/10] firmware: ti_sci: Add support for IRQ management Lokesh Vutla
2019-02-12 7:42 ` [PATCH v5 04/10] firmware: ti_sci: Add RM mapping table for am654 Lokesh Vutla
2019-02-12 7:42 ` [PATCH v5 05/10] dt-bindings: irqchip: Introduce TISCI Interrupt router bindings Lokesh Vutla
2019-02-12 16:22 ` Tony Lindgren
2019-02-13 4:25 ` Lokesh Vutla
2019-02-13 15:26 ` Tony Lindgren
2019-02-13 20:40 ` Rob Herring
2019-02-14 8:38 ` Lokesh Vutla
2019-02-14 15:41 ` Tony Lindgren
2019-02-14 17:32 ` Lokesh Vutla
2019-02-14 17:46 ` Tony Lindgren
2019-02-14 18:02 ` Lokesh Vutla
2019-02-15 16:16 ` Tony Lindgren
2019-02-16 3:29 ` Lokesh Vutla
2019-02-18 14:32 ` Tony Lindgren
2019-02-19 8:51 ` Lokesh Vutla
2019-02-19 15:35 ` Tony Lindgren
2019-02-19 16:19 ` Lokesh Vutla
2019-02-19 17:11 ` Tony Lindgren
2019-02-19 17:56 ` Tony Lindgren
2019-02-20 5:53 ` Lokesh Vutla
2019-02-20 16:36 ` Tony Lindgren
2019-02-20 17:17 ` Lokesh Vutla
2019-02-12 16:30 ` Tony Lindgren [this message]
2019-02-13 4:22 ` Lokesh Vutla
2019-02-13 15:32 ` Tony Lindgren
2019-02-14 8:40 ` Lokesh Vutla
2019-02-14 15:42 ` Tony Lindgren
2019-02-16 3:30 ` Lokesh Vutla
2019-02-18 14:35 ` Tony Lindgren
2019-02-22 10:10 ` Peter Ujfalusi
2019-02-18 15:12 ` Marc Zyngier
2019-02-18 15:27 ` Lokesh Vutla
2019-02-12 7:42 ` [PATCH v5 06/10] irqchip: ti-sci-intr: Add support for Interrupt Router driver Lokesh Vutla
2019-02-18 15:52 ` Marc Zyngier
2019-02-20 13:17 ` Lokesh Vutla
2019-03-19 12:44 ` Lokesh Vutla
2019-02-12 7:42 ` [PATCH v5 07/10] dt-bindings: irqchip: Introduce TISCI Interrupt Aggregator bindings Lokesh Vutla
2019-02-12 7:42 ` [PATCH v5 08/10] irqchip: ti-sci-inta: Add support for Interrupt Aggregator driver Lokesh Vutla
2019-02-12 7:42 ` [PATCH v5 09/10] soc: ti: Add MSI domain support for K3 Interrupt Aggregator Lokesh Vutla
2019-02-13 16:41 ` Tony Lindgren
2019-02-12 7:42 ` [PATCH v5 10/10] soc: ti: am6: Enable interrupt controller drivers Lokesh Vutla
2019-02-16 3:37 ` [PATCH v5 00/10] Add support for TISCI irqchip drivers Lokesh Vutla
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190212163018.GL5720@atomide.com \
--to=tony@atomide.com \
--cc=devicetree@vger.kernel.org \
--cc=jason@lakedaemon.net \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=lokeshvutla@ti.com \
--cc=marc.zyngier@arm.com \
--cc=nm@ti.com \
--cc=nsekhar@ti.com \
--cc=peter.ujfalusi@ti.com \
--cc=robh+dt@kernel.org \
--cc=ssantosh@kernel.org \
--cc=t-kristo@ti.com \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).