From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF235C43381 for ; Thu, 14 Feb 2019 14:40:33 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BE294222D7 for ; Thu, 14 Feb 2019 14:40:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="DO439CPf" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BE294222D7 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=VQ2R/5+7/gNXWU1mlCL39k8QE+q2IKVWQ+LfHHP13WM=; b=DO439CPfgr/7DQ ilv8klvLPAZao9pfVWtLBGIC7S2YckdO9Vba1Seu3dDbhgpSW9LdfvKutqZNmUt44+KT2kyV8uxYL ocVAOKlbH1gxonm/UQ1XOILNxvUS48k4mLUN7I2HL+exTfNdEoNNbH2r/KruvDHe3oeSpEwFBqPps DpKLYEgUJCFHw4X2QL4kz4RyJrtah5+61Phi79dEKDvQ/8g+2ryQyA+kBfL91jHGtv8SuIvqhBzrN 9qzJZ/F0ttCN4Kc8Selxh5TT837amysf9Dlg7uIl7Nb8XO8Jcq1nq4DNO6qEIe9HtxHD01Ju4Uuwp fm0nW115dKwfqD56i2lA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1guIBf-0008Oj-9i; Thu, 14 Feb 2019 14:40:27 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1guIBa-0008OG-U0 for linux-arm-kernel@lists.infradead.org; Thu, 14 Feb 2019 14:40:25 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6127580D; Thu, 14 Feb 2019 06:40:21 -0800 (PST) Received: from fuggles.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DB92F3F557; Thu, 14 Feb 2019 06:40:19 -0800 (PST) Date: Thu, 14 Feb 2019 14:40:17 +0000 From: Will Deacon To: Ard Biesheuvel Subject: Re: [PATCH 1/2] arm64: account for GICv3 LPI tables in static memblock reserve table Message-ID: <20190214144017.GG31597@fuggles.cambridge.arm.com> References: <20190213132738.10294-1-ard.biesheuvel@linaro.org> <20190213132738.10294-2-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20190213132738.10294-2-ard.biesheuvel@linaro.org> User-Agent: Mutt/1.11.1+86 (6f28e57d73f2) () X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190214_064024_194969_A5F4EF2F X-CRM114-Status: GOOD ( 22.12 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-efi@vger.kernel.org, Marc Zyngier , Catalin Marinas , linux-mm@kvack.org, James Morse , Andrew Morton , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Feb 13, 2019 at 02:27:37PM +0100, Ard Biesheuvel wrote: > In the irqchip and EFI code, we have what basically amounts to a quirk > to work around a peculiarity in the GICv3 architecture, which permits > the system memory address of LPI tables to be programmable only once > after a CPU reset. This means kexec kernels must use the same memory > as the first kernel, and thus ensure that this memory has not been > given out for other purposes by the time the ITS init code runs, which > is not very early for secondary CPUs. > > On systems with many CPUs, these reservations could overflow the > memblock reservation table, and this was addressed in commit > eff896288872 ("efi/arm: Defer persistent reservations until after > paging_init()"). However, this turns out to have made things worse, > since the allocation of page tables and heap space for the resized > memblock reservation table itself may overwrite the regions we are > attempting to reserve, which may cause all kinds of corruption, > also considering that the ITS will still be poking bits into that > memory in response to incoming MSIs. > > So instead, let's grow the static memblock reservation table on such > systems so it can accommodate these reservations at an earlier time. > This will permit us to revert the above commit in a subsequent patch. > > Signed-off-by: Ard Biesheuvel > --- > arch/arm64/include/asm/memory.h | 11 +++++++++++ > include/linux/memblock.h | 3 --- > mm/memblock.c | 10 ++++++++-- > 3 files changed, 19 insertions(+), 5 deletions(-) > > diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h > index e1ec947e7c0c..7e2b13cdd970 100644 > --- a/arch/arm64/include/asm/memory.h > +++ b/arch/arm64/include/asm/memory.h > @@ -332,6 +332,17 @@ static inline void *phys_to_virt(phys_addr_t x) > #define virt_addr_valid(kaddr) \ > (_virt_addr_is_linear(kaddr) && _virt_addr_valid(kaddr)) > > +/* > + * Given that the GIC architecture permits ITS implementations that can only be > + * configured with a LPI table address once, GICv3 systems with many CPUs may > + * end up reserving a lot of different regions after a kexec for their LPI > + * tables, as we are forced to reuse the same memory after kexec (and thus > + * reserve it persistently with EFI beforehand) > + */ > +#if defined(CONFIG_EFI) && defined(CONFIG_ARM_GIC_V3_ITS) > +#define INIT_MEMBLOCK_RESERVED_REGIONS (INIT_MEMBLOCK_REGIONS + 2 * NR_CPUS) > +#endif Assuming this "ought to be enough for anybody", then: Acked-by: Will Deacon Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel