From: Alexandre Belloni <alexandre.belloni@bootlin.com>
To: Claudiu.Beznea@microchip.com
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
sboyd@kernel.org, mturquette@baylibre.com,
linux-kernel@vger.kernel.org, Ludovic.Desroches@microchip.com,
robh+dt@kernel.org, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 2/3] clk: at91: sckc: add support for SAM9X60
Date: Mon, 18 Feb 2019 22:20:07 +0100 [thread overview]
Message-ID: <20190218212007.GW10129@piout.net> (raw)
In-Reply-To: <1550146447-1441-3-git-send-email-claudiu.beznea@microchip.com>
On 14/02/2019 12:14:32+0000, Claudiu.Beznea@microchip.com wrote:
> From: Claudiu Beznea <claudiu.beznea@microchip.com>
>
> Add support for SAM9X60.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> ---
> drivers/clk/at91/sckc.c | 30 ++++++++++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
> diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c
> index b7163d3a2269..b3075c51d260 100644
> --- a/drivers/clk/at91/sckc.c
> +++ b/drivers/clk/at91/sckc.c
> @@ -459,6 +459,36 @@ static void __init of_at91sam9x5_sckc_setup(struct device_node *np)
> CLK_OF_DECLARE(at91sam9x5_clk_sckc, "atmel,at91sam9x5-sckc",
> of_at91sam9x5_sckc_setup);
>
> +static const struct clk_slow_offsets at91sam9x60_offsets = {
> + .cr_rcen = AT91_SCKC_OFFSET_INVALID,
> + .cr_osc32en = 1,
> + .cr_osc32byp = 2,
> + .cr_oscsel = 24,
> +};
> +
> +static void __init of_at91sam9x60_sckc_setup(struct device_node *np)
> +{
> + struct device_node *childnp;
> + void (*clk_setup)(struct device_node *np, void __iomem *io,
> + const struct clk_slow_offsets *offsets);
> + const struct of_device_id *clk_id;
> + void __iomem *regbase = of_iomap(np, 0);
> +
> + if (!regbase)
> + return;
> +
> + for_each_child_of_node(np, childnp) {
> + clk_id = of_match_node(sckc_clk_ids, childnp);
> + if (!clk_id)
> + continue;
> + clk_setup = clk_id->data;
> + clk_setup(childnp, regbase, &at91sam9x60_offsets);
> + }
You actually need to have new bindings. The sam9x60 registration should
look more like the sama5d4 registration. I have a rework for the sam9x5
sckc that I will send this week to have a proper binding (i.e: no
children).
However, there is a fundamental change in the sam9x60, previously, the
sckc had only one output clock. the sam9x60 has both td_slck and
md_slck. Both need to be accessible because they are input to the PMC.
This means you will have to register the sckc with of_clk_hw_onecell_get
as the get callback.
We could still decide to do the same with sam9x5 even if it has only one
output clock.
--
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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linux-arm-kernel mailing list
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next prev parent reply other threads:[~2019-02-18 21:20 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-14 12:14 [PATCH v2 0/3] add slow clock support for SAM9X60 Claudiu.Beznea
2019-02-14 12:14 ` [PATCH v2 1/3] clk: at91: sckc: add support to specify registers bit offsets Claudiu.Beznea
2019-02-18 21:08 ` Alexandre Belloni
2019-02-19 9:17 ` Claudiu.Beznea
2019-02-14 12:14 ` [PATCH v2 2/3] clk: at91: sckc: add support for SAM9X60 Claudiu.Beznea
2019-02-18 21:20 ` Alexandre Belloni [this message]
2019-02-19 9:17 ` Claudiu.Beznea
2019-02-20 11:06 ` Alexandre Belloni
2019-02-14 12:14 ` [PATCH v2 3/3] dt-bindings: clk: at91: add bindings for SAM9X60's slow clock controller Claudiu.Beznea
2019-02-18 20:04 ` Rob Herring
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