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From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
To: honghui.zhang@mediatek.com
Cc: youlin.pei@mediatek.com, ryder.lee@mediatek.com,
	poza@codeaurora.org, fred@fredlawl.com,
	linux-pci@vger.kernel.org, rafael.j.wysocki@intel.com,
	linux-kernel@vger.kernel.org, jianjun.wang@mediatek.com,
	linux-mediatek@lists.infradead.org, bhelgaas@google.com,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v3 2/2] PCI: mediatek: Enlarge PCIe2AHB window size to support 4GB DRAM
Date: Thu, 28 Feb 2019 17:42:57 +0000
Message-ID: <20190228174257.GA26501@e107981-ln.cambridge.arm.com> (raw)
In-Reply-To: <1548999367-11733-3-git-send-email-honghui.zhang@mediatek.com>

On Fri, Feb 01, 2019 at 01:36:07PM +0800, honghui.zhang@mediatek.com wrote:
> From: Honghui Zhang <honghui.zhang@mediatek.com>
> 
> The PCIE_AXI_WINDOW0 defines the translate window size for the request
> from EP side. Request outside of this window will be treated as
> unsupported request.
> 
> Enlarge this window size from fls(0xffffffff) to 2^33 to support 8GB
> translate address range then EP DMA is capable of fully access 4GB
> DRAM range(physical DRAM is start from 0x40000000).

I have rewritten both patches logs with the aim of merging them even if
it is quite late in the cycle, first you have to explain something to
me.

fls(0xffffffff) = 0x1f, which by your logic -> 2^31

What does it mean given what you say above ? That PCI devices can't
do _any_ DMA in the current setting (given the DRAM start address) ?

Lorenzo

> Reported-by: Bjorn Helgaas <bhelgaas@google.com>
> Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
> ---
>  drivers/pci/controller/pcie-mediatek.c | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
> index c42fe5c..0b6c728 100644
> --- a/drivers/pci/controller/pcie-mediatek.c
> +++ b/drivers/pci/controller/pcie-mediatek.c
> @@ -90,6 +90,12 @@
>  #define AHB2PCIE_SIZE(x)	((x) & GENMASK(4, 0))
>  #define PCIE_AXI_WINDOW0	0x448
>  #define WIN_ENABLE		BIT(7)
> +/*
> + * Define PCIe to AHB window size as 2^33 to support max 8GB address space
> + * translate, support least 4GB DRAM size access from EP DMA(physical DRAM
> + * start from 0x40000000).
> + */
> +#define PCIE2AHB_SIZE	0x21
>  
>  /* PCIe V2 configuration transaction header */
>  #define PCIE_CFG_HEADER0	0x460
> @@ -713,7 +719,7 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
>  	writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
>  
>  	/* Set PCIe to AXI translation memory space.*/
> -	val = fls(0xffffffff) | WIN_ENABLE;
> +	val = PCIE2AHB_SIZE | WIN_ENABLE;
>  	writel(val, port->base + PCIE_AXI_WINDOW0);
>  
>  	return 0;
> -- 
> 2.6.4
> 

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Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-02-01  5:36 [PATCH v3 0/2] PCI: mediatek: enable whole MMIO range and enlarge the PCIe2AHB window size honghui.zhang
2019-02-01  5:36 ` [PATCH v3 1/2] PCI: mediatek: Enable the whole memory mapped IO range honghui.zhang
2019-02-01  5:36 ` [PATCH v3 2/2] PCI: mediatek: Enlarge PCIe2AHB window size to support 4GB DRAM honghui.zhang
2019-02-28 17:42   ` Lorenzo Pieralisi [this message]
2019-03-01  1:58     ` Honghui Zhang
2019-02-12  3:32 ` [SPAM][PATCH v3 0/2] PCI: mediatek: enable whole MMIO range and enlarge the PCIe2AHB window size Ryder Lee
2019-03-01 11:30 ` [PATCH " Lorenzo Pieralisi

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