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Received: from j217100.upc-j.chello.nl ([24.132.217.100] helo=hirez.programming.kicks-ass.net) by merlin.infradead.org with esmtpsa (Exim 4.90_1 #2 (Red Hat Linux)) id 1hRX0X-00075i-Do; Fri, 17 May 2019 07:10:21 +0000 Received: by hirez.programming.kicks-ass.net (Postfix, from userid 1000) id 9ED092029906B; Fri, 17 May 2019 09:10:18 +0200 (CEST) Date: Fri, 17 May 2019 09:10:18 +0200 From: Peter Zijlstra To: Raphael Gault Subject: Re: [PATCH 4/6] arm64: pmu: Add hook to handle pmu-related undefined instructions Message-ID: <20190517071018.GH2623@hirez.programming.kicks-ass.net> References: <20190516132148.10085-1-raphael.gault@arm.com> <20190516132148.10085-5-raphael.gault@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20190516132148.10085-5-raphael.gault@arm.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, acme@kernel.org, mingo@redhat.com, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, May 16, 2019 at 02:21:46PM +0100, Raphael Gault wrote: > In order to prevent the userspace processes which are trying to access > the registers from the pmu registers on a big.LITTLE environment we > introduce a hook to handle undefined instructions. > > The goal here is to prevent the process to be interrupted by a signal > when the error is caused by the task being scheduled while accessing > a counter, causing the counter access to be invalid. As we are not able > to know efficiently the number of counters available physically on both > pmu in that context we consider that any faulting access to a counter > which is architecturally correct should not cause a SIGILL signal if > the permissions are set accordingly. The other approach is using rseq for this; with that you can guarantee it will never issue the instruction on a wrong CPU. That said; emulating the thing isn't horrible either. > + /* > + * We put 0 in the target register if we > + * are reading from pmu register. If we are > + * writing, we do nothing. > + */ Wait _what_ ?!? userspace can _WRITE_ to these registers? _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel