From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.5 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76AFDC04AB4 for ; Fri, 17 May 2019 08:27:05 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 48DF820818 for ; Fri, 17 May 2019 08:27:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="TFUoC1PY" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 48DF820818 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=infradead.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=zs1ZjIAUG3ReUrh+yOKStHLdgQCJdH4k+h/S4aK2dyc=; b=TFUoC1PY6wktXp ZKEzw01TpAiIFC+I6gkD5hBmuAQdd+kKpFY9KWviZTC/KHaep/IDMTcYZgIy/OJBN+ZWcxQwfaBKj B4NBLzqWShOhsl90W4Uvzkf9OmO7KExBwWrq/GMPWRvWwBChIWyn+sVqxvEpyv9dNkfDCPfvglnKz /LPcqREUluCUOaQr7jDwEPNyyms9DYx064umj5zo9L5Fcyme/WxOY5nDj0Sz8HaMapr1Q2GO9skEM 52+fXineuTM/7YAnRi45+X65WnRNSvmAJRquImeeF+c40H7O9l5C3J/G0gmORp/t+yGWQ7MBKyuqy xSAl6om1pY3FA4ueZ0Dg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hRYCh-0001cW-4l; Fri, 17 May 2019 08:26:59 +0000 Received: from j217100.upc-j.chello.nl ([24.132.217.100] helo=hirez.programming.kicks-ass.net) by bombadil.infradead.org with esmtpsa (Exim 4.90_1 #2 (Red Hat Linux)) id 1hRYCf-0001bw-3l; Fri, 17 May 2019 08:26:57 +0000 Received: by hirez.programming.kicks-ass.net (Postfix, from userid 1000) id 126B52029F888; Fri, 17 May 2019 10:26:55 +0200 (CEST) Date: Fri, 17 May 2019 10:26:55 +0200 From: Peter Zijlstra To: Mark Rutland Subject: Re: [PATCH 4/6] arm64: pmu: Add hook to handle pmu-related undefined instructions Message-ID: <20190517082655.GK2623@hirez.programming.kicks-ass.net> References: <20190516132148.10085-1-raphael.gault@arm.com> <20190516132148.10085-5-raphael.gault@arm.com> <20190517071018.GH2623@hirez.programming.kicks-ass.net> <20190517080419.dziz4iqc7t4mpoej@blommer> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20190517080419.dziz4iqc7t4mpoej@blommer> User-Agent: Mutt/1.10.1 (2018-07-13) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: catalin.marinas@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, acme@kernel.org, Raphael Gault , mingo@redhat.com, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, May 17, 2019 at 09:04:20AM +0100, Mark Rutland wrote: > Remember that this is in an undefined (trap) handler. > > If userspace _attempts_ to write to the registers, the CPU will trap to the > kernel. The comment is perhaps misleading; when we "do nothing", the common > trap handling code will send a SIGILL to userspace. > > It would probably be better to say something like: > > /* > * If userspace is tries to read a counter that doesn't exist on this > * CPU, we emulate it as reading as zero. This happens if userspace is > * preempted between reading the idx and actually reading the counter, > * and the seqlock and idx have already changed, so it's as-if the > * counter has been reprogrammed with a different event. Might be good to mention that userspace will/should discard the value it reads, and therefore any value is good (including 0). > * We don't permit userspace to write to these registers, and will > * inject a SIGILL. > */ > > There is one caveat: userspace can write to PMSELR without trapping, so we will > have to context-switch with the task. That only affects indirect addressing of > PMU registers, and doesn't have a functional effect on the behaviour of the > PMU, so that's benign from the PoV of perf. Sad though; ideally you'd state that indirect addressing is out-of-bounds and they get to keep the pieces. But I suspect you're right that people will do it anyway and complain once it comes apart. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel