[PATCH resend 0/2] Marvell A7k/A8k thermal throttling

[PATCH resend 0/2] Marvell A7k/A8k thermal throttling

[Miquel Raynal]

Hello,

This series works on top of Gregory's series adding both CPUfreq (already
merged) and a suitable AP806 clock driver. These two patches can fly
as-is and do not depend on Gregory's work to apply and should probably
merged independently.

With his patches, all the pieces where available to enable thermal
throttling on the AP806 embedded in Marvell Armada 7k/8k SoCs. This is
just the glue to make it actually work.

Patch 1 changes the core numbering in the thermal-zone node to be in
sync with the CPU numbering in the DT (from 0 to 3 instead of from 1
to 4). Patch 2 adds trip points and cooling maps to actually enable
the feature.

Tested with an Armada 7k DB.

Thanks,
Miquèl

Miquel Raynal (2):
  arm64: dts: marvell: Change core numbering in AP806 thermal-node
  arm64: dts: marvell: Enable AP806 thermal throttling with CPUfreq

 .../boot/dts/marvell/armada-ap806-dual.dtsi   |   2 +
 .../boot/dts/marvell/armada-ap806-quad.dtsi   |   5 +
 arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 110 +++++++++++++++---
 3 files changed, 103 insertions(+), 14 deletions(-)

-- 
2.19.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH resend 1/2] arm64: dts: marvell: Change core numbering in AP806 thermal-node

[Miquel Raynal]

When adding thermal nodes, the CPUs have been named from 1 to 4 while
usually everywhere else they are referred as 0-3. Let's change this to
be consistent with later changes when we will use CPUfreq and CPU
phandles as cooling devices to avoid inconsistencies in the nodes
numbering.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
 arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index 28e9dbcf47e3..df90e8b1daa8 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -324,7 +324,7 @@
 			cooling-maps { };
 		};
 
-		ap_thermal_cpu1: ap-thermal-cpu1 {
+		ap_thermal_cpu0: ap-thermal-cpu0 {
 			polling-delay-passive = <1000>;
 			polling-delay = <1000>;
 
@@ -334,7 +334,7 @@
 			cooling-maps { };
 		};
 
-		ap_thermal_cpu2: ap-thermal-cpu2 {
+		ap_thermal_cpu1: ap-thermal-cpu1 {
 			polling-delay-passive = <1000>;
 			polling-delay = <1000>;
 
@@ -344,7 +344,7 @@
 			cooling-maps { };
 		};
 
-		ap_thermal_cpu3: ap-thermal-cpu3 {
+		ap_thermal_cpu2: ap-thermal-cpu2 {
 			polling-delay-passive = <1000>;
 			polling-delay = <1000>;
 
@@ -354,7 +354,7 @@
 			cooling-maps { };
 		};
 
-		ap_thermal_cpu4: ap-thermal-cpu4 {
+		ap_thermal_cpu3: ap-thermal-cpu3 {
 			polling-delay-passive = <1000>;
 			polling-delay = <1000>;
 
-- 
2.19.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH resend 2/2] arm64: dts: marvell: Enable AP806 thermal throttling with CPUfreq

[Miquel Raynal]

Avoid critical temperatures in the AP806 by adding the relevant trip
points/cooling-maps using CPUfreq as cooling device.

So far, when the temperature reaches 100°C in the thermal IP of the
AP806 (close enough from the 2/4 cores) an overheat interrupt is
raised. The thermal core then shutdowns the system to avoid damaging
the hardware.

Adding CPUfreq as a cooling device could help avoiding such very
critical situation. For that, we enable thermal throttling by
defining, for each CPU, two trip points with the corresponding cooling
'intensity'. CPU0 and CPU1 are in the same cluster and are driven by
the same clock. Same applies for CPU2 and CPU3, if available. So
changing the frequency of one will also change the frequency of the
other one, hence the use of two cooling devices per core.

The heat map is as follow:
- Below 85°C: the cluster runs at the highest frequency
  (e.g: 1200MHz).
- Between 85°C and 95°C: there are two trip points at half
  (e.g: 600MHz) and a third (e.g: 400MHz) of the highest frequency.
- Above 95°C the cluster runs at a quarter of the highest frequency
  (e.g: 300MHz).
- At 100°C the platform is shutdown.

Suggested-by: Omri Itach <omrii@marvell.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
 .../boot/dts/marvell/armada-ap806-dual.dtsi   |   2 +
 .../boot/dts/marvell/armada-ap806-quad.dtsi   |   5 +
 arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 102 ++++++++++++++++--
 3 files changed, 99 insertions(+), 10 deletions(-)

diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
index 861fd21922c4..9024a2d9db07 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
@@ -20,12 +20,14 @@
 			compatible = "arm,cortex-a72";
 			reg = <0x000>;
 			enable-method = "psci";
+			#cooling-cells = <2>;
 		};
 		cpu1: cpu@1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a72";
 			reg = <0x001>;
 			enable-method = "psci";
+			#cooling-cells = <2>;
 		};
 	};
 };
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
index 472211159979..4b81ffcb901a 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
@@ -21,6 +21,7 @@
 			reg = <0x000>;
 			enable-method = "psci";
 			clocks = <&cpu_clk 0>;
+			#cooling-cells = <2>;
 		};
 		cpu1: cpu@1 {
 			device_type = "cpu";
@@ -28,6 +29,7 @@
 			reg = <0x001>;
 			enable-method = "psci";
 			clocks = <&cpu_clk 0>;
+			#cooling-cells = <2>;
 		};
 		cpu2: cpu@100 {
 			device_type = "cpu";
@@ -35,6 +37,7 @@
 			reg = <0x100>;
 			enable-method = "psci";
 			clocks = <&cpu_clk 1>;
+			#cooling-cells = <2>;
 		};
 		cpu3: cpu@101 {
 			device_type = "cpu";
@@ -42,6 +45,8 @@
 			reg = <0x101>;
 			enable-method = "psci";
 			clocks = <&cpu_clk 1>;
+			#cooling-cells = <2>;
 		};
 	};
+
 };
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index df90e8b1daa8..83265cd2d7a1 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -303,8 +303,6 @@
 	 *
 	 * Only one thermal zone per AP/CP may trigger interrupts at a time, the
 	 * first one that will have a critical trip point will be chosen.
-	 *
-	 * The cooling maps are always empty as there are no cooling devices.
 	 */
 	thermal-zones {
 		ap_thermal_ic: ap-thermal-ic {
@@ -330,8 +328,29 @@
 
 			thermal-sensors = <&ap_thermal 1>;
 
-			trips { };
-			cooling-maps { };
+			trips {
+				cpu0_hot: cpu0-hot {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				cpu0_emerg: cpu0-emerg {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+			};
+
+			cooling-maps {
+				map0_hot: map0-hot {
+					trip = <&cpu0_hot>;
+					cooling-device = <&cpu0 1 2>, <&cpu1 1 2>;
+				};
+				map0_emerg: map0-ermerg {
+					trip = <&cpu0_emerg>;
+					cooling-device = <&cpu0 3 3>, <&cpu1 3 3>;
+				};
+			};
 		};
 
 		ap_thermal_cpu1: ap-thermal-cpu1 {
@@ -340,8 +359,29 @@
 
 			thermal-sensors = <&ap_thermal 2>;
 
-			trips { };
-			cooling-maps { };
+			trips {
+				cpu1_hot: cpu1-hot {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				cpu1_emerg: cpu1-emerg {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+			};
+
+			cooling-maps {
+				map1_hot: map1-hot {
+					trip = <&cpu1_hot>;
+					cooling-device = <&cpu0 1 2>, <&cpu1 1 2>;
+				};
+				map1_emerg: map1-emerg {
+					trip = <&cpu1_emerg>;
+					cooling-device = <&cpu0 3 3>, <&cpu1 3 3>;
+				};
+			};
 		};
 
 		ap_thermal_cpu2: ap-thermal-cpu2 {
@@ -350,8 +390,29 @@
 
 			thermal-sensors = <&ap_thermal 3>;
 
-			trips { };
-			cooling-maps { };
+			trips {
+				cpu2_hot: cpu2-hot {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				cpu2_emerg: cpu2-emerg {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+			};
+
+			cooling-maps {
+				map2_hot: map2-hot {
+					trip = <&cpu2_hot>;
+					cooling-device = <&cpu2 1 2>, <&cpu3 1 2>;
+				};
+				map2_emerg: map2-emerg {
+					trip = <&cpu2_emerg>;
+					cooling-device = <&cpu2 3 3>, <&cpu3 3 3>;
+				};
+			};
 		};
 
 		ap_thermal_cpu3: ap-thermal-cpu3 {
@@ -360,8 +421,29 @@
 
 			thermal-sensors = <&ap_thermal 4>;
 
-			trips { };
-			cooling-maps { };
+			trips {
+				cpu3_hot: cpu3-hot {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				cpu3_emerg: cpu3-emerg {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+			};
+
+			cooling-maps {
+				map3_hot: map3-bhot {
+					trip = <&cpu3_hot>;
+					cooling-device = <&cpu2 1 2>, <&cpu3 1 2>;
+				};
+				map3_emerg: map3-emerg {
+					trip = <&cpu3_emerg>;
+					cooling-device = <&cpu2 3 3>, <&cpu3 3 3>;
+				};
+			};
 		};
 	};
 };
-- 
2.19.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH resend 0/2] Marvell A7k/A8k thermal throttling

[Gregory CLEMENT]

Miquel Raynal <miquel.raynal@bootlin.com> writes:

> Hello,
>
> This series works on top of Gregory's series adding both CPUfreq (already
> merged) and a suitable AP806 clock driver. These two patches can fly
> as-is and do not depend on Gregory's work to apply and should probably
> merged independently.
>
> With his patches, all the pieces where available to enable thermal
> throttling on the AP806 embedded in Marvell Armada 7k/8k SoCs. This is
> just the glue to make it actually work.
>
> Patch 1 changes the core numbering in the thermal-zone node to be in
> sync with the CPU numbering in the DT (from 0 to 3 instead of from 1
> to 4). Patch 2 adds trip points and cooling maps to actually enable
> the feature.
>
> Tested with an Armada 7k DB.
>
> Thanks,
> Miquèl
>
> Miquel Raynal (2):
>   arm64: dts: marvell: Change core numbering in AP806 thermal-node
>   arm64: dts: marvell: Enable AP806 thermal throttling with CPUfreq

Both pacthes applied on mvebu/dt64

Thanks,

Gregory

>
>  .../boot/dts/marvell/armada-ap806-dual.dtsi   |   2 +
>  .../boot/dts/marvell/armada-ap806-quad.dtsi   |   5 +
>  arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 110 +++++++++++++++---
>  3 files changed, 103 insertions(+), 14 deletions(-)
>
> -- 
> 2.19.1
>

-- 
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel