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* [PATCH v2 1/2] ARM: dts: vf610-zii-dev: Fix incorrect UART2 pin assignment
@ 2019-05-22  7:20 Andrey Smirnov
  2019-05-22  7:20 ` [PATCH v2 2/2] ARM: dts: vf610-zii-dev: Add QSPI node Andrey Smirnov
  2019-05-23 12:56 ` [PATCH v2 1/2] ARM: dts: vf610-zii-dev: Fix incorrect UART2 pin assignment Shawn Guo
  0 siblings, 2 replies; 3+ messages in thread
From: Andrey Smirnov @ 2019-05-22  7:20 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Andrew Lunn, Andrey Smirnov, Shawn Guo, linux-kernel,
	Fabio Estevam, Chris Healy

UART2 is connected to PTD22/23, not PTD0/1. Fix corresponding pinmux
node.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
 arch/arm/boot/dts/vf610-zii-dev.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/vf610-zii-dev.dtsi b/arch/arm/boot/dts/vf610-zii-dev.dtsi
index 0507e6dcbb21..1f2e65ae2bd6 100644
--- a/arch/arm/boot/dts/vf610-zii-dev.dtsi
+++ b/arch/arm/boot/dts/vf610-zii-dev.dtsi
@@ -385,8 +385,8 @@
 
 	pinctrl_uart2: uart2grp {
 		fsl,pins = <
-			VF610_PAD_PTD0__UART2_TX	0x21a2
-			VF610_PAD_PTD1__UART2_RX	0x21a1
+			VF610_PAD_PTD23__UART2_TX	0x21a2
+			VF610_PAD_PTD22__UART2_RX	0x21a1
 		>;
 	};
 
-- 
2.21.0


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^ permalink raw reply	[flat|nested] 3+ messages in thread

* [PATCH v2 2/2] ARM: dts: vf610-zii-dev: Add QSPI node
  2019-05-22  7:20 [PATCH v2 1/2] ARM: dts: vf610-zii-dev: Fix incorrect UART2 pin assignment Andrey Smirnov
@ 2019-05-22  7:20 ` Andrey Smirnov
  2019-05-23 12:56 ` [PATCH v2 1/2] ARM: dts: vf610-zii-dev: Fix incorrect UART2 pin assignment Shawn Guo
  1 sibling, 0 replies; 3+ messages in thread
From: Andrey Smirnov @ 2019-05-22  7:20 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Andrew Lunn, Andrey Smirnov, Shawn Guo, linux-kernel,
	Fabio Estevam, Chris Healy

Both rev C and rev B of the board come with two QSPI-NOR chips
attached to the SoC. Add DT code describing all of this.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---

Changes since [v1]:

  - Small spelling fixes in comment block
  
[v1] lore.kernel.org/r/20190513035909.30460-2-andrew.smirnov@gmail.com

 arch/arm/boot/dts/vf610-zii-dev.dtsi | 48 ++++++++++++++++++++++++----
 1 file changed, 42 insertions(+), 6 deletions(-)

diff --git a/arch/arm/boot/dts/vf610-zii-dev.dtsi b/arch/arm/boot/dts/vf610-zii-dev.dtsi
index 1f2e65ae2bd6..a1b4ccee2a10 100644
--- a/arch/arm/boot/dts/vf610-zii-dev.dtsi
+++ b/arch/arm/boot/dts/vf610-zii-dev.dtsi
@@ -177,6 +177,36 @@
 	status = "okay";
 };
 
+&qspi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_qspi0>;
+	status = "okay";
+
+	/*
+	 * Attached MT25QL02 can go up to 90Mhz in DTR and 166 in STR
+	 * modes, so, spi-max-frequency is limited to 90MHz
+	 */
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <90000000>;
+		spi-rx-bus-width = <4>;
+		reg = <0>;
+		m25p,fast-read;
+	};
+
+	flash@2 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <90000000>;
+		spi-rx-bus-width = <4>;
+		reg = <2>;
+		m25p,fast-read;
+	};
+};
+
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart0>;
@@ -360,12 +390,18 @@
 
 	pinctrl_qspi0: qspi0grp {
 		fsl,pins = <
-			VF610_PAD_PTD7__QSPI0_B_QSCK	0x31c3
-			VF610_PAD_PTD8__QSPI0_B_CS0	0x31ff
-			VF610_PAD_PTD9__QSPI0_B_DATA3	0x31c3
-			VF610_PAD_PTD10__QSPI0_B_DATA2	0x31c3
-			VF610_PAD_PTD11__QSPI0_B_DATA1	0x31c3
-			VF610_PAD_PTD12__QSPI0_B_DATA0	0x31c3
+			VF610_PAD_PTD0__QSPI0_A_QSCK	0x38c2
+			VF610_PAD_PTD1__QSPI0_A_CS0	0x38c2
+			VF610_PAD_PTD2__QSPI0_A_DATA3	0x38c3
+			VF610_PAD_PTD3__QSPI0_A_DATA2	0x38c3
+			VF610_PAD_PTD4__QSPI0_A_DATA1	0x38c3
+			VF610_PAD_PTD5__QSPI0_A_DATA0	0x38c3
+			VF610_PAD_PTD7__QSPI0_B_QSCK	0x38c2
+			VF610_PAD_PTD8__QSPI0_B_CS0	0x38c2
+			VF610_PAD_PTD9__QSPI0_B_DATA3	0x38c3
+			VF610_PAD_PTD10__QSPI0_B_DATA2	0x38c3
+			VF610_PAD_PTD11__QSPI0_B_DATA1	0x38c3
+			VF610_PAD_PTD12__QSPI0_B_DATA0	0x38c3
 		>;
 	};
 
-- 
2.21.0


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linux-arm-kernel@lists.infradead.org
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^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [PATCH v2 1/2] ARM: dts: vf610-zii-dev: Fix incorrect UART2 pin assignment
  2019-05-22  7:20 [PATCH v2 1/2] ARM: dts: vf610-zii-dev: Fix incorrect UART2 pin assignment Andrey Smirnov
  2019-05-22  7:20 ` [PATCH v2 2/2] ARM: dts: vf610-zii-dev: Add QSPI node Andrey Smirnov
@ 2019-05-23 12:56 ` Shawn Guo
  1 sibling, 0 replies; 3+ messages in thread
From: Shawn Guo @ 2019-05-23 12:56 UTC (permalink / raw)
  To: Andrey Smirnov
  Cc: Andrew Lunn, Fabio Estevam, Chris Healy, linux-arm-kernel, linux-kernel

On Wed, May 22, 2019 at 12:20:51AM -0700, Andrey Smirnov wrote:
> UART2 is connected to PTD22/23, not PTD0/1. Fix corresponding pinmux
> node.
> 
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Chris Healy <cphealy@gmail.com>
> Cc: Andrew Lunn <andrew@lunn.ch>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org

Applied both, thanks.

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^ permalink raw reply	[flat|nested] 3+ messages in thread

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2019-05-22  7:20 [PATCH v2 1/2] ARM: dts: vf610-zii-dev: Fix incorrect UART2 pin assignment Andrey Smirnov
2019-05-22  7:20 ` [PATCH v2 2/2] ARM: dts: vf610-zii-dev: Add QSPI node Andrey Smirnov
2019-05-23 12:56 ` [PATCH v2 1/2] ARM: dts: vf610-zii-dev: Fix incorrect UART2 pin assignment Shawn Guo

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