From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: acme@kernel.org
Cc: suzuki.poulose@arm.com, peterz@infradead.org,
coresight@lists.linaro.org, linux-kernel@vger.kernel.org,
alexander.shishkin@linux.intel.com, mingo@redhat.com,
leo.yan@linaro.org, namhyung@kernel.org, jolsa@redhat.com,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 13/17] perf tools: Use traceID aware memory callback API
Date: Fri, 24 May 2019 11:35:04 -0600 [thread overview]
Message-ID: <20190524173508.29044-14-mathieu.poirier@linaro.org> (raw)
In-Reply-To: <20190524173508.29044-1-mathieu.poirier@linaro.org>
When working with CPU-wide traces different traceID may be found in the
same stream. As such we need to use the decoder callback that provides
the traceID in order to know the thread context being decoded.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
.../perf/util/cs-etm-decoder/cs-etm-decoder.c | 14 +++----
.../perf/util/cs-etm-decoder/cs-etm-decoder.h | 3 +-
tools/perf/util/cs-etm.c | 41 +++++++++++++------
3 files changed, 36 insertions(+), 22 deletions(-)
diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c
index 4303d2d00d31..87264b79de0e 100644
--- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c
+++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c
@@ -41,15 +41,14 @@ static u32
cs_etm_decoder__mem_access(const void *context,
const ocsd_vaddr_t address,
const ocsd_mem_space_acc_t mem_space __maybe_unused,
+ const u8 trace_chan_id,
const u32 req_size,
u8 *buffer)
{
struct cs_etm_decoder *decoder = (struct cs_etm_decoder *) context;
- return decoder->mem_access(decoder->data,
- address,
- req_size,
- buffer);
+ return decoder->mem_access(decoder->data, trace_chan_id,
+ address, req_size, buffer);
}
int cs_etm_decoder__add_mem_access_cb(struct cs_etm_decoder *decoder,
@@ -58,9 +57,10 @@ int cs_etm_decoder__add_mem_access_cb(struct cs_etm_decoder *decoder,
{
decoder->mem_access = cb_func;
- if (ocsd_dt_add_callback_mem_acc(decoder->dcd_tree, start, end,
- OCSD_MEM_SPACE_ANY,
- cs_etm_decoder__mem_access, decoder))
+ if (ocsd_dt_add_callback_trcid_mem_acc(decoder->dcd_tree, start, end,
+ OCSD_MEM_SPACE_ANY,
+ cs_etm_decoder__mem_access,
+ decoder))
return -1;
return 0;
diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h
index 6ae7ab4cf5fe..11f3391d06f2 100644
--- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h
+++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h
@@ -19,8 +19,7 @@ struct cs_etm_packet_queue;
struct cs_etm_queue;
-typedef u32 (*cs_etm_mem_cb_type)(struct cs_etm_queue *, u64,
- size_t, u8 *);
+typedef u32 (*cs_etm_mem_cb_type)(struct cs_etm_queue *, u8, u64, size_t, u8 *);
struct cs_etmv3_trace_params {
u32 reg_ctrl;
diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c
index 7e3b4d10f5c4..2483293266d8 100644
--- a/tools/perf/util/cs-etm.c
+++ b/tools/perf/util/cs-etm.c
@@ -491,8 +491,8 @@ static u8 cs_etm__cpu_mode(struct cs_etm_queue *etmq, u64 address)
}
}
-static u32 cs_etm__mem_access(struct cs_etm_queue *etmq, u64 address,
- size_t size, u8 *buffer)
+static u32 cs_etm__mem_access(struct cs_etm_queue *etmq, u8 trace_chan_id,
+ u64 address, size_t size, u8 *buffer)
{
u8 cpumode;
u64 offset;
@@ -501,6 +501,8 @@ static u32 cs_etm__mem_access(struct cs_etm_queue *etmq, u64 address,
struct machine *machine;
struct addr_location al;
+ (void)trace_chan_id;
+
if (!etmq)
return 0;
@@ -687,10 +689,12 @@ void cs_etm__reset_last_branch_rb(struct cs_etm_traceid_queue *tidq)
}
static inline int cs_etm__t32_instr_size(struct cs_etm_queue *etmq,
- u64 addr) {
+ u8 trace_chan_id, u64 addr)
+{
u8 instrBytes[2];
- cs_etm__mem_access(etmq, addr, ARRAY_SIZE(instrBytes), instrBytes);
+ cs_etm__mem_access(etmq, trace_chan_id, addr,
+ ARRAY_SIZE(instrBytes), instrBytes);
/*
* T32 instruction size is indicated by bits[15:11] of the first
* 16-bit word of the instruction: 0b11101, 0b11110 and 0b11111
@@ -719,6 +723,7 @@ u64 cs_etm__last_executed_instr(const struct cs_etm_packet *packet)
}
static inline u64 cs_etm__instr_addr(struct cs_etm_queue *etmq,
+ u64 trace_chan_id,
const struct cs_etm_packet *packet,
u64 offset)
{
@@ -726,7 +731,8 @@ static inline u64 cs_etm__instr_addr(struct cs_etm_queue *etmq,
u64 addr = packet->start_addr;
while (offset > 0) {
- addr += cs_etm__t32_instr_size(etmq, addr);
+ addr += cs_etm__t32_instr_size(etmq,
+ trace_chan_id, addr);
offset--;
}
return addr;
@@ -1063,6 +1069,7 @@ static int cs_etm__sample(struct cs_etm_queue *etmq,
struct cs_etm_auxtrace *etm = etmq->etm;
struct cs_etm_packet *tmp;
int ret;
+ u8 trace_chan_id = tidq->trace_chan_id;
u64 instrs_executed = tidq->packet->instr_count;
tidq->period_instructions += instrs_executed;
@@ -1093,7 +1100,8 @@ static int cs_etm__sample(struct cs_etm_queue *etmq,
* executed, but PC has not advanced to next instruction)
*/
u64 offset = (instrs_executed - instrs_over - 1);
- u64 addr = cs_etm__instr_addr(etmq, tidq->packet, offset);
+ u64 addr = cs_etm__instr_addr(etmq, trace_chan_id,
+ tidq->packet, offset);
ret = cs_etm__synth_instruction_sample(
etmq, tidq, addr, etm->instructions_sample_period);
@@ -1268,7 +1276,7 @@ static int cs_etm__get_data_block(struct cs_etm_queue *etmq)
return etmq->buf_len;
}
-static bool cs_etm__is_svc_instr(struct cs_etm_queue *etmq,
+static bool cs_etm__is_svc_instr(struct cs_etm_queue *etmq, u8 trace_chan_id,
struct cs_etm_packet *packet,
u64 end_addr)
{
@@ -1291,7 +1299,8 @@ static bool cs_etm__is_svc_instr(struct cs_etm_queue *etmq,
* so below only read 2 bytes as instruction size for T32.
*/
addr = end_addr - 2;
- cs_etm__mem_access(etmq, addr, sizeof(instr16), (u8 *)&instr16);
+ cs_etm__mem_access(etmq, trace_chan_id, addr,
+ sizeof(instr16), (u8 *)&instr16);
if ((instr16 & 0xFF00) == 0xDF00)
return true;
@@ -1306,7 +1315,8 @@ static bool cs_etm__is_svc_instr(struct cs_etm_queue *etmq,
* +---------+---------+-------------------------+
*/
addr = end_addr - 4;
- cs_etm__mem_access(etmq, addr, sizeof(instr32), (u8 *)&instr32);
+ cs_etm__mem_access(etmq, trace_chan_id, addr,
+ sizeof(instr32), (u8 *)&instr32);
if ((instr32 & 0x0F000000) == 0x0F000000 &&
(instr32 & 0xF0000000) != 0xF0000000)
return true;
@@ -1322,7 +1332,8 @@ static bool cs_etm__is_svc_instr(struct cs_etm_queue *etmq,
* +-----------------------+---------+-----------+
*/
addr = end_addr - 4;
- cs_etm__mem_access(etmq, addr, sizeof(instr32), (u8 *)&instr32);
+ cs_etm__mem_access(etmq, trace_chan_id, addr,
+ sizeof(instr32), (u8 *)&instr32);
if ((instr32 & 0xFFE0001F) == 0xd4000001)
return true;
@@ -1338,6 +1349,7 @@ static bool cs_etm__is_svc_instr(struct cs_etm_queue *etmq,
static bool cs_etm__is_syscall(struct cs_etm_queue *etmq,
struct cs_etm_traceid_queue *tidq, u64 magic)
{
+ u8 trace_chan_id = tidq->trace_chan_id;
struct cs_etm_packet *packet = tidq->packet;
struct cs_etm_packet *prev_packet = tidq->prev_packet;
@@ -1352,7 +1364,7 @@ static bool cs_etm__is_syscall(struct cs_etm_queue *etmq,
*/
if (magic == __perf_cs_etmv4_magic) {
if (packet->exception_number == CS_ETMV4_EXC_CALL &&
- cs_etm__is_svc_instr(etmq, prev_packet,
+ cs_etm__is_svc_instr(etmq, trace_chan_id, prev_packet,
prev_packet->end_addr))
return true;
}
@@ -1390,6 +1402,7 @@ static bool cs_etm__is_sync_exception(struct cs_etm_queue *etmq,
struct cs_etm_traceid_queue *tidq,
u64 magic)
{
+ u8 trace_chan_id = tidq->trace_chan_id;
struct cs_etm_packet *packet = tidq->packet;
struct cs_etm_packet *prev_packet = tidq->prev_packet;
@@ -1415,7 +1428,7 @@ static bool cs_etm__is_sync_exception(struct cs_etm_queue *etmq,
* (SMC, HVC) are taken as sync exceptions.
*/
if (packet->exception_number == CS_ETMV4_EXC_CALL &&
- !cs_etm__is_svc_instr(etmq, prev_packet,
+ !cs_etm__is_svc_instr(etmq, trace_chan_id, prev_packet,
prev_packet->end_addr))
return true;
@@ -1439,6 +1452,7 @@ static int cs_etm__set_sample_flags(struct cs_etm_queue *etmq,
{
struct cs_etm_packet *packet = tidq->packet;
struct cs_etm_packet *prev_packet = tidq->prev_packet;
+ u8 trace_chan_id = tidq->trace_chan_id;
u64 magic;
int ret;
@@ -1519,7 +1533,8 @@ static int cs_etm__set_sample_flags(struct cs_etm_queue *etmq,
if (prev_packet->flags == (PERF_IP_FLAG_BRANCH |
PERF_IP_FLAG_RETURN |
PERF_IP_FLAG_INTERRUPT) &&
- cs_etm__is_svc_instr(etmq, packet, packet->start_addr))
+ cs_etm__is_svc_instr(etmq, trace_chan_id,
+ packet, packet->start_addr))
prev_packet->flags = PERF_IP_FLAG_BRANCH |
PERF_IP_FLAG_RETURN |
PERF_IP_FLAG_SYSCALLRET;
--
2.17.1
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next prev parent reply other threads:[~2019-05-24 17:37 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-24 17:34 [PATCH v2 00/17] perf tools: Coresight: Add CPU-wide trace support Mathieu Poirier
2019-05-24 17:34 ` [PATCH v2 01/17] perf tools: Configure contextID tracing in CPU-wide mode Mathieu Poirier
2019-06-07 9:21 ` Suzuki K Poulose
2019-06-07 17:40 ` Mathieu Poirier
2019-06-07 18:20 ` Arnaldo Carvalho de Melo
2019-06-07 19:33 ` Mathieu Poirier
2019-05-24 17:34 ` [PATCH v2 02/17] perf tools: Configure timestsamp generation " Mathieu Poirier
2019-06-07 9:41 ` Suzuki K Poulose
2019-06-07 17:46 ` Mathieu Poirier
2019-06-07 18:34 ` Arnaldo Carvalho de Melo
2019-05-24 17:34 ` [PATCH v2 03/17] perf tools: Configure SWITCH_EVENTS " Mathieu Poirier
2019-05-24 17:34 ` [PATCH v2 04/17] perf tools: Add handling of itrace start events Mathieu Poirier
2019-05-24 17:34 ` [PATCH v2 05/17] perf tools: Add handling of switch-CPU-wide events Mathieu Poirier
2019-05-24 17:34 ` [PATCH v2 06/17] perf tools: Refactor error path in cs_etm_decoder__new() Mathieu Poirier
2019-05-24 17:34 ` [PATCH v2 07/17] perf tools: Move packet queue out of decoder structure Mathieu Poirier
2019-05-24 17:34 ` [PATCH v2 08/17] perf tools: Fix indentation in function cs_etm__process_decoder_queue() Mathieu Poirier
2019-05-24 17:35 ` [PATCH v2 09/17] perf tools: Introduce the concept of trace ID queues Mathieu Poirier
2019-05-24 17:35 ` [PATCH v2 10/17] perf tools: Get rid of unused cpu in struct cs_etm_queue Mathieu Poirier
2019-05-24 17:35 ` [PATCH v2 11/17] perf tools: Move thread to traceid_queue Mathieu Poirier
2019-05-24 17:35 ` [PATCH v2 12/17] perf tools: Move tid/pid " Mathieu Poirier
2019-05-24 17:35 ` Mathieu Poirier [this message]
2019-05-24 17:35 ` [PATCH v2 14/17] perf tools: Add support for multiple traceID queues Mathieu Poirier
2019-05-24 17:35 ` [PATCH v2 15/17] perf tools: Linking PE contextID with perf thread mechanic Mathieu Poirier
2019-05-24 17:35 ` [PATCH v2 16/17] perf tools: Add notion of time to decoding code Mathieu Poirier
2019-06-06 18:50 ` Arnaldo Carvalho de Melo
2019-06-07 14:38 ` Mathieu Poirier
2019-05-24 17:35 ` [PATCH v2 17/17] perf tools: Add support for CPU-wide trace scenarios Mathieu Poirier
2019-05-31 1:45 ` [PATCH v2 00/17] perf tools: Coresight: Add CPU-wide trace support Leo Yan
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