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Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hcw25-0007RM-Ot; Mon, 17 Jun 2019 18:07:05 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hcw22-0007Qg-1r for linux-arm-kernel@lists.infradead.org; Mon, 17 Jun 2019 18:07:03 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E642B28; Mon, 17 Jun 2019 11:07:00 -0700 (PDT) Received: from localhost (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 66E013F246; Mon, 17 Jun 2019 11:07:00 -0700 (PDT) Date: Mon, 17 Jun 2019 19:06:58 +0100 From: Andrew Murray To: Suzuki K Poulose Subject: Re: [PATCH v9 4/5] KVM: arm/arm64: remove pmc->bitmask Message-ID: <20190617180658.GN20984@e119886-lin.cambridge.arm.com> References: <20190612190450.7085-1-andrew.murray@arm.com> <20190612190450.7085-5-andrew.murray@arm.com> <6a8e4fdd-d8cf-f3fb-55cd-2d06805b0eb9@arm.com> <20190613093957.GG49779@e119886-lin.cambridge.arm.com> <5e18d747-1d82-8eed-ef1c-de86c5b3a7e7@arm.com> <20190617154311.GM20984@e119886-lin.cambridge.arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1+81 (426a6c1) (2018-08-26) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190617_110702_139280_1DC8E2B4 X-CRM114-Status: GOOD ( 17.54 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: julien.thierry@arm.com, marc.zyngier@arm.com, christoffer.dall@arm.com, james.morse@arm.com, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Jun 17, 2019 at 05:33:40PM +0100, Suzuki K Poulose wrote: > > > On 17/06/2019 16:43, Andrew Murray wrote: > > On Thu, Jun 13, 2019 at 05:50:43PM +0100, Suzuki K Poulose wrote: > > > > > > > > > On 13/06/2019 10:39, Andrew Murray wrote: > > > > On Thu, Jun 13, 2019 at 08:30:51AM +0100, Julien Thierry wrote: > > > > > > > index ae1e886d4a1a..88ce24ae0b45 100644 > > > > > > --- a/virt/kvm/arm/pmu.c > > > > > > +++ b/virt/kvm/arm/pmu.c > > > > > > @@ -47,7 +47,10 @@ u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx) > > > > > > counter += perf_event_read_value(pmc->perf_event, &enabled, > > > > > > &running); > > > > > > - return counter & pmc->bitmask; > > > > > > + if (select_idx != ARMV8_PMU_CYCLE_IDX) > > > > > > + counter = lower_32_bits(counter); > > > > > > > > > > Shouldn't this depend on PMCR.LC as well? If PMCR.LC is clear we only > > > > > want the lower 32bits of the cycle counter. > > > > > > > > Yes that's correct. The hunk should look like this: > > > > > > > > - return counter & pmc->bitmask; > > > > + if (!(select_idx == ARMV8_PMU_CYCLE_IDX && > > > > + __vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_LC)) > > > > + counter = lower_32_bits(counter); > > > > + > > > > + return counter; > > > > > > May be you could add a macro : > > > > > > #define vcpu_pmu_counter_is_64bit(vcpu, idx) ? > > > > Yes I think a helper would be useful - though I'd prefer the name > > 'kvm_pmu_idx_is_long_cycle_counter'. This seems a little clearer as > > you could otherwise argue that a chained counter is also 64 bits. > > When you get to add 64bit PMU counter (v8.5), this would be handy. So > having it de-coupled from the cycle counter may be a good idea. Anyways, > I leave that to you. Yes that thought crossed my mind. I'll take your suggestion afterall. Thanks, Andrew Murray > > Cheers > Suzuki _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel