From: Icenowy Zheng <icenowy@aosc.io>
To: Rob Herring <robh+dt@kernel.org>,
Maxime Ripard <maxime.ripard@bootlin.com>,
Chen-Yu Tsai <wens@csie.org>,
Linus Walleij <linus.walleij@linaro.org>
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
Icenowy Zheng <icenowy@aosc.io>
Subject: [PATCH v3 8/9] dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board
Date: Sun, 23 Jun 2019 12:38:00 +0800 [thread overview]
Message-ID: <20190623043801.14040-9-icenowy@aosc.io> (raw)
In-Reply-To: <20190623043801.14040-1-icenowy@aosc.io>
The Lichee Zero Plus is a core board made by Sipeed, with a microUSB
connector on it, TF slot or WSON8 SD chip, optional eMMC or SPI Flash.
It has a gold finger connector for expansion, and UART is available from
reserved pins w/ 2.54mm pitch. The board can use either SoChip S3 or
Allwinner V3L SoCs.
Add the device tree binding of the basic version of the core board --
w/o eMMC or SPI Flash, w/ TF slot or WSON8 SD, and use S3 SoC.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
No changes in v3.
Patch introduced in v2.
Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml
index 000a00d12d6a..48c126a7a848 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.yaml
+++ b/Documentation/devicetree/bindings/arm/sunxi.yaml
@@ -353,6 +353,11 @@ properties:
- const: licheepi,licheepi-zero
- const: allwinner,sun8i-v3s
+ - description: Lichee Zero Plus (with S3, without eMMC/SPI Flash)
+ items:
+ - const: sipeed,lichee-zero-plus
+ - const: allwinner,sun8i-s3
+
- description: Linksprite PCDuino
items:
- const: linksprite,a10-pcduino
--
2.21.0
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next prev parent reply other threads:[~2019-06-23 4:42 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-23 4:37 [PATCH v3 0/9] Support for Allwinner V3/S3L and Sochip S3 Icenowy Zheng
2019-06-23 4:37 ` [PATCH v3 1/9] pinctrl: sunxi: v3s: introduce support for V3 Icenowy Zheng
2019-06-24 12:40 ` Maxime Ripard
2019-06-25 13:57 ` Linus Walleij
2019-06-25 14:10 ` Maxime Ripard
2019-06-23 4:37 ` [PATCH v3 2/9] clk: sunxi-ng: v3s: add the missing PLL_DDR1 Icenowy Zheng
2019-06-23 4:37 ` [PATCH v3 3/9] dt-bindings: clk: sunxi-ccu: add compatible string for V3 CCU Icenowy Zheng
2019-06-23 4:37 ` [PATCH v3 4/9] clk: sunxi-ng: v3s: add Allwinner V3 support Icenowy Zheng
2019-07-09 22:56 ` Rob Herring
2019-06-23 4:37 ` [PATCH v3 5/9] dt-bindings: vendor-prefixes: add SoChip Icenowy Zheng
2019-06-25 13:55 ` Linus Walleij
2019-06-25 17:39 ` Rob Herring
2019-06-23 4:37 ` [PATCH v3 6/9] ARM: sunxi: dts: s3/s3l/v3: add DTSI files for S3/S3L/V3 SoCs Icenowy Zheng
2019-06-23 4:37 ` [PATCH v3 7/9] dt-bindings: vendor-prefixes: add Sipeed Icenowy Zheng
2019-07-09 22:57 ` Rob Herring
2019-06-23 4:38 ` Icenowy Zheng [this message]
2019-06-24 12:42 ` [PATCH v3 8/9] dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board Maxime Ripard
2019-06-23 4:38 ` [PATCH v3 9/9] ARM: dts: sun8i: s3: add devicetree for Lichee zero plus w/ S3 Icenowy Zheng
2019-06-24 12:43 ` Maxime Ripard
2019-06-24 13:43 ` Icenowy Zheng
2019-06-24 13:48 ` Maxime Ripard
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