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[85.30.9.151]) by smtp.gmail.com with ESMTPSA id p9sm2284328lji.107.2019.06.25.06.05.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 25 Jun 2019 06:05:01 -0700 (PDT) Date: Tue, 25 Jun 2019 05:49:24 -0700 From: Olof Johansson To: Simon Horman Subject: Re: [GIT PULL] Renesas ARM Based SoC Updates for v5.3 Message-ID: <20190625124924.ubpi3pxwggbz5cbw@localhost> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: NeoMutt/20170113 (1.7.2) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190625_060507_298682_72CD83A0 X-CRM114-Status: GOOD ( 16.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Arnd Bergmann , Kevin Hilman , Magnus Damm , linux-renesas-soc@vger.kernel.org, arm@kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Jun 21, 2019 at 11:12:04AM +0200, Simon Horman wrote: > Hi Olof, Hi Kevin, Hi Arnd, > > Please consider these Renesas ARM based SoC updates for v5.3. > > > The following changes since commit a188339ca5a396acc588e5851ed7e19f66b0ebd9: > > Linux 5.2-rc1 (2019-05-19 15:47:09 -0700) > > are available in the git repository at: > > https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-arm-soc-for-v5.3 > > for you to fetch changes up to 02af9f90941b6cce5fb672ee058c142adcc11a2f: > > soc: renesas: Enable RZ/A1 IRQC on RZ/A1H and RZ/A2M (2019-06-06 10:37:06 +0200) > > ---------------------------------------------------------------- > Renesas ARM Based SoC Updates for v5.3 > > * Auto-enable RZ/A1 IRQC on RZ/A1H and RZ/A2M > * Don't init CNTVOFF/counter if PSCI is available > > ---------------------------------------------------------------- > Geert Uytterhoeven (1): > soc: renesas: Enable RZ/A1 IRQC on RZ/A1H and RZ/A2M > > Oleksandr Tyshchenko (1): > ARM: mach-shmobile: Don't init CNTVOFF/counter if PSCI is available Merged, thanks. Note that in this patch, code like this: +#ifdef CONFIG_ARM_PSCI_FW + if (psci_ops.cpu_on) + need_update = false; +#endif + + if (need_update == false) + goto skip_update; Can either be replaced with a goto under the ifdef, or at the very least, no need to do a 'need_update == false' -- 'if (need_update)' is sufficient. -Olof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel