From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_MUTT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38063C48BD7 for ; Thu, 27 Jun 2019 14:58:16 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 060242086D for ; Thu, 27 Jun 2019 14:58:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="o6r9XW9k" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 060242086D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=I441owNut45/o59YPqYDEIOiz8AheSgcQkBozZwz+mM=; b=o6r9XW9kbqnb6p JQocLac7y12HRhIdDpalBZAka1b7v2kVAoaooP2msyhz7S7/cxHKTZSEL6pzyd4ee4H838lRJ49L3 LvS6Q75bTkCTUlNP8LItC7a8RIJczqP5A6lhVK2E+nDPumAG5H/FAh7EaXJbXoiuewbAjfrWoWsOr Y3OkEz0HLTYieTES60Qqm77Vs4h5uDwdmVqyM4qJpffqx4CnWHJbB9qZhzfCkLEwywAn5AbYM9Hl+ jGSEExlQlxqOjZyF7ckne1KBxZRFtKSXVTOrdqQdfRmrisqOzwMH8AslGGHS2eQE3Oz1b8gALNZBg Pd7U9oIc9rWxd4xofDjA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hgVqj-0008OB-Ss; Thu, 27 Jun 2019 14:58:10 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hgVqf-0008N4-Rr for linux-arm-kernel@lists.infradead.org; Thu, 27 Jun 2019 14:58:07 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4B367360; Thu, 27 Jun 2019 07:58:05 -0700 (PDT) Received: from e121166-lin.cambridge.arm.com (unknown [10.1.196.255]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B6A5D3F246; Thu, 27 Jun 2019 07:58:02 -0700 (PDT) Date: Thu, 27 Jun 2019 15:58:00 +0100 From: Lorenzo Pieralisi To: Vidya Sagar Subject: Re: [PATCH V11 03/12] PCI: dwc: Perform dbi regs write lock towards the end Message-ID: <20190627145800.GD3782@e121166-lin.cambridge.arm.com> References: <20190624091505.1711-1-vidyas@nvidia.com> <20190624091505.1711-4-vidyas@nvidia.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20190624091505.1711-4-vidyas@nvidia.com> User-Agent: Mutt/1.9.4 (2018-02-28) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190627_075805_991033_402D4C6A X-CRM114-Status: GOOD ( 16.80 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, mperttunen@nvidia.com, mmaddireddy@nvidia.com, linux-pci@vger.kernel.org, catalin.marinas@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, kthota@nvidia.com, kishon@ti.com, linux-tegra@vger.kernel.org, robh+dt@kernel.org, thierry.reding@gmail.com, gustavo.pimentel@synopsys.com, jingoohan1@gmail.com, bhelgaas@google.com, digetx@gmail.com, jonathanh@nvidia.com, linux-arm-kernel@lists.infradead.org, sagar.tv@gmail.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Jun 24, 2019 at 02:44:56PM +0530, Vidya Sagar wrote: > Remove multiple write enable and disable sequences of dbi registers as > Tegra194 implements writes to BAR-0 register (offset: 0x10) controlled by > DBI write-lock enable bit thereby not allowing any further writes to BAR-0 > register in config space to take place. Hence enabling write permission at > the start of function and disabling the same only towards the end. I do not understand what this patch does, I would like to rephrase the commit log in a way that is easier to parse. In particular I do not get what you mean in relation to BAR-0, I am confused, please clarify. Lorenzo > Signed-off-by: Vidya Sagar > Reviewed-by: Thierry Reding > Acked-by: Jingoo Han > --- > Changes since [v10]: > * None > > Changes since [v9]: > * None > > Changes since [v8]: > * None > > Changes since [v7]: > * None > > Changes since [v6]: > * None > > Changes since [v5]: > * Moved write enable to the beginning of the API and write disable to the end > > Changes since [v4]: > * None > > Changes since [v3]: > * None > > Changes since [v2]: > * None > > Changes since [v1]: > * None > > drivers/pci/controller/dwc/pcie-designware-host.c | 14 ++++++++------ > 1 file changed, 8 insertions(+), 6 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c > index f93252d0da5b..d3156446ff27 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > @@ -628,6 +628,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp) > u32 val, ctrl, num_ctrls; > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > > + /* > + * Enable DBI read-only registers for writing/updating configuration. > + * Write permission gets disabled towards the end of this function. > + */ > + dw_pcie_dbi_ro_wr_en(pci); > + > dw_pcie_setup(pci); > > if (!pp->ops->msi_host_init) { > @@ -650,12 +656,10 @@ void dw_pcie_setup_rc(struct pcie_port *pp) > dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000); > > /* Setup interrupt pins */ > - dw_pcie_dbi_ro_wr_en(pci); > val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE); > val &= 0xffff00ff; > val |= 0x00000100; > dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val); > - dw_pcie_dbi_ro_wr_dis(pci); > > /* Setup bus numbers */ > val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS); > @@ -687,15 +691,13 @@ void dw_pcie_setup_rc(struct pcie_port *pp) > > dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); > > - /* Enable write permission for the DBI read-only register */ > - dw_pcie_dbi_ro_wr_en(pci); > /* Program correct class for RC */ > dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); > - /* Better disable write permission right after the update */ > - dw_pcie_dbi_ro_wr_dis(pci); > > dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val); > val |= PORT_LOGIC_SPEED_CHANGE; > dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); > + > + dw_pcie_dbi_ro_wr_dis(pci); > } > EXPORT_SYMBOL_GPL(dw_pcie_setup_rc); > -- > 2.17.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel