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[98.248.47.108]) by smtp.gmail.com with ESMTPSA id n89sm13742921pjc.0.2019.06.28.01.10.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 28 Jun 2019 01:10:19 -0700 (PDT) Date: Fri, 28 Jun 2019 01:10:07 -0700 From: Nicolin Chen To: Will Deacon Subject: Re: Why doesn't arm-smmu (v2) driver take VA_BITS into consideration? Message-ID: <20190628081006.GA6628@Asurada> References: <20190627001932.GA27343@Asurada-Nvidia.nvidia.com> <20190627102640.2pzgiro3gq3ont5s@willie-the-truck> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20190627102640.2pzgiro3gq3ont5s@willie-the-truck> User-Agent: Mutt/1.5.22 (2013-10-16) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190628_011022_472447_E47C750F X-CRM114-Status: GOOD ( 18.20 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: will.deacon@arm.com, robin.murphy@arm.com, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Will, On Thu, Jun 27, 2019 at 11:26:40AM +0100, Will Deacon wrote: > On Wed, Jun 26, 2019 at 05:19:33PM -0700, Nicolin Chen wrote: > > I am using an Soc that contains arm-smmu v2 engines. I found that > > the arm-smmu driver reads GR_ID2 register and defines ias and oas > > of each domain based on the corresponding fields of that GR_ID2. > > > > Using my platform for example, it gets 48-bit for all ias and oas, > > being translated from those fields so I got these 2 stages: > > Stage-1: 48-bit VA -> 48-bit IPA > > Stage-2: 48-bit IPA -> 48-bit PA > > > > Then the code does below to configure aperture_end to 48-bit: > > 914 domain->geometry.aperture_end = (1UL << ias) - 1; > > > > However, my system configures VA_BITS to 39. So aperture_end==48 > > is a mismatch comparing to VA_BITS_39. Although the aperture_end > > is supposed to cap IOVA allocation, this 48-bit cap won't really > > do the job at all. > > What actually goes wrong, though? IOVAs should only be handed over to > devices, so VA_BITS doesn't strictly matter. It's the DMA masks that are > important. Ah..that's true. I think I misunderstood one of my situations here. > > I saw that arm-smmu-v3 driver takes VA_BITS into consideration: > > 1765 switch (smmu_domain->stage) { > > 1766 case ARM_SMMU_DOMAIN_S1: > > 1767 ias = (smmu->features & ARM_SMMU_FEAT_VAX) ? > > 1768 ias = min_t(unsigned long, ias, VA_BITS); > > > > So I am wondering if it is intentionally designed so by ignoring > > VA_BITS? Would you please help me understand this a bit? > > I think it's simply that SMMUv3 doesn't provide an ID field to tell you > what to use, so we chose to go with VA_BITS since it's what we're using > on the CPU. I see. Thanks for explaining! Nicolin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel