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[79.131.225.144]) by smtp.gmail.com with ESMTPSA id s11sm2387689wrr.59.2019.07.04.05.49.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 04 Jul 2019 05:49:44 -0700 (PDT) Date: Thu, 4 Jul 2019 15:49:41 +0300 From: Ilias Apalodimas To: Arnd Bergmann Subject: Re: [PATCH net-next 3/3] net: stmmac: Introducing support for Page Pool Message-ID: <20190704124941.GA9617@apalos> References: <1b254bb7fc6044c5e6e2fdd9e00088d1d13a808b.1562149883.git.joabreu@synopsys.com> <20190704120018.4523a119@carbon> <20190704103057.GA29734@apalos> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190704_054946_446105_B9836CFE X-CRM114-Status: GOOD ( 17.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jose Abreu , Joao Pinto , Alexandre Torgue , Maxime Ripard , Networking , Linux Kernel Mailing List , linux-stm32@st-md-mailman.stormreply.com, Chen-Yu Tsai , Maxime Coquelin , Jesper Dangaard Brouer , Giuseppe Cavallaro , "David S . Miller" , Linux ARM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Jul 04, 2019 at 02:14:28PM +0200, Arnd Bergmann wrote: > On Thu, Jul 4, 2019 at 12:31 PM Ilias Apalodimas > wrote: > > > On Wed, 3 Jul 2019 12:37:50 +0200 > > > Jose Abreu wrote: > > > 1. page pool allocs packet. The API doesn't sync but i *think* you don't have to > > explicitly since the CPU won't touch that buffer until the NAPI handler kicks > > in. On the napi handler you need to dma_sync_single_for_cpu() and process the > > packet. > > > So bvottom line i *think* we can skip the dma_sync_single_for_device() on the > > initial allocation *only*. If am terribly wrong please let me know :) > > I think you have to do a sync_single_for_device /somewhere/ before the > buffer is given to the device. On a non-cache-coherent machine with > a write-back cache, there may be dirty cache lines that get written back > after the device DMA's data into it (e.g. from a previous memset > from before the buffer got freed), so you absolutely need to flush any > dirty cache lines on it first. Ok my bad here i forgot to add "when coherency is there", since the driver i had in mind runs on such a device (i think this is configurable though so i'll add the sync explicitly to make sure we won't break any configurations). In general you are right, thanks for the explanation! > You may also need to invalidate the cache lines in the following > sync_single_for_cpu() to eliminate clean cache lines with stale data > that got there when speculatively reading between the cache-invalidate > and the DMA. > > Arnd Thanks! /Ilias _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel