From: Andrew Jeffery <andrew@aj.id.au>
To: linux-aspeed@lists.ozlabs.org
Cc: mark.rutland@arm.com, Andrew Jeffery <andrew@aj.id.au>,
ryanchen.aspeed@gmail.com, linux-kernel@vger.kernel.org,
robh+dt@kernel.org, joel@jms.id.au,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/3] ARM: dts: aspeed: Describe SD controller in DTSIs
Date: Wed, 10 Jul 2019 23:45:01 +0930 [thread overview]
Message-ID: <20190710141503.21026-2-andrew@aj.id.au> (raw)
In-Reply-To: <20190710141503.21026-1-andrew@aj.id.au>
The AST2400 and AST2500 both share the same SD controller, at the same
location in the physical address space and the same hardware interrupt,
with the same clock configurations.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
arch/arm/boot/dts/aspeed-g4.dtsi | 30 ++++++++++++++++++++++++++++++
arch/arm/boot/dts/aspeed-g5.dtsi | 30 ++++++++++++++++++++++++++++++
2 files changed, 60 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 5d7050d00874..4bfda5d91dbe 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -188,6 +188,36 @@
reg = <0x1e720000 0x8000>; // 32K
};
+ sdc: sdc@1e740000 {
+ compatible = "aspeed,ast2400-sdc";
+ reg = <0x1e740000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;
+ status = "disabled";
+
+ sdhci0: sdhci@1e740100 {
+ compatible = "aspeed,ast2400-sdhci", "sdhci";
+ reg = <0x1e740100 0x100>;
+ aspeed,sdhci-slot = <0>;
+ interrupts = <26>;
+ sdhci,auto-cmd12;
+ clocks = <&syscon ASPEED_CLK_SDIO>;
+ status = "disabled";
+ };
+
+ sdhci1: sdhci@1e740200 {
+ compatible = "aspeed,ast2400-sdhci", "sdhci";
+ reg = <0x1e740200 0x100>;
+ aspeed,sdhci-slot = <1>;
+ interrupts = <26>;
+ sdhci,auto-cmd12;
+ clocks = <&syscon ASPEED_CLK_SDIO>;
+ status = "disabled";
+ };
+ };
+
gpio: gpio@1e780000 {
#gpio-cells = <2>;
gpio-controller;
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 4345c3153ca7..8d6404311652 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -262,6 +262,36 @@
reg = <0x1e720000 0x9000>; // 36K
};
+ sdc: sdc@1e740000 {
+ compatible = "aspeed,ast2500-sdc";
+ reg = <0x1e740000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;
+ status = "disabled";
+
+ sdhci0: sdhci@1e740100 {
+ compatible = "aspeed,ast2500-sdhci", "sdhci";
+ reg = <0x1e740100 0x100>;
+ slot = <0>;
+ interrupts = <26>;
+ sdhci,auto-cmd12;
+ clocks = <&syscon ASPEED_CLK_SDIO>;
+ status = "disabled";
+ };
+
+ sdhci1: sdhci@1e740200 {
+ compatible = "aspeed,ast2500-sdhci", "sdhci";
+ reg = <0x1e740200 0x100>;
+ slot = <1>;
+ interrupts = <26>;
+ sdhci,auto-cmd12;
+ clocks = <&syscon ASPEED_CLK_SDIO>;
+ status = "disabled";
+ };
+ };
+
gpio: gpio@1e780000 {
#gpio-cells = <2>;
gpio-controller;
--
2.20.1
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next prev parent reply other threads:[~2019-07-10 14:15 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-10 14:15 [PATCH 0/3] ARM: dts: aspeed: Enable SD controllers Andrew Jeffery
2019-07-10 14:15 ` Andrew Jeffery [this message]
2019-07-10 14:15 ` [PATCH 2/3] ARM: dts: aspeed: Enable both MMC slots on AST2500 EVB Andrew Jeffery
2019-07-10 14:15 ` [PATCH 3/3] ARM: dts: aspeed: Enable both MMC slots on Swift Andrew Jeffery
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