Linux-ARM-Kernel Archive on lore.kernel.org
 help / color / Atom feed
From: Lukasz Luba <l.luba@partner.samsung.com>
To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org
Cc: mark.rutland@arm.com, cw00.choi@samsung.com,
	b.zolnierkie@samsung.com, sboyd@kernel.org,
	mturquette@baylibre.com, krzk@kernel.org,
	Lukasz Luba <l.luba@partner.samsung.com>,
	a.hajda@samsung.com, robh+dt@kernel.org,
	kyungmin.park@samsung.com, kgene@kernel.org,
	myungjoo.ham@samsung.com, s.nawrocki@samsung.com,
	m.szyprowski@samsung.com
Subject: [PATCH v1 00/50] Exynos5x clocks and buses changes
Date: Mon, 15 Jul 2019 14:43:27 +0200
Message-ID: <20190715124417.4787-1-l.luba@partner.samsung.com> (raw)
In-Reply-To: <CGME20190715124433eucas1p2a292f236ea55751117836742c1ca5d23@eucas1p2.samsung.com>

Hi all,

The patch set fixes clock settings for the Exynos5420/5422/5800 SoCs which
can be found in Odroid XU3/4, Google Peach Pi. Support for DT board files
with Exynos5420 (like Google Peach Pit) are under development.  The old
implementation did not configure properly the clock rates or the
connections which could cause performance issues or instability.  The
Exynos5x SoC has complex clocks topology. Some of the NoC clock branches
provide clock to the device internal buses or AXI interface and had wrong
settings.

In the old configuration the OPP values where not reflecting the actually
set frequencies, which were possible by setting the divider value on the
clock tree. The algorithms in governors, which use these frequencies,
relied on wrong assumption during their calculations. It also applies to
device drivers code, which does not check the rate of the clock but relay
on OPP values, which in some cases are different.  It is not only the bus
frequency but also the connected component internal buses (accelerators
like e.g. G2D, scaler, rotator) frequency.  Wrong frequency set due to
impossible division from PLL rate caused that some devices had lower than
possible clock for internal logic and for the AXI bus which transfers the
data.  For example fixes for MMC controller, where OPP max frequency
changed from 150MHz to 240MHz, changing the PLL rate to proper value caused
performance increase up to 20% (FSYS2 OPP table).

Affected components inside SoC: image rotator, usb3.0 and 2.0 controller,
jpeg accelerator, image/video scaler, mmc controller, ISP, display
controller, all NoC buses.

Some of the clocks have name which might indicate their max speed, e.g.
CLK_DOUT_ACLK266 but it is not true.  The max speed clock from this example
is 300MHz (according to the RM) and has been reflected accordingly in this
patch set.

Main changes:
- defined new clocks or added IDs to take them from DT nodes
- set proper PLLs frequency for: MPLL, DPLL, which would handle children
  clock requirements down in the tree,
- changed parents of some clocks to proper PLL or to proper parent clock,
- properly calculated OPP values for the buses keeping in mind the parent
  clock frequency and possible values derived from there by one clock
divider with proper bit length indicating maximum allowed divider; thanks
to that it is possible to set the requested frequency in all children
without changing the PLL frequency, which also makes the governor frequency
values assumption true,
- some OPPs were removed because it was not possible to set them due to
  different base frequency, which would require of changing PLL rate, which
might affect other devices connected to this PLL and their misscalculated
rates.

The last two patches touches Exynos5800 and are optional. They have been
checked due to some issues with disabling parent, which accidently was
populated up to MPLL and shut down the PLL. They might be used for testing
on Peach Pi.

The patch set is based on Samsung clock repo and branch 'for-v5.3/next'
[1].

Regards,
Lukasz Luba

[1] https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk.git/log/?h=for-v5.3/next

Lukasz Luba (50):
  clk: samsung: add new IDs for Exynos5420 clocks
  clk: samsung: add IDs for Exynos5420 NoC clocks
  clk: samsung: change parent of dout_aclk400_wcore in Exynos5420
  clk: samsung: add IDs to manage aclk400_mscl in Exynos5420
  clk: samsung: add IDs to aclk400_isp in Exynos5420
  clk: samsung: add IDs to ACLK266 clocks in Exynos5420
  clk: samsung: add IDs to ACLK266_G2D clocks in Exynos5420
  clk: samsung: change aclk266_isp clocks definitions Exynos5420
  clk: samsung: add IDs to FSYS clocks in Exynos5x
  clk: samsung: change ACLK100_NOC clocks definitions Exynos5x
  clk: samsung: add IDs to UART clocks in Exynos5420
  clk: add ID to PWM MUX in Exynos5420
  clk: samsung: add DPLL rate table in Exynos5420
  clk: samsung: add CLK_MOUT_SCLK_CPLL in the Exynos5420
  clk: samsung: add MPLL rate table in Exynos5420
  clk: samsung: add SPLL rate table in Exynos5420
  clk: samsung: add CLK_MOUT_MMC0 in the Exynos5420
  ARM: dts: exynos: add bus_isp with OPP table
  ARM: dts: exynos: change OPPs values for FSYS2 in Exynos5420
  ARM: dts: exynos: change and rename FSYS OPP table in Exynos5420
  ARM: dts: exynos: add OPP into FSYS APB bus in Exynos5420
  ARM: dts: exynos: OPPs for bus_disp1 in Exynos5420
  ARM: dts: exynos: change lowest OPP in bus_disp1_fimd in Exynos5420
  ARM: dts: exynos: align OPPs with PLL rate for MSCL in Exynos5420
  ARM: dts: exynos: add 300MHz to bus_disp1_fimd in Exynos5420
  ARM: dts: exynos: align NOC100 bus OPPs in Exynos5420
  ARM: dts: exynos: align bus_wcore OPPs in Exynos5420
  ARM: dts: exynos: change OPPs for g2d and g2d_acp buses in Exynos5420
  ARM: dts: exynos: align OPPs of bus_gen in Exynos5420
  ARM: dts: exynos: add bus_isp266 into Exynos5800
  ARM: dts: exynos: align lowest OPP in bus_jpeg in Exynos5420
  ARM: dts: exynos: remove lowest OPP from bus_mfc in Exynos5420
  ARM: dts: exynos: set parent clocks to UARTs in Exynos5420
  ARM: dts: exynos: set parent clocks to PWM in Exynos5420
  ARM: dts: exynos: change speed and parent of NoC clock in Exynos5420
  ARM: dts: exynos: change ACLK100_NOC config in Exynos5422
  ARM: dts: exynos: change parent and rate of bus_fsys in Exynos5422
  ARM: dts: exynos: change parent and rate of bus_fsys2 in Exynos5422
  ARM: dts: exynos: change parent and rate of bus_fsys_acp in Exynos5422
  ARM: dts: exynos: change parent and rate of bus_gen in Exynos5422
  ARM: dts: exynos: change parent and rate of bus_g2d in Exynos5422
  ARM: dts: exynos: change parent and rate of bus_mscl in Exynos5422
  ARM: dts: exynos: add bus_isp in Exynos5422
  ARM: dts: exynos: change rate of bus_jpeg in Exynos5422
  ARM: dts: exynos: change rate of bus_disp1_fimd in Exynos5422
  ARM: dts: exynos: change rates of bus_disp1 in Exynos5422
  ARM: dts: exynos: change rate of bus_gscl_scaler in Exynos5422
  ARM: dts: exynos: set proper parents to bus_isp266 Exynos5422
  ARM: dts: exynos: add buses support for Exynos5800 Peach Pi
  ARM: dts: exynos: change MMC0 clock parent in Exynos5800 Peach Pi

 arch/arm/boot/dts/exynos5420.dtsi             | 116 +++++++-----
 arch/arm/boot/dts/exynos5422-odroid-core.dtsi |  74 ++++++++
 arch/arm/boot/dts/exynos5800-peach-pi.dts     | 175 ++++++++++++++++++
 arch/arm/boot/dts/exynos5800.dtsi             |  10 +
 drivers/clk/samsung/clk-exynos5420.c          | 109 +++++++----
 include/dt-bindings/clock/exynos5420.h        |  27 ++-
 6 files changed, 429 insertions(+), 82 deletions(-)

-- 
2.17.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

       reply index

Thread overview: 90+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <CGME20190715124433eucas1p2a292f236ea55751117836742c1ca5d23@eucas1p2.samsung.com>
2019-07-15 12:43 ` Lukasz Luba [this message]
     [not found]   ` <CGME20190715124434eucas1p273e2efaad8bc3904c6f76cc1671aeb6c@eucas1p2.samsung.com>
2019-07-15 12:43     ` [PATCH v1 01/50] clk: samsung: add new IDs for Exynos5420 clocks Lukasz Luba
2019-07-16  9:49       ` Chanwoo Choi
2019-07-18  6:02         ` Lukasz Luba
     [not found]   ` <CGME20190715124435eucas1p2099cd7670a3d85d9b11eb0ff86041a2a@eucas1p2.samsung.com>
2019-07-15 12:43     ` [PATCH v1 02/50] clk: samsung: add IDs for Exynos5420 NoC clocks Lukasz Luba
2019-07-16  9:26       ` Chanwoo Choi
2019-07-18  5:26         ` Lukasz Luba
     [not found]   ` <CGME20190715124436eucas1p28a581bc25f6dae52a5b9b1af26d26368@eucas1p2.samsung.com>
2019-07-15 12:43     ` [PATCH v1 03/50] clk: samsung: change parent of dout_aclk400_wcore in Exynos5420 Lukasz Luba
2019-07-16  9:13       ` Chanwoo Choi
2019-07-18  5:19         ` Lukasz Luba
     [not found]   ` <CGME20190715124437eucas1p1827d7b5d7196f060799e5df6c27d29ad@eucas1p1.samsung.com>
2019-07-15 12:43     ` [PATCH v1 04/50] clk: samsung: add IDs to manage aclk400_mscl " Lukasz Luba
2019-07-16  9:17       ` Chanwoo Choi
2019-07-18  5:21         ` Lukasz Luba
     [not found]   ` <CGME20190715124437eucas1p2d817f0c1fcf4b523c7910218a6e557d9@eucas1p2.samsung.com>
2019-07-15 12:43     ` [PATCH v1 05/50] clk: samsung: add IDs to aclk400_isp " Lukasz Luba
     [not found]   ` <CGME20190715124438eucas1p2ee9d27c451eb7125bd3ec874baf76e14@eucas1p2.samsung.com>
2019-07-15 12:43     ` [PATCH v1 06/50] clk: samsung: add IDs to ACLK266 clocks " Lukasz Luba
     [not found]   ` <CGME20190715124439eucas1p18c4f512d2647717d77666d94dca867a6@eucas1p1.samsung.com>
2019-07-15 12:43     ` [PATCH v1 07/50] clk: samsung: add IDs to ACLK266_G2D " Lukasz Luba
     [not found]   ` <CGME20190715124440eucas1p10bb25e412f32f0da95761f96831893e6@eucas1p1.samsung.com>
2019-07-15 12:43     ` [PATCH v1 08/50] clk: samsung: change aclk266_isp clocks definitions Exynos5420 Lukasz Luba
2019-07-16 10:22       ` Chanwoo Choi
2019-07-18  6:05         ` Lukasz Luba
     [not found]   ` <CGME20190715124441eucas1p12e1f58587318219a5a2c695faa200b17@eucas1p1.samsung.com>
2019-07-15 12:43     ` [PATCH v1 09/50] clk: samsung: add IDs to FSYS clocks in Exynos5x Lukasz Luba
     [not found]   ` <CGME20190715124441eucas1p29f1205c20e9bea5b33f8f0b5747b1102@eucas1p2.samsung.com>
2019-07-15 12:43     ` [PATCH v1 10/50] clk: samsung: change ACLK100_NOC clocks definitions Exynos5x Lukasz Luba
2019-07-16 10:01       ` Chanwoo Choi
     [not found]   ` <CGME20190715124442eucas1p197b23d50f6986477467d23f53b84d187@eucas1p1.samsung.com>
2019-07-15 12:43     ` [PATCH v1 11/50] clk: samsung: add IDs to UART clocks in Exynos5420 Lukasz Luba
     [not found]   ` <CGME20190715124443eucas1p1adf02a02bf77448f2277ddd5fe5e895b@eucas1p1.samsung.com>
2019-07-15 12:43     ` [PATCH v1 12/50] clk: add ID to PWM MUX " Lukasz Luba
     [not found]   ` <CGME20190715124444eucas1p2683c9896e8be45d6a0cd4afeb681a2ea@eucas1p2.samsung.com>
2019-07-15 12:43     ` [PATCH v1 13/50] clk: samsung: add DPLL rate table " Lukasz Luba
2019-07-16  9:31       ` Chanwoo Choi
2019-07-18  6:01         ` Lukasz Luba
     [not found]   ` <CGME20190715124445eucas1p1a73385fcbe6205d868ae63b1198ff572@eucas1p1.samsung.com>
2019-07-15 12:43     ` [PATCH v1 14/50] clk: samsung: add CLK_MOUT_SCLK_CPLL in the Exynos5420 Lukasz Luba
     [not found]   ` <CGME20190715124446eucas1p1de55fe42ed5555c7a09b10f8c3ec3c3e@eucas1p1.samsung.com>
2019-07-15 12:43     ` [PATCH v1 15/50] clk: samsung: add MPLL rate table in Exynos5420 Lukasz Luba
     [not found]   ` <CGME20190715124446eucas1p1b9b7ec3235fdd887bf5a253a4e223df0@eucas1p1.samsung.com>
2019-07-15 12:43     ` [PATCH v1 16/50] clk: samsung: add SPLL " Lukasz Luba
     [not found]   ` <CGME20190715124447eucas1p143a857f619f48b9b87437ec3b13dfb3f@eucas1p1.samsung.com>
2019-07-15 12:43     ` [PATCH v1 17/50] clk: samsung: add CLK_MOUT_MMC0 in the Exynos5420 Lukasz Luba
     [not found]   ` <CGME20190715124448eucas1p1b3a8d16d6f5e9fd4ed49c3b7fa66e18e@eucas1p1.samsung.com>
2019-07-15 12:43     ` [PATCH v1 18/50] ARM: dts: exynos: add bus_isp with OPP table Lukasz Luba
     [not found]   ` <CGME20190715124449eucas1p130d853368cb8bf02bef337da2d513fff@eucas1p1.samsung.com>
2019-07-15 12:43     ` [PATCH v1 19/50] ARM: dts: exynos: change OPPs values for FSYS2 in Exynos5420 Lukasz Luba
     [not found]   ` <CGME20190715124450eucas1p189043d196375aa6adacf898de81bfa9b@eucas1p1.samsung.com>
2019-07-15 12:43     ` [PATCH v1 20/50] ARM: dts: exynos: change and rename FSYS OPP table " Lukasz Luba
2019-07-17  8:39       ` Krzysztof Kozlowski
2019-07-17 10:04         ` Lukasz Luba
     [not found]   ` <CGME20190715124451eucas1p2904b49f59cca0cbbc22381f168affbb5@eucas1p2.samsung.com>
2019-07-15 12:43     ` [PATCH v1 21/50] ARM: dts: exynos: add OPP into FSYS APB bus " Lukasz Luba
2019-07-17  8:48       ` Krzysztof Kozlowski
2019-07-22 10:47         ` Lukasz Luba
     [not found]   ` <CGME20190715124451eucas1p28ac87fa7bd7e602ffab69a6915f37536@eucas1p2.samsung.com>
2019-07-15 12:43     ` [PATCH v1 22/50] ARM: dts: exynos: OPPs for bus_disp1 " Lukasz Luba
     [not found]   ` <CGME20190715124452eucas1p294d89255359b2036b19213427f558dbf@eucas1p2.samsung.com>
2019-07-15 12:43     ` [PATCH v1 23/50] ARM: dts: exynos: change lowest OPP in bus_disp1_fimd " Lukasz Luba
2019-07-17  9:08       ` Krzysztof Kozlowski
     [not found]   ` <CGME20190715124453eucas1p1dbdfab862499d9a7bd8a853e30944bac@eucas1p1.samsung.com>
2019-07-15 12:43     ` [PATCH v1 24/50] ARM: dts: exynos: align OPPs with PLL rate for MSCL " Lukasz Luba
     [not found]   ` <CGME20190715124454eucas1p1cd37552b222539b02629cb52e646ae29@eucas1p1.samsung.com>
2019-07-15 12:43     ` [PATCH v1 25/50] ARM: dts: exynos: add 300MHz to bus_disp1_fimd " Lukasz Luba
2019-07-17 10:04       ` Krzysztof Kozlowski
     [not found]   ` <CGME20190715124455eucas1p13bfc0c1d113225db9607e4c0dbac353c@eucas1p1.samsung.com>
2019-07-15 12:43     ` [PATCH v1 26/50] ARM: dts: exynos: align NOC100 bus OPPs " Lukasz Luba
2019-07-17 10:10       ` Krzysztof Kozlowski
2019-07-17 10:27         ` Lukasz Luba
2019-07-17 10:38           ` Krzysztof Kozlowski
2019-07-17 10:41             ` Lukasz Luba
     [not found]   ` <CGME20190715124456eucas1p2acf15d00e3fa7b77fe3a2b10ce1ab74f@eucas1p2.samsung.com>
2019-07-15 12:43     ` [PATCH v1 27/50] ARM: dts: exynos: align bus_wcore " Lukasz Luba
2019-07-17 10:15       ` Krzysztof Kozlowski
2019-07-17 10:29         ` Lukasz Luba
2019-07-17 16:58         ` Lukasz Luba
2019-07-23 12:08           ` Krzysztof Kozlowski
     [not found]   ` <CGME20190715124457eucas1p1b3033c2505581b350191eed7ba47bb40@eucas1p1.samsung.com>
2019-07-15 12:43     ` [PATCH v1 28/50] ARM: dts: exynos: change OPPs for g2d and g2d_acp buses " Lukasz Luba
     [not found]   ` <CGME20190715124457eucas1p20401b92a7c0eb51af1e0910fbebaa0b5@eucas1p2.samsung.com>
2019-07-15 12:43     ` [PATCH v1 29/50] ARM: dts: exynos: align OPPs of bus_gen " Lukasz Luba
     [not found]   ` <CGME20190715124458eucas1p2df56f2e0c7a1a0a9144a4d5fbdb471a9@eucas1p2.samsung.com>
2019-07-15 12:43     ` [PATCH v1 30/50] ARM: dts: exynos: add bus_isp266 into Exynos5800 Lukasz Luba
2019-07-17 10:33       ` Krzysztof Kozlowski
     [not found]   ` <CGME20190715124459eucas1p2a1d8795e57a82704ff221567a8810485@eucas1p2.samsung.com>
2019-07-15 12:43     ` [PATCH v1 31/50] ARM: dts: exynos: align lowest OPP in bus_jpeg in Exynos5420 Lukasz Luba
2019-07-17 10:30       ` Krzysztof Kozlowski
     [not found]   ` <CGME20190715124500eucas1p114c6cbbbb4efa421b2e24d49a6d3d603@eucas1p1.samsung.com>
2019-07-15 12:43     ` [PATCH v1 32/50] ARM: dts: exynos: remove lowest OPP from bus_mfc " Lukasz Luba
     [not found]   ` <CGME20190715124501eucas1p17382ca9cead8bfe1dc938e6fb583b7c5@eucas1p1.samsung.com>
2019-07-15 12:44     ` [PATCH v1 33/50] ARM: dts: exynos: set parent clocks to UARTs " Lukasz Luba
2019-07-17 10:35       ` Krzysztof Kozlowski
     [not found]   ` <CGME20190715124502eucas1p20a35f8c0f426878e50583fa3402de988@eucas1p2.samsung.com>
2019-07-15 12:44     ` [PATCH v1 34/50] ARM: dts: exynos: set parent clocks to PWM " Lukasz Luba
     [not found]   ` <CGME20190715124502eucas1p1b795c100232b405070f4700e3ca6130b@eucas1p1.samsung.com>
2019-07-15 12:44     ` [PATCH v1 35/50] ARM: dts: exynos: change speed and parent of NoC clock " Lukasz Luba
     [not found]   ` <CGME20190715124503eucas1p1d41112e5c10c4fd21c7aada7bdf8e513@eucas1p1.samsung.com>
2019-07-15 12:44     ` [PATCH v1 36/50] ARM: dts: exynos: change ACLK100_NOC config in Exynos5422 Lukasz Luba
     [not found]   ` <CGME20190715124504eucas1p1afe0da2c6ac3a8b45d85017a77ba9edf@eucas1p1.samsung.com>
2019-07-15 12:44     ` [PATCH v1 37/50] ARM: dts: exynos: change parent and rate of bus_fsys " Lukasz Luba
2019-07-17 10:25       ` Krzysztof Kozlowski
2019-07-17 10:38         ` Lukasz Luba
2019-07-17 10:45           ` Krzysztof Kozlowski
2019-07-17 11:05             ` Lukasz Luba
2019-07-17 11:11               ` Krzysztof Kozlowski
2019-07-17 12:55                 ` Lukasz Luba
2019-07-23 12:06                   ` Krzysztof Kozlowski
     [not found]   ` <CGME20190715124505eucas1p14e68a537cb53cda2cfd832e59425cd25@eucas1p1.samsung.com>
2019-07-15 12:44     ` [PATCH v1 38/50] ARM: dts: exynos: change parent and rate of bus_fsys2 " Lukasz Luba
     [not found]   ` <CGME20190715124506eucas1p2b4e906a88978e3edd875e92b1a9fedc4@eucas1p2.samsung.com>
2019-07-15 12:44     ` [PATCH v1 39/50] ARM: dts: exynos: change parent and rate of bus_fsys_acp " Lukasz Luba
     [not found]   ` <CGME20190715124507eucas1p17793ab35cd6a64fc5626b751e7f095ee@eucas1p1.samsung.com>
2019-07-15 12:44     ` [PATCH v1 40/50] ARM: dts: exynos: change parent and rate of bus_gen " Lukasz Luba
     [not found]   ` <CGME20190715124508eucas1p2b66d72b7eadd7428063387c6881aca64@eucas1p2.samsung.com>
2019-07-15 12:44     ` [PATCH v1 41/50] ARM: dts: exynos: change parent and rate of bus_g2d " Lukasz Luba
     [not found]   ` <CGME20190715124508eucas1p2f2e09e296dd4ad97a52a2023ede8ae98@eucas1p2.samsung.com>
2019-07-15 12:44     ` [PATCH v1 42/50] ARM: dts: exynos: change parent and rate of bus_mscl " Lukasz Luba
     [not found]   ` <CGME20190715124509eucas1p1f2e44af951158fbef1a245467956ef93@eucas1p1.samsung.com>
2019-07-15 12:44     ` [PATCH v1 43/50] ARM: dts: exynos: add bus_isp " Lukasz Luba
2019-07-17 10:02       ` Krzysztof Kozlowski
2019-07-17 10:12         ` Lukasz Luba
     [not found]   ` <CGME20190715124510eucas1p1a88fcaa3b6175a5dae69e6879a534746@eucas1p1.samsung.com>
2019-07-15 12:44     ` [PATCH v1 44/50] ARM: dts: exynos: change rate of bus_jpeg " Lukasz Luba
     [not found]   ` <CGME20190715124511eucas1p2b11ef3a5bc093e686ae5450d16785225@eucas1p2.samsung.com>
2019-07-15 12:44     ` [PATCH v1 45/50] ARM: dts: exynos: change rate of bus_disp1_fimd " Lukasz Luba
     [not found]   ` <CGME20190715124512eucas1p1bd847805f945ada00f2b7952592cc104@eucas1p1.samsung.com>
2019-07-15 12:44     ` [PATCH v1 46/50] ARM: dts: exynos: change rates of bus_disp1 " Lukasz Luba
     [not found]   ` <CGME20190715124513eucas1p2c30a951141622994d350df5e61fdaed4@eucas1p2.samsung.com>
2019-07-15 12:44     ` [PATCH v1 47/50] ARM: dts: exynos: change rate of bus_gscl_scaler " Lukasz Luba
     [not found]   ` <CGME20190715124514eucas1p1531a88cfb9b4e2fdb801074963372688@eucas1p1.samsung.com>
2019-07-15 12:44     ` [PATCH v1 48/50] ARM: dts: exynos: set proper parents to bus_isp266 Exynos5422 Lukasz Luba
     [not found]   ` <CGME20190715124514eucas1p1dcbbcbac0503980825d5e4ebae32003b@eucas1p1.samsung.com>
2019-07-15 12:44     ` [PATCH v1 49/50] ARM: dts: exynos: add buses support for Exynos5800 Peach Pi Lukasz Luba
     [not found]   ` <CGME20190715124515eucas1p240a8c61dd62d56cbbd0e4d313be2273e@eucas1p2.samsung.com>
2019-07-15 12:44     ` [PATCH v1 50/50] ARM: dts: exynos: change MMC0 clock parent in " Lukasz Luba

Reply instructions:

You may reply publically to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20190715124417.4787-1-l.luba@partner.samsung.com \
    --to=l.luba@partner.samsung.com \
    --cc=a.hajda@samsung.com \
    --cc=b.zolnierkie@samsung.com \
    --cc=cw00.choi@samsung.com \
    --cc=devicetree@vger.kernel.org \
    --cc=kgene@kernel.org \
    --cc=krzk@kernel.org \
    --cc=kyungmin.park@samsung.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-clk@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-samsung-soc@vger.kernel.org \
    --cc=m.szyprowski@samsung.com \
    --cc=mark.rutland@arm.com \
    --cc=mturquette@baylibre.com \
    --cc=myungjoo.ham@samsung.com \
    --cc=robh+dt@kernel.org \
    --cc=s.nawrocki@samsung.com \
    --cc=sboyd@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

Linux-ARM-Kernel Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/linux-arm-kernel/0 linux-arm-kernel/git/0.git
	git clone --mirror https://lore.kernel.org/linux-arm-kernel/1 linux-arm-kernel/git/1.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 linux-arm-kernel linux-arm-kernel/ https://lore.kernel.org/linux-arm-kernel \
		linux-arm-kernel@lists.infradead.org infradead-linux-arm-kernel@archiver.kernel.org
	public-inbox-index linux-arm-kernel

Example config snippet for mirrors

Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.infradead.lists.linux-arm-kernel


AGPL code for this site: git clone https://public-inbox.org/ public-inbox