Re: [PATCH 5/5] coresight: tmc-etr: Check if non-secure access is enabled

From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 5/5] coresight: tmc-etr: Check if non-secure access is enabled
Date: Mon, 29 Jul 2019 13:49:31 -0600	[thread overview]
Message-ID: <20190729194931.GC26214@xps15> (raw)
In-Reply-To: <20190724114312.1024-6-suzuki.poulose@arm.com>

On Wed, Jul 24, 2019 at 12:43:12PM +0100, Suzuki K Poulose wrote:
> CoreSight TMC-ETR must have the non-secure invasive debug access
> enabled for use by self-hosted tracing. Without it, there is no
> point in enabling the ETR. So, let us check it in the TMC_AUTHSTATUS
> register and fail the probe if it is disabled.
> 
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
>  drivers/hwtracing/coresight/coresight-tmc.c | 12 ++++++++++++
>  drivers/hwtracing/coresight/coresight-tmc.h |  3 +++
>  2 files changed, 15 insertions(+)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
> index be37aff573b4..3055bf8e2236 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc.c
> @@ -236,6 +236,7 @@ coresight_tmc_reg(ffcr, TMC_FFCR);
>  coresight_tmc_reg(mode, TMC_MODE);
>  coresight_tmc_reg(pscr, TMC_PSCR);
>  coresight_tmc_reg(axictl, TMC_AXICTL);
> +coresight_tmc_reg(authstatus, TMC_AUTHSTATUS);
>  coresight_tmc_reg(devid, CORESIGHT_DEVID);
>  coresight_tmc_reg64(rrp, TMC_RRP, TMC_RRPHI);
>  coresight_tmc_reg64(rwp, TMC_RWP, TMC_RWPHI);
> @@ -255,6 +256,7 @@ static struct attribute *coresight_tmc_mgmt_attrs[] = {
>  	&dev_attr_devid.attr,
>  	&dev_attr_dba.attr,
>  	&dev_attr_axictl.attr,
> +	&dev_attr_authstatus.attr,
>  	NULL,
>  };
>  
> @@ -342,6 +344,13 @@ static inline bool tmc_etr_can_use_sg(struct device *dev)
>  	return fwnode_property_present(dev->fwnode, "arm,scatter-gather");
>  }
>  
> +static inline bool tmc_etr_has_non_secure_access(struct tmc_drvdata *drvdata)
> +{
> +	u32 auth = readl_relaxed(drvdata->base + TMC_AUTHSTATUS);
> +
> +	return (auth & TMC_AUTH_NSID_MASK) == 0x3;
> +}
> +
>  /* Detect and initialise the capabilities of a TMC ETR */
>  static int tmc_etr_setup_caps(struct device *parent, u32 devid, void *dev_caps)
>  {
> @@ -349,6 +358,9 @@ static int tmc_etr_setup_caps(struct device *parent, u32 devid, void *dev_caps)
>  	u32 dma_mask = 0;
>  	struct tmc_drvdata *drvdata = dev_get_drvdata(parent);
>  
> +	if (!tmc_etr_has_non_secure_access(drvdata))
> +		return -EACCES;
> +
>  	/* Set the unadvertised capabilities */
>  	tmc_etr_init_caps(drvdata, (u32)(unsigned long)dev_caps);
>  
> diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
> index 95d2e2747970..4c59f2a4ad0e 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc.h
> +++ b/drivers/hwtracing/coresight/coresight-tmc.h
> @@ -39,6 +39,7 @@
>  #define TMC_ITATBCTR2		0xef0
>  #define TMC_ITATBCTR1		0xef4
>  #define TMC_ITATBCTR0		0xef8
> +#define TMC_AUTHSTATUS		0xfb8
>  
>  /* register description */
>  /* TMC_CTL - 0x020 */
> @@ -90,6 +91,8 @@
>  #define TMC_DEVID_AXIAW_SHIFT	17
>  #define TMC_DEVID_AXIAW_MASK	0x7f
>  
> +#define TMC_AUTH_NSID_MASK	GENMASK(1, 0)
> +
>  enum tmc_config_type {
>  	TMC_CONFIG_TYPE_ETB,
>  	TMC_CONFIG_TYPE_ETR,

I have also picked-up patches 3-5.

Thanks,
Mathieu

> -- 
> 2.21.0
> 

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