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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Jul 17, 2019 at 09:17:05AM +0100, Julien Thierry wrote: > Since the PMU driver uses direct registers for counter > setup/manipulation, locking around these operations is no longer needed. > > For operations that can be called with interrupts enabled, preemption > still needs to be disabled to ensure the programming of the PMU is > done on the expected CPU and not migrated mid-programming. > > Signed-off-by: Julien Thierry > Cc: Will Deacon > Cc: Mark Rutland > Cc: Peter Zijlstra > Cc: Ingo Molnar > Cc: Arnaldo Carvalho de Melo > Cc: Alexander Shishkin > Cc: Jiri Olsa > Cc: Namhyung Kim > Cc: Catalin Marinas > --- > arch/arm64/kernel/perf_event.c | 30 ++---------------------------- > 1 file changed, 2 insertions(+), 28 deletions(-) > > diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c > index 838758f..0e2cf5d 100644 > --- a/arch/arm64/kernel/perf_event.c > +++ b/arch/arm64/kernel/perf_event.c > @@ -673,15 +673,10 @@ static inline u32 armv8pmu_getreset_flags(void) > > static void armv8pmu_enable_event(struct perf_event *event) > { > - unsigned long flags; > - struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); > - struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events); > - > /* > * Enable counter and interrupt, and set the counter to count > * the event that we're interested in. > */ > - raw_spin_lock_irqsave(&events->pmu_lock, flags); > > /* > * Disable counter > @@ -702,21 +697,10 @@ static void armv8pmu_enable_event(struct perf_event *event) > * Enable counter > */ > armv8pmu_enable_event_counter(event); > - > - raw_spin_unlock_irqrestore(&events->pmu_lock, flags); > } With the implicit ISBs now removed by virtue of addressing the counter register directly, what prevents the programming of the evtype being reordered with respect to disabling/enabling the counter? > static void armv8pmu_disable_event(struct perf_event *event) > { > - unsigned long flags; > - struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); > - struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events); > - > - /* > - * Disable counter and interrupt > - */ > - raw_spin_lock_irqsave(&events->pmu_lock, flags); > - > /* > * Disable counter > */ > @@ -726,30 +710,20 @@ static void armv8pmu_disable_event(struct perf_event *event) > * Disable interrupt for this counter > */ > armv8pmu_disable_event_irq(event); > - > - raw_spin_unlock_irqrestore(&events->pmu_lock, flags); > } > > static void armv8pmu_start(struct arm_pmu *cpu_pmu) > { > - unsigned long flags; > - struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events); > - > - raw_spin_lock_irqsave(&events->pmu_lock, flags); > + WARN_ON_ONCE(preemptible()); > /* Enable all counters */ > armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMU_PMCR_E); > - raw_spin_unlock_irqrestore(&events->pmu_lock, flags); > } > > static void armv8pmu_stop(struct arm_pmu *cpu_pmu) > { > - unsigned long flags; > - struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events); > - > - raw_spin_lock_irqsave(&events->pmu_lock, flags); > + WARN_ON_ONCE(preemptible()); I don't think we need these WARN_ONs -- these are very much per-CPU operations from the context of the perf core, so we'll be ok. Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel