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From: Steve Capper <steve.capper@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: crecklin@redhat.com, ard.biesheuvel@linaro.org,
	catalin.marinas@arm.com, bhsharma@redhat.com,
	Steve Capper <steve.capper@arm.com>,
	maz@kernel.org, will@kernel.org
Subject: [PATCH V5 11/12] arm64: mm: Remove vabits_user
Date: Wed,  7 Aug 2019 16:55:23 +0100	[thread overview]
Message-ID: <20190807155524.5112-12-steve.capper@arm.com> (raw)
In-Reply-To: <20190807155524.5112-1-steve.capper@arm.com>

Previous patches have enabled 52-bit kernel + user VAs and there is no
longer any scenario where user VA != kernel VA size.

This patch removes the, now redundant, vabits_user variable and replaces
usage with vabits_actual where appropriate.

Signed-off-by: Steve Capper <steve.capper@arm.com>

---

New in V5
---
 arch/arm64/include/asm/memory.h       | 3 ---
 arch/arm64/include/asm/pointer_auth.h | 2 +-
 arch/arm64/include/asm/processor.h    | 2 +-
 arch/arm64/kernel/head.S              | 7 +------
 arch/arm64/mm/fault.c                 | 3 +--
 arch/arm64/mm/mmu.c                   | 2 --
 arch/arm64/mm/proc.S                  | 2 +-
 7 files changed, 5 insertions(+), 16 deletions(-)

diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h
index 3b5d1327035e..56e79da139c2 100644
--- a/arch/arm64/include/asm/memory.h
+++ b/arch/arm64/include/asm/memory.h
@@ -194,9 +194,6 @@ static inline unsigned long kaslr_offset(void)
 	return kimage_vaddr - KIMAGE_VADDR;
 }
 
-/* the actual size of a user virtual address */
-extern u64			vabits_user;
-
 /*
  * Allow all memory at the discovery stage. We will clip it later.
  */
diff --git a/arch/arm64/include/asm/pointer_auth.h b/arch/arm64/include/asm/pointer_auth.h
index d328540cb85e..7a24bad1a58b 100644
--- a/arch/arm64/include/asm/pointer_auth.h
+++ b/arch/arm64/include/asm/pointer_auth.h
@@ -69,7 +69,7 @@ extern int ptrauth_prctl_reset_keys(struct task_struct *tsk, unsigned long arg);
  * The EL0 pointer bits used by a pointer authentication code.
  * This is dependent on TBI0 being enabled, or bits 63:56 would also apply.
  */
-#define ptrauth_user_pac_mask()	GENMASK(54, vabits_user)
+#define ptrauth_user_pac_mask()	GENMASK(54, vabits_actual)
 
 /* Only valid for EL0 TTBR0 instruction pointers */
 static inline unsigned long ptrauth_strip_insn_pac(unsigned long ptr)
diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h
index 0e1f2770192a..e4c93945e477 100644
--- a/arch/arm64/include/asm/processor.h
+++ b/arch/arm64/include/asm/processor.h
@@ -43,7 +43,7 @@
  */
 
 #define DEFAULT_MAP_WINDOW_64	(UL(1) << VA_BITS_MIN)
-#define TASK_SIZE_64		(UL(1) << vabits_user)
+#define TASK_SIZE_64		(UL(1) << vabits_actual)
 
 #ifdef CONFIG_COMPAT
 #if defined(CONFIG_ARM64_64K_PAGES) && defined(CONFIG_KUSER_HELPERS)
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index c8446f8c81f5..949b001a73bb 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -316,11 +316,6 @@ __create_page_tables:
 #endif
 	mov	x5, #VA_BITS_MIN
 1:
-	adr_l	x6, vabits_user
-	str	x5, [x6]
-	dmb	sy
-	dc	ivac, x6		// Invalidate potentially stale cache line
-
 	adr_l	x6, vabits_actual
 	str	x5, [x6]
 	dmb	sy
@@ -795,7 +790,7 @@ ENDPROC(__enable_mmu)
 
 ENTRY(__cpu_secondary_check52bitva)
 #ifdef CONFIG_ARM64_VA_BITS_52
-	ldr_l	x0, vabits_user
+	ldr_l	x0, vabits_actual
 	cmp	x0, #52
 	b.ne	2f
 
diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c
index 86fc1aff3462..3ef0a9f64240 100644
--- a/arch/arm64/mm/fault.c
+++ b/arch/arm64/mm/fault.c
@@ -140,8 +140,7 @@ static void show_pte(unsigned long addr)
 
 	pr_alert("%s pgtable: %luk pages, %llu-bit VAs, pgdp=%016lx\n",
 		 mm == &init_mm ? "swapper" : "user", PAGE_SIZE / SZ_1K,
-		 mm == &init_mm ? vabits_actual : (int)vabits_user,
-		 (unsigned long)virt_to_phys(mm->pgd));
+		 vabits_actual, (unsigned long)virt_to_phys(mm->pgd));
 	pgdp = pgd_offset(mm, addr);
 	pgd = READ_ONCE(*pgdp);
 	pr_alert("[%016lx] pgd=%016llx", addr, pgd_val(pgd));
diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
index 07b30e6d17f8..0c8f7e55f859 100644
--- a/arch/arm64/mm/mmu.c
+++ b/arch/arm64/mm/mmu.c
@@ -40,8 +40,6 @@
 
 u64 idmap_t0sz = TCR_T0SZ(VA_BITS);
 u64 idmap_ptrs_per_pgd = PTRS_PER_PGD;
-u64 vabits_user __ro_after_init;
-EXPORT_SYMBOL(vabits_user);
 
 u64 __section(".mmuoff.data.write") vabits_actual;
 EXPORT_SYMBOL(vabits_actual);
diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index 8b021c5c0884..391f9cabfe60 100644
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -439,7 +439,7 @@ ENTRY(__cpu_setup)
 	tcr_clear_errata_bits x10, x9, x5
 
 #ifdef CONFIG_ARM64_VA_BITS_52
-	ldr_l		x9, vabits_user
+	ldr_l		x9, vabits_actual
 	sub		x9, xzr, x9
 	add		x9, x9, #64
 	tcr_set_t1sz	x10, x9
-- 
2.20.1


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  parent reply	other threads:[~2019-08-07 15:58 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-07 15:55 [PATCH V5 00/12] 52-bit kernel + user VAs Steve Capper
2019-08-07 15:55 ` [PATCH V5 01/12] arm64: mm: Remove bit-masking optimisations for PAGE_OFFSET and VMEMMAP_START Steve Capper
2019-08-07 15:55 ` [PATCH V5 02/12] arm64: mm: Flip kernel VA space Steve Capper
2019-08-07 16:12   ` Catalin Marinas
2019-08-07 15:55 ` [PATCH V5 03/12] arm64: kasan: Switch to using KASAN_SHADOW_OFFSET Steve Capper
2019-08-07 16:12   ` Catalin Marinas
2019-08-14 15:20   ` [PATCH] arm64: fix CONFIG_KASAN_SW_TAGS && CONFIG_KASAN_INLINE (was: Re: [PATCH V5 03/12] arm64: kasan: Switch to using) KASAN_SHADOW_OFFSET Mark Rutland
2019-08-14 15:57     ` Will Deacon
2019-08-14 16:03       ` Mark Rutland
2019-08-14 17:53         ` Steve Capper
2019-08-15 12:09         ` Will Deacon
2019-08-15 12:21           ` [PATCH] arm64: fix CONFIG_KASAN_SW_TAGS && CONFIG_KASAN_INLINE Andrey Ryabinin
2019-08-15 12:22             ` Will Deacon
2019-08-20  6:02           ` [PATCH] arm64: fix CONFIG_KASAN_SW_TAGS && CONFIG_KASAN_INLINE (was: Re: [PATCH V5 03/12] arm64: kasan: Switch to using) KASAN_SHADOW_OFFSET Bhupesh Sharma
2019-08-14 16:07     ` Steve Capper
2019-08-14 16:14       ` Steve Capper
2019-08-07 15:55 ` [PATCH V5 04/12] arm64: dump: De-constify VA_START and KASAN_SHADOW_START Steve Capper
2019-08-07 15:55 ` [PATCH V5 05/12] arm64: mm: Introduce VA_BITS_MIN Steve Capper
2019-08-07 16:14   ` Catalin Marinas
2019-08-07 15:55 ` [PATCH V5 06/12] arm64: mm: Introduce vabits_actual Steve Capper
2019-08-07 16:16   ` Catalin Marinas
2019-08-07 15:55 ` [PATCH V5 07/12] arm64: mm: Logic to make offset_ttbr1 conditional Steve Capper
2019-08-07 15:55 ` [PATCH V5 08/12] arm64: mm: Separate out vmemmap Steve Capper
2019-08-07 15:55 ` [PATCH V5 09/12] arm64: mm: Modify calculation of VMEMMAP_SIZE Steve Capper
2019-08-07 15:55 ` [PATCH V5 10/12] arm64: mm: Introduce 52-bit Kernel VAs Steve Capper
2019-08-07 15:55 ` Steve Capper [this message]
2019-08-07 16:17   ` [PATCH V5 11/12] arm64: mm: Remove vabits_user Catalin Marinas
2019-08-07 15:55 ` [PATCH V5 12/12] docs: arm64: Add layout and 52-bit info to memory document Steve Capper
2019-08-09 16:47 ` [PATCH V5 00/12] 52-bit kernel + user VAs Will Deacon
2019-08-13 11:23   ` Steve Capper
2019-08-13 11:59     ` Will Deacon
2019-08-13 12:43   ` Geert Uytterhoeven
2019-08-13 13:10     ` Will Deacon
2019-08-13 13:36       ` Geert Uytterhoeven
2019-08-14  8:04         ` Bhupesh Sharma
2019-08-14  8:21           ` Will Deacon
2019-08-14 11:59             ` Bhupesh Sharma
2019-08-14 12:24               ` Will Deacon

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