From: Vidya Sagar <vidyas@nvidia.com>
To: <lorenzo.pieralisi@arm.com>, <bhelgaas@google.com>,
<robh+dt@kernel.org>, <mark.rutland@arm.com>,
<thierry.reding@gmail.com>, <jonathanh@nvidia.com>,
<kishon@ti.com>, <catalin.marinas@arm.com>, <will.deacon@arm.com>,
<jingoohan1@gmail.com>, <gustavo.pimentel@synopsys.com>
Cc: devicetree@vger.kernel.org, mmaddireddy@nvidia.com,
kthota@nvidia.com, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org, mperttunen@nvidia.com,
linux-tegra@vger.kernel.org, digetx@gmail.com, vidyas@nvidia.com,
linux-arm-kernel@lists.infradead.org, sagar.tv@gmail.com
Subject: [PATCH V15 03/13] PCI: dwc: Perform dbi regs write lock towards the end
Date: Fri, 9 Aug 2019 10:15:59 +0530 [thread overview]
Message-ID: <20190809044609.20401-4-vidyas@nvidia.com> (raw)
In-Reply-To: <20190809044609.20401-1-vidyas@nvidia.com>
Some of DesignWare core's DBI registers (a.k.a configuration space
registers) are write-protected with a lock without enabling which they are
read-only by default. These write-protected registers are implementation
specific. Tegra194's BAR-0 register which is at offset 0x10 in the
configuration space is an example. Current implementation in
dw_pcie_setup_rc() API attempts to unlock those write-protected registers
whenever they are updated and lock them back again for writing. This patch
attempts to unlock all such write-protected registers for writing in the
beginning of the API once and lock them back again towards the end to avoid
bloating the API with multiple unlock/lock sequences for all those
write-protected registers.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Acked-by: Jingoo Han <jingoohan1@gmail.com>
---
V15:
* None
V14:
* None
V13:
* None
V12:
* Modified commit message to make it explicit that write-protected registers are
implementation specific.
V11:
* None
V10:
* None
V9:
* None
V8:
* None
V7:
* None
V6:
* Moved write enable to the beginning of the API and write disable to the end
V5:
* None
V4:
* None
V3:
* None
V2:
* None
drivers/pci/controller/dwc/pcie-designware-host.c | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index f93252d0da5b..d3156446ff27 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -628,6 +628,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
u32 val, ctrl, num_ctrls;
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ /*
+ * Enable DBI read-only registers for writing/updating configuration.
+ * Write permission gets disabled towards the end of this function.
+ */
+ dw_pcie_dbi_ro_wr_en(pci);
+
dw_pcie_setup(pci);
if (!pp->ops->msi_host_init) {
@@ -650,12 +656,10 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000);
/* Setup interrupt pins */
- dw_pcie_dbi_ro_wr_en(pci);
val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE);
val &= 0xffff00ff;
val |= 0x00000100;
dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val);
- dw_pcie_dbi_ro_wr_dis(pci);
/* Setup bus numbers */
val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
@@ -687,15 +691,13 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
- /* Enable write permission for the DBI read-only register */
- dw_pcie_dbi_ro_wr_en(pci);
/* Program correct class for RC */
dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
- /* Better disable write permission right after the update */
- dw_pcie_dbi_ro_wr_dis(pci);
dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
val |= PORT_LOGIC_SPEED_CHANGE;
dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
+
+ dw_pcie_dbi_ro_wr_dis(pci);
}
EXPORT_SYMBOL_GPL(dw_pcie_setup_rc);
--
2.17.1
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next prev parent reply other threads:[~2019-08-09 4:47 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-09 4:45 [PATCH V15 00/13] PCI: tegra: Add Tegra194 PCIe support Vidya Sagar
2019-08-09 4:45 ` [PATCH V15 01/13] PCI: Add #defines for some of PCIe spec r4.0 features Vidya Sagar
2019-08-09 4:45 ` [PATCH V15 02/13] PCI: Disable MSI for Tegra root ports Vidya Sagar
2019-08-09 4:45 ` Vidya Sagar [this message]
2019-08-09 4:46 ` [PATCH V15 04/13] PCI: dwc: Move config space capability search API Vidya Sagar
2019-08-09 4:46 ` [PATCH V15 05/13] PCI: dwc: Add ext " Vidya Sagar
2019-08-09 4:46 ` [PATCH V15 06/13] PCI: dwc: Export dw_pcie_wait_for_link() API Vidya Sagar
2019-08-09 4:46 ` [PATCH V15 07/13] dt-bindings: PCI: designware: Add binding for CDM register check Vidya Sagar
2019-08-09 4:46 ` [PATCH V15 08/13] PCI: dwc: Add support to enable " Vidya Sagar
2019-08-09 4:46 ` [PATCH V15 09/13] dt-bindings: Add PCIe supports-clkreq property Vidya Sagar
2019-08-09 4:46 ` [PATCH V15 10/13] dt-bindings: PCI: tegra: Add device tree support for Tegra194 Vidya Sagar
2019-08-09 4:46 ` [PATCH V15 11/13] dt-bindings: PHY: P2U: Add Tegra194 P2U block Vidya Sagar
2019-08-09 4:46 ` [PATCH V15 12/13] phy: tegra: Add PCIe PIPE2UPHY support Vidya Sagar
2019-08-12 10:23 ` Thierry Reding
2019-08-09 4:46 ` [PATCH V15 13/13] PCI: tegra: Add Tegra194 PCIe support Vidya Sagar
2019-08-13 10:57 ` Lorenzo Pieralisi
2019-08-13 11:36 ` Vidya Sagar
2019-08-12 10:25 ` [PATCH V15 00/13] " Thierry Reding
2019-08-12 10:29 ` Vidya Sagar
2019-08-12 10:34 ` Thierry Reding
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