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From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: sboyd@kernel.org, mturquette@baylibre.com, robh+dt@kernel.org
Cc: devicetree@vger.kernel.org,
	Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
	darren.tsao@bitmain.com, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, fisher.cheng@bitmain.com,
	alec.lin@bitmain.com, linux-clk@vger.kernel.org,
	haitao.suo@bitmain.com
Subject: [PATCH v2 0/7] Add Bitmain BM1880 clock driver
Date: Sun, 18 Aug 2019 00:06:07 +0530
Message-ID: <20190817183614.8429-1-manivannan.sadhasivam@linaro.org> (raw)

Hello,

This patchset adds common clock driver for Bitmain BM1880 SoC clock
controller. The clock controller consists of gate, divider, mux
and pll clocks with different compositions. Hence, the driver uses
composite clock structure in place where multiple clocking units are
combined together.

This patchset also removes UART fixed clock and sources clocks from clock
controller for Sophon Edge board where the driver has been validated.

Thanks,
Mani

Changes in v2:

* Converted the dt binding to YAML
* Incorporated review comments from Stephen (majority of change is switching
  to new way of specifying clk parents)

Manivannan Sadhasivam (7):
  dt-bindings: clock: Add devicetree binding for BM1880 SoC
  arm64: dts: bitmain: Add clock controller support for BM1880 SoC
  arm64: dts: bitmain: Source common clock for UART controllers
  clk: Add common clock driver for BM1880 SoC
  MAINTAINERS: Add entry for BM1880 SoC clock driver
  clk: Warn if clk_init_data is not zero initialized
  clk: Zero init clk_init_data in helpers

 .../bindings/clock/bitmain,bm1880-clk.yaml    |  83 ++
 MAINTAINERS                                   |   2 +
 .../boot/dts/bitmain/bm1880-sophon-edge.dts   |   9 -
 arch/arm64/boot/dts/bitmain/bm1880.dtsi       |  28 +
 drivers/clk/Kconfig                           |   6 +
 drivers/clk/Makefile                          |   1 +
 drivers/clk/clk-bm1880.c                      | 970 ++++++++++++++++++
 drivers/clk/clk-composite.c                   |   2 +-
 drivers/clk/clk-divider.c                     |   2 +-
 drivers/clk/clk-fixed-rate.c                  |   2 +-
 drivers/clk/clk-gate.c                        |   2 +-
 drivers/clk/clk-mux.c                         |   2 +-
 drivers/clk/clk.c                             |   8 +
 include/dt-bindings/clock/bm1880-clock.h      |  82 ++
 14 files changed, 1185 insertions(+), 14 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml
 create mode 100644 drivers/clk/clk-bm1880.c
 create mode 100644 include/dt-bindings/clock/bm1880-clock.h

-- 
2.17.1


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Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-17 18:36 Manivannan Sadhasivam [this message]
2019-08-17 18:36 ` [PATCH v2 1/7] dt-bindings: clock: Add devicetree binding for BM1880 SoC Manivannan Sadhasivam
2019-08-17 18:36 ` [PATCH v2 2/7] arm64: dts: bitmain: Add clock controller support " Manivannan Sadhasivam
2019-08-17 18:36 ` [PATCH v2 3/7] arm64: dts: bitmain: Source common clock for UART controllers Manivannan Sadhasivam
2019-08-17 18:36 ` [PATCH v2 4/7] clk: Add common clock driver for BM1880 SoC Manivannan Sadhasivam
2019-08-17 18:36 ` [PATCH v2 5/7] MAINTAINERS: Add entry for BM1880 SoC clock driver Manivannan Sadhasivam
2019-08-17 18:36 ` [PATCH v2 6/7] clk: Warn if clk_init_data is not zero initialized Manivannan Sadhasivam
2019-08-17 18:36 ` [PATCH v2 7/7] clk: Zero init clk_init_data in helpers Manivannan Sadhasivam

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