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Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hzdUp-0003C2-TM; Mon, 19 Aug 2019 08:58:35 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hzdUl-0003Ba-Ro for linux-arm-kernel@lists.infradead.org; Mon, 19 Aug 2019 08:58:33 +0000 Received: from X250 (37.80-203-192.nextgentel.com [80.203.192.37]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id B85C42086C; Mon, 19 Aug 2019 08:58:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1566205111; bh=dvHPVhvUax2+B3bDV3fweqBjG7vvPVh6dCKZsep59Pw=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=KiLkiCT8nfWpjVu1iC54rmDHnjngi43bXYjsRRKC79q410E2fqlD6BUOcKlmXkQ8k hOcHYlDT3r7pjhk3Af/LeKPsdNsFdTLLg4ku+Bs+MnuqV6hkzvO6P0GtrVG6ZlLOM6 vpc03XVU/OIyr5Nmv9U3xE70ZJudAW4z5er7DAcg= Date: Mon, 19 Aug 2019 10:58:17 +0200 From: Shawn Guo To: Stefan-gabriel Mirea Subject: Re: [PATCH v2 3/6] arm64: dts: fsl: Add device tree for S32V234-EVB Message-ID: <20190819085816.GI5999@X250> References: <20190809112853.15846-1-stefan-gabriel.mirea@nxp.com> <20190809112853.15846-4-stefan-gabriel.mirea@nxp.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20190809112853.15846-4-stefan-gabriel.mirea@nxp.com> User-Agent: Mutt/1.5.24 (2015-08-30) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190819_015831_948232_95DC1F29 X-CRM114-Status: GOOD ( 19.35 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "mark.rutland@arm.com" , "devicetree@vger.kernel.org" , "corbet@lwn.net" , "gregkh@linuxfoundation.org" , "jslaby@suse.com" , "linux-doc@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Leo Li , Cosmin Stefan Stoica , "robh+dt@kernel.org" , Dan Nica , "linux-serial@vger.kernel.org" , "catalin.marinas@arm.com" , "will@kernel.org" , "linux-arm-kernel@lists.infradead.org" , Larisa Ileana Grigore Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Aug 09, 2019 at 11:29:12AM +0000, Stefan-gabriel Mirea wrote: > From: Stoica Cosmin-Stefan > > Add initial version of device tree for S32V234-EVB, including nodes for the > 4 Cortex-A53 cores, AIPS bus with UART modules, ARM architected timer and > Generic Interrupt Controller (GIC). > > Keep SoC level separate from board level to let future boards with this SoC > share common properties, while the dts files will keep board-dependent > properties. > > Signed-off-by: Stoica Cosmin-Stefan > Signed-off-by: Mihaela Martinas > Signed-off-by: Dan Nica > Signed-off-by: Larisa Grigore > Signed-off-by: Phu Luu An > Signed-off-by: Stefan-Gabriel Mirea > --- > arch/arm64/boot/dts/freescale/Makefile | 2 + > .../boot/dts/freescale/fsl-s32v234-evb.dts | 24 ++++ The 'fsl-' prefix can be saved here, so that we can distinguish three families by starting string: imx??? for i.MX, fsl-??? for LayerScape, and s32??? for S32. > .../arm64/boot/dts/freescale/fsl-s32v234.dtsi | 130 ++++++++++++++++++ > 3 files changed, 156 insertions(+) > create mode 100644 arch/arm64/boot/dts/freescale/fsl-s32v234-evb.dts > create mode 100644 arch/arm64/boot/dts/freescale/fsl-s32v234.dtsi > > diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile > index c043aca66572..3af29b58a833 100644 > --- a/arch/arm64/boot/dts/freescale/Makefile > +++ b/arch/arm64/boot/dts/freescale/Makefile > @@ -26,3 +26,5 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb > + > +dtb-$(CONFIG_ARCH_S32) += fsl-s32v234-evb.dtb > diff --git a/arch/arm64/boot/dts/freescale/fsl-s32v234-evb.dts b/arch/arm64/boot/dts/freescale/fsl-s32v234-evb.dts > new file mode 100644 > index 000000000000..92bf6c5563a3 > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/fsl-s32v234-evb.dts > @@ -0,0 +1,24 @@ > +// SPDX-License-Identifier: GPL-2.0-or-later > +/* > + * Copyright 2015-2016 Freescale Semiconductor, Inc. > + * Copyright 2016-2017 NXP > + */ > + > +/dts-v1/; > +#include "fsl-s32v234.dtsi" > + > +/ { > + compatible = "fsl,s32v234-evb", "fsl,s32v234"; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > +}; > + > +&uart0 { > + status = "okay"; > +}; > + > +&uart1 { > + status = "okay"; > +}; > diff --git a/arch/arm64/boot/dts/freescale/fsl-s32v234.dtsi b/arch/arm64/boot/dts/freescale/fsl-s32v234.dtsi > new file mode 100644 > index 000000000000..6d686d3ba997 > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/fsl-s32v234.dtsi > @@ -0,0 +1,130 @@ > +// SPDX-License-Identifier: GPL-2.0-or-later > +/* > + * Copyright 2015-2016 Freescale Semiconductor, Inc. > + * Copyright 2016-2018 NXP > + */ > + > +/memreserve/ 0x80000000 0x00010000; > + > +/ { > + model = "Freescale S32V234"; The 'model' is usually used in board level DTS to describe the board. > + compatible = "fsl,s32v234"; > + interrupt-parent = <&gic>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + aliases { > + serial0 = &uart0; > + serial1 = &uart1; > + }; > + > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x0 0x0>; > + enable-method = "spin-table"; > + cpu-release-addr = <0x0 0x80000000>; > + next-level-cache = <&cluster0_l2_cache>; > + }; Please have a newline between nodes. > + cpu1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x0 0x1>; > + enable-method = "spin-table"; > + cpu-release-addr = <0x0 0x80000000>; > + next-level-cache = <&cluster0_l2_cache>; > + }; > + cpu2: cpu@100 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x0 0x100>; > + enable-method = "spin-table"; > + cpu-release-addr = <0x0 0x80000000>; > + next-level-cache = <&cluster1_l2_cache>; > + }; > + cpu3: cpu@101 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x0 0x101>; > + enable-method = "spin-table"; > + cpu-release-addr = <0x0 0x80000000>; > + next-level-cache = <&cluster1_l2_cache>; > + }; > + > + cluster0_l2_cache: l2-cache0 { > + compatible = "cache"; > + }; > + > + cluster1_l2_cache: l2-cache1 { > + compatible = "cache"; > + }; > + }; > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + compatible = "simple-bus"; > + interrupt-parent = <&gic>; > + ranges; > + > + aips0: aips-bus@40000000 { > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <2>; > + interrupt-parent = <&gic>; > + reg = <0x0 0x40000000 0x0 0x7D000>; > + ranges; > + > + uart0: serial@40053000 { > + compatible = "fsl,s32-linflexuart"; > + reg = <0x0 0x40053000 0x0 0x1000>; > + interrupts = <0 59 1>; Please use GIC_SPI and IRQ_TYPE_xxx defines to make it more readable. > + status = "disabled"; > + }; > + }; > + > + aips1: aips-bus@40080000 { > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <2>; > + interrupt-parent = <&gic>; > + reg = <0x0 0x40080000 0x0 0x70000>; > + ranges; > + > + uart1: serial@400bc000 { > + compatible = "fsl,s32-linflexuart"; > + reg = <0x0 0x400bc000 0x0 0x1000>; > + interrupts = <0 60 1>; > + status = "disabled"; > + }; > + }; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = <1 13 0xf08>, > + <1 14 0xf08>, > + <1 11 0xf08>, > + <1 10 0xf08>; > + /* clock-frequency might be modified by u-boot, depending on the > + * chip version. > + */ > + clock-frequency = <10000000>; > + }; > + > + gic: interrupt-controller@7d001000 { > + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; > + #interrupt-cells = <3>; > + #address-cells = <0>; > + interrupt-controller; > + reg = <0 0x7d001000 0 0x1000>, > + <0 0x7d002000 0 0x2000>, > + <0 0x7d004000 0 0x2000>, > + <0 0x7d006000 0 0x2000>; > + interrupts = <1 9 0xf04>; > + }; We usually put these core platform devices prior to 'soc' node. Shawn > +}; > -- > 2.22.0 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel