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From: Paul Burton <paul.burton@mips.com>
To: Christoph Hellwig <hch@lst.de>
Cc: Shawn Anastasio <shawn@anastas.io>,
	"linux-m68k@lists.linux-m68k.org"
	<linux-m68k@lists.linux-m68k.org>, Will Deacon <will@kernel.org>,
	"linuxppc-dev@lists.ozlabs.org" <linuxppc-dev@lists.ozlabs.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Russell King <linux@armlinux.org.uk>,
	"linux-mips@vger.kernel.org" <linux-mips@vger.kernel.org>,
	"iommu@lists.linux-foundation.org"
	<iommu@lists.linux-foundation.org>,
	Geert Uytterhoeven <geert@linux-m68k.org>,
	Catalin Marinas <catalin.marinas@arm.com>,
	James Hogan <jhogan@kernel.org>, Guan Xuetao <gxt@pku.edu.cn>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	Robin Murphy <robin.murphy@arm.com>
Subject: Re: cleanup the dma_pgprot handling
Date: Fri, 23 Aug 2019 21:58:04 +0000
Message-ID: <20190823215759.zprrwotlbva46y33@pburton-laptop> (raw)
In-Reply-To: <20190816070754.15653-1-hch@lst.de>

Hi Christoph,

On Fri, Aug 16, 2019 at 09:07:48AM +0200, Christoph Hellwig wrote:
> I'd still like to hear a confirmation from the mips folks how
> the write combibe attribute can or can't work with the KSEG1
> uncached segment.

Quoting section 4.8 "Cacheability and Coherency Attributes and Access
Types" of "MIPS Architecture Volume 1: Introduction to the MIPS32
Architecture" (MD00080, revision 6.01):

https://www.mips.com/?do-download=introduction-to-the-mips32-architecture-v6-01

> Memory access types are specified by architecturally-defined and
> implementation-specific Cacheability and Coherency Attribute bits
> (CCAs) generated by the MMU for the access.
>
> Slightly different cacheability and coherency attributes such as
> “cached coherent, update on write” and “cached coherent, exclusive on
> write” can map to the same memory access type; in this case they both
> map to cached coherent. In order to map to the same access type, the
> fundamental mechanisms of both CCAs must be the same.
>
> When the operation of the instruction is affected, the instructions
> are described in terms of memory access types. The load and store
> operations in a processor proceed according to the specific CCA of the
> reference, however, and the pseudocode for load and store common
> functions uses the CCA value rather than the corresponding memory
> access type.

So I believe uncached & uncached accelerated are another case like that
described above - they're 2 different CCAs but the same "access type",
namely uncached.

Section 4.9 then goes on to forbid mixing access types, but not CCAs.

It would be nice if the precise mapping from CCA to access type was
provided, but I don't see that anywhere. I can check with the
architecture team to be sure, but to my knowledge we're fine to mix
access via kseg1 (ie. uncached) & mappings with CCA=7 (uncached
accelerated).

Thanks,
    Paul
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  parent reply index

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-16  7:07 Christoph Hellwig
2019-08-16  7:07 ` [PATCH 1/6] MIPS: remove support for DMA_ATTR_WRITE_COMBINE Christoph Hellwig
2019-08-16  7:07 ` [PATCH 2/6] unicore32: remove the unused pgprot_dmacoherent define Christoph Hellwig
2019-08-16  7:07 ` [PATCH 3/6] arm-nommu: " Christoph Hellwig
2019-08-16  7:07 ` [PATCH 4/6] dma-mapping: remove arch_dma_mmap_pgprot Christoph Hellwig
2019-08-16  7:43   ` Geert Uytterhoeven
2019-08-16  7:07 ` [PATCH 5/6] dma-mapping: make dma_atomic_pool_init self-contained Christoph Hellwig
2019-08-16  7:07 ` [PATCH 6/6] arm64: document the choice of page attributes for pgprot_dmacoherent Christoph Hellwig
2019-08-16 17:31   ` Will Deacon
2019-08-16 17:36     ` Mark Rutland
2019-08-16 17:59     ` Christoph Hellwig
2019-08-16 18:05       ` Will Deacon
2019-08-23 21:58 ` Paul Burton [this message]
2019-08-24 22:34   ` cleanup the dma_pgprot handling Christoph Hellwig

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