From: Rob Herring <robh@kernel.org> To: "René van Dorst" <opensource@vdorst.com> Cc: Andrew Lunn <andrew@lunn.ch>, Florian Fainelli <f.fainelli@gmail.com>, Frank Wunderlich <frank-w@public-files.de>, netdev@vger.kernel.org, Sean Wang <sean.wang@mediatek.com>, linux-mips@vger.kernel.org, "David S . Miller" <davem@davemloft.net>, devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, John Crispin <john@phrozen.org>, Matthias Brugger <matthias.bgg@gmail.com>, Vivien Didelot <vivien.didelot@gmail.com>, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH net-next v2 2/3] dt-bindings: net: dsa: mt7530: Add support for port 5 Date: Tue, 27 Aug 2019 17:22:51 -0500 Message-ID: <20190827222251.GA30507@bogus> (raw) In-Reply-To: <20190821144547.15113-3-opensource@vdorst.com> On Wed, Aug 21, 2019 at 04:45:46PM +0200, René van Dorst wrote: > MT7530 port 5 has many modes/configurations. > Update the documentation how to use port 5. > > Signed-off-by: René van Dorst <opensource@vdorst.com> > Cc: devicetree@vger.kernel.org > Cc: Rob Herring <robh@kernel.org> > v1->v2: > * Adding extra note about RGMII2 and gpio use. > rfc->v1: > * No change The changelog goes below the '---' > --- > .../devicetree/bindings/net/dsa/mt7530.txt | 218 ++++++++++++++++++ > 1 file changed, 218 insertions(+) > > diff --git a/Documentation/devicetree/bindings/net/dsa/mt7530.txt b/Documentation/devicetree/bindings/net/dsa/mt7530.txt > index 47aa205ee0bd..43993aae3f9c 100644 > --- a/Documentation/devicetree/bindings/net/dsa/mt7530.txt > +++ b/Documentation/devicetree/bindings/net/dsa/mt7530.txt > @@ -35,6 +35,42 @@ Required properties for the child nodes within ports container: > - phy-mode: String, must be either "trgmii" or "rgmii" for port labeled > "cpu". > > +Port 5 of the switch is muxed between: > +1. GMAC5: GMAC5 can interface with another external MAC or PHY. > +2. PHY of port 0 or port 4: PHY interfaces with an external MAC like 2nd GMAC > + of the SOC. Used in many setups where port 0/4 becomes the WAN port. > + Note: On a MT7621 SOC with integrated switch: 2nd GMAC can only connected to > + GMAC5 when the gpios for RGMII2 (GPIO 22-33) are not used and not > + connected to external component! > + > +Port 5 modes/configurations: > +1. Port 5 is disabled and isolated: An external phy can interface to the 2nd > + GMAC of the SOC. > + In the case of a build-in MT7530 switch, port 5 shares the RGMII bus with 2nd > + GMAC and an optional external phy. Mind the GPIO/pinctl settings of the SOC! > +2. Port 5 is muxed to PHY of port 0/4: Port 0/4 interfaces with 2nd GMAC. > + It is a simple MAC to PHY interface, port 5 needs to be setup for xMII mode > + and RGMII delay. > +3. Port 5 is muxed to GMAC5 and can interface to an external phy. > + Port 5 becomes an extra switch port. > + Only works on platform where external phy TX<->RX lines are swapped. > + Like in the Ubiquiti ER-X-SFP. > +4. Port 5 is muxed to GMAC5 and interfaces with the 2nd GAMC as 2nd CPU port. > + Currently a 2nd CPU port is not supported by DSA code. > + > +Depending on how the external PHY is wired: > +1. normal: The PHY can only connect to 2nd GMAC but not to the switch > +2. swapped: RGMII TX, RX are swapped; external phy interface with the switch as > + a ethernet port. But can't interface to the 2nd GMAC. > + > +Based on the DT the port 5 mode is configured. > + > +Driver tries to lookup the phy-handle of the 2nd GMAC of the master device. > +When phy-handle matches PHY of port 0 or 4 then port 5 set-up as mode 2. > +phy-mode must be set, see also example 2 below! > + * mt7621: phy-mode = "rgmii-txid"; > + * mt7623: phy-mode = "rgmii"; > + > See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional > required, optional properties and how the integrated switch subnodes must > be specified. > @@ -94,3 +130,185 @@ Example: > }; > }; > }; > + > +Example 2: MT7621: Port 4 is WAN port: 2nd GMAC -> Port 5 -> PHY port 4. > + > +ð { > + status = "okay"; Don't show status in examples. This should show the complete node. > + > + gmac0: mac@0 { > + compatible = "mediatek,eth-mac"; > + reg = <0>; > + phy-mode = "rgmii"; > + > + fixed-link { > + speed = <1000>; > + full-duplex; > + pause; > + }; > + }; > + > + gmac1: mac@1 { > + compatible = "mediatek,eth-mac"; > + reg = <1>; > + phy-mode = "rgmii-txid"; > + phy-handle = <&phy4>; > + }; > + > + mdio: mdio-bus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + /* Internal phy */ > + phy4: ethernet-phy@4 { > + reg = <4>; > + }; > + > + mt7530: switch@1f { > + compatible = "mediatek,mt7621"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x1f>; > + pinctrl-names = "default"; > + mediatek,mcm; > + > + resets = <&rstctrl 2>; > + reset-names = "mcm"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + label = "lan0"; > + }; > + > + port@1 { > + reg = <1>; > + label = "lan1"; > + }; > + > + port@2 { > + reg = <2>; > + label = "lan2"; > + }; > + > + port@3 { > + reg = <3>; > + label = "lan3"; > + }; > + > +/* Commented out. Port 4 is handled by 2nd GMAC. > + port@4 { > + reg = <4>; > + label = "lan4"; > + }; > +*/ > + > + cpu_port0: port@6 { > + reg = <6>; > + label = "cpu"; > + ethernet = <&gmac0>; > + phy-mode = "rgmii"; > + > + fixed-link { > + speed = <1000>; > + full-duplex; > + pause; > + }; > + }; > + }; > + }; > + }; > +}; > + > +Example 3: MT7621: Port 5 is connected to external PHY: Port 5 -> external PHY. > + > +ð { > + status = "okay"; > + > + gmac0: mac@0 { > + compatible = "mediatek,eth-mac"; > + reg = <0>; > + phy-mode = "rgmii"; > + > + fixed-link { > + speed = <1000>; > + full-duplex; > + pause; > + }; > + }; > + > + mdio: mdio-bus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + /* External phy */ > + ephy5: ethernet-phy@7 { > + reg = <7>; > + }; > + > + mt7530: switch@1f { > + compatible = "mediatek,mt7621"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x1f>; > + pinctrl-names = "default"; > + mediatek,mcm; > + > + resets = <&rstctrl 2>; > + reset-names = "mcm"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + label = "lan0"; > + }; > + > + port@1 { > + reg = <1>; > + label = "lan1"; > + }; > + > + port@2 { > + reg = <2>; > + label = "lan2"; > + }; > + > + port@3 { > + reg = <3>; > + label = "lan3"; > + }; > + > + port@4 { > + reg = <4>; > + label = "lan4"; > + }; > + > + port@5 { > + reg = <5>; > + label = "lan5"; > + phy-mode = "rgmii"; > + phy-handle = <&ephy5>; > + }; > + > + cpu_port0: port@6 { > + reg = <6>; > + label = "cpu"; > + ethernet = <&gmac0>; > + phy-mode = "rgmii"; > + > + fixed-link { > + speed = <1000>; > + full-duplex; > + pause; > + }; > + }; > + }; > + }; > + }; > +}; > -- > 2.20.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply index Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-08-21 14:45 [PATCH net-next v2 0/3] net: dsa: mt7530: Convert to PHYLINK and add " René van Dorst 2019-08-21 14:45 ` [PATCH net-next v2 1/3] net: dsa: mt7530: Convert to PHYLINK API René van Dorst 2019-08-21 14:45 ` [PATCH net-next v2 2/3] dt-bindings: net: dsa: mt7530: Add support for port 5 René van Dorst 2019-08-27 22:22 ` Rob Herring [this message] 2019-08-28 6:35 ` René van Dorst 2019-08-30 17:16 ` René van Dorst 2019-08-21 14:45 ` [PATCH net-next v2 3/3] " René van Dorst 2019-08-24 23:19 ` David Miller 2019-08-25 12:48 ` René van Dorst 2019-08-21 21:05 ` [PATCH net-next v2 0/3] net: dsa: mt7530: Convert to PHYLINK and add " Andrew Lunn 2019-08-22 15:44 ` Aw: " Frank Wunderlich 2019-08-22 16:26 ` Frank Wunderlich 2019-08-22 23:20 ` David Miller 2019-08-23 1:09 ` Andrew Lunn 2019-08-24 21:18 ` David Miller 2019-08-24 22:15 ` Andrew Lunn 2019-08-24 22:31 ` Russell King - ARM Linux admin 2019-08-24 22:18 ` Russell King - ARM Linux admin 2019-08-24 22:29 ` Russell King - ARM Linux admin 2019-08-25 13:15 ` René van Dorst
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20190827222251.GA30507@bogus \ --to=robh@kernel.org \ --cc=andrew@lunn.ch \ --cc=davem@davemloft.net \ --cc=devicetree@vger.kernel.org \ --cc=f.fainelli@gmail.com \ --cc=frank-w@public-files.de \ --cc=john@phrozen.org \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-mediatek@lists.infradead.org \ --cc=linux-mips@vger.kernel.org \ --cc=matthias.bgg@gmail.com \ --cc=netdev@vger.kernel.org \ --cc=opensource@vdorst.com \ --cc=sean.wang@mediatek.com \ --cc=vivien.didelot@gmail.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: link
Linux-ARM-Kernel Archive on lore.kernel.org Archives are clonable: git clone --mirror https://lore.kernel.org/linux-arm-kernel/0 linux-arm-kernel/git/0.git git clone --mirror https://lore.kernel.org/linux-arm-kernel/1 linux-arm-kernel/git/1.git # If you have public-inbox 1.1+ installed, you may # initialize and index your mirror using the following commands: public-inbox-init -V2 linux-arm-kernel linux-arm-kernel/ https://lore.kernel.org/linux-arm-kernel \ linux-arm-kernel@lists.infradead.org public-inbox-index linux-arm-kernel Example config snippet for mirrors Newsgroup available over NNTP: nntp://nntp.lore.kernel.org/org.infradead.lists.linux-arm-kernel AGPL code for this site: git clone https://public-inbox.org/public-inbox.git