[PATCH] arm64: dts: allwinner: a64: pine64-plus: Add PHY regulator delay

[PATCH] arm64: dts: allwinner: a64: pine64-plus: Add PHY regulator delay

[Jernej Skrabec]

Depending on kernel and bootloader configuration, it's possible that
Realtek ethernet PHY isn't powered on properly. It needs some time
before it can be used.

Fix that by adding 100ms ramp delay to regulator responsible for
powering PHY.

Fixes: 94dcfdc77fc5 ("arm64: allwinner: pine64-plus: Enable dwmac-sun8i")
Suggested-by: Ondrej Jirman <megous@megous.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
index 24f1aac366d6..9612a34c1762 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
@@ -63,3 +63,7 @@
 		reg = <1>;
 	};
 };
+
+&reg_dc1sw {
+	regulator-enable-ramp-delay = <100000>;
+};
-- 
2.23.0


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Re: [PATCH] arm64: dts: allwinner: a64: pine64-plus: Add PHY regulator delay

[Maxime Ripard]

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On Sun, Aug 25, 2019 at 03:03:36PM +0200, Jernej Skrabec wrote:
> Depending on kernel and bootloader configuration, it's possible that
> Realtek ethernet PHY isn't powered on properly. It needs some time
> before it can be used.
>
> Fix that by adding 100ms ramp delay to regulator responsible for
> powering PHY.
>
> Fixes: 94dcfdc77fc5 ("arm64: allwinner: pine64-plus: Enable dwmac-sun8i")
> Suggested-by: Ondrej Jirman <megous@megous.com>
> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>

How was that delay found?

It should at least have a comment explaining why it's there.

Thanks!
Maxime

--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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Re: [PATCH] arm64: dts: allwinner: a64: pine64-plus: Add PHY regulator delay

[Ondřej Jirman]

Hi,

On Tue, Aug 27, 2019 at 03:34:43PM +0200, Maxime Ripard wrote:
> On Sun, Aug 25, 2019 at 03:03:36PM +0200, Jernej Skrabec wrote:
> > Depending on kernel and bootloader configuration, it's possible that
> > Realtek ethernet PHY isn't powered on properly. It needs some time
> > before it can be used.
> >
> > Fix that by adding 100ms ramp delay to regulator responsible for
> > powering PHY.
> >
> > Fixes: 94dcfdc77fc5 ("arm64: allwinner: pine64-plus: Enable dwmac-sun8i")
> > Suggested-by: Ondrej Jirman <megous@megous.com>
> > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> 
> How was that delay found?

I suggested it. There's no delay in the dwmac-sun8i driver, so after enabling
the phy power, it will start accessing it over MDIO right away, which is not
good.

I suggested the value based on post-reset delay in the PHY's datasheet (30ms).
Multiplied ~3x (if I remember correctly) to get some safety margin. Chip has
more to do then after the HW reset, and regulator also needs some time to
ramp-up.

regards,
	o.

> It should at least have a comment explaining why it's there.
> 
> Thanks!
> Maxime
> 
> --
> Maxime Ripard, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com



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Re: [PATCH] arm64: dts: allwinner: a64: pine64-plus: Add PHY regulator delay

[Maxime Ripard]

On Tue, Aug 27, 2019 at 03:48:06PM +0200, Ondřej Jirman wrote:
> Hi,
>
> On Tue, Aug 27, 2019 at 03:34:43PM +0200, Maxime Ripard wrote:
> > On Sun, Aug 25, 2019 at 03:03:36PM +0200, Jernej Skrabec wrote:
> > > Depending on kernel and bootloader configuration, it's possible that
> > > Realtek ethernet PHY isn't powered on properly. It needs some time
> > > before it can be used.
> > >
> > > Fix that by adding 100ms ramp delay to regulator responsible for
> > > powering PHY.
> > >
> > > Fixes: 94dcfdc77fc5 ("arm64: allwinner: pine64-plus: Enable dwmac-sun8i")
> > > Suggested-by: Ondrej Jirman <megous@megous.com>
> > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> >
> > How was that delay found?
>
> I suggested it. There's no delay in the dwmac-sun8i driver, so after enabling
> the phy power, it will start accessing it over MDIO right away, which is not
> good.
>
> I suggested the value based on post-reset delay in the PHY's datasheet (30ms).
> Multiplied ~3x (if I remember correctly) to get some safety margin. Chip has
> more to do then after the HW reset, and regulator also needs some time to
> ramp-up.

That sounds reasonable, can you add that as a comment?

Thanks!
Maxime

--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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