From: Andrew Murray <andrew.murray@arm.com>
To: Neil Armstrong <narmstrong@baylibre.com>
Cc: lorenzo.pieralisi@arm.com, khilman@baylibre.com,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
kishon@ti.com, repk@triplefau.lt, maz@kernel.org,
bhelgaas@google.com, linux-amlogic@lists.infradead.org,
yue.wang@Amlogic.com, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 4/6] phy: meson-g12a-usb3-pcie: Add support for PCIe mode
Date: Wed, 11 Sep 2019 13:59:58 +0100 [thread overview]
Message-ID: <20190911125958.GW9720@e119886-lin.cambridge.arm.com> (raw)
In-Reply-To: <e4249d3a-9a98-c596-01ae-2917ffd78f17@baylibre.com>
On Wed, Sep 11, 2019 at 02:45:23PM +0200, Neil Armstrong wrote:
> On 11/09/2019 14:19, Andrew Murray wrote:
> > On Sun, Sep 08, 2019 at 01:42:56PM +0000, Neil Armstrong wrote:
> >> This adds extended PCIe PHY functions for the Amlogic G12A
> >> USB3+PCIE Combo PHY to support reset, power_on and power_off for
> >> PCIe exclusively.
> >>
> >> With these callbacks, we can handle all the needed operations of the
> >> Amlogic PCIe controller driver.
> >>
> >> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
> >> ---
> >> .../phy/amlogic/phy-meson-g12a-usb3-pcie.c | 70 ++++++++++++++++---
> >> 1 file changed, 61 insertions(+), 9 deletions(-)
> >>
> >> diff --git a/drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c b/drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c
> >> index ac322d643c7a..08e322789e59 100644
> >> --- a/drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c
> >> +++ b/drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c
> >> @@ -50,6 +50,8 @@
> >> #define PHY_R5_PHY_CR_ACK BIT(16)
> >> #define PHY_R5_PHY_BS_OUT BIT(17)
> >>
> >> +#define PCIE_RESET_DELAY 500
> >> +
> >> struct phy_g12a_usb3_pcie_priv {
> >> struct regmap *regmap;
> >> struct regmap *regmap_cr;
> >> @@ -196,6 +198,10 @@ static int phy_g12a_usb3_init(struct phy *phy)
> >> struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
> >> int data, ret;
> >>
> >> + ret = reset_control_reset(priv->reset);
> >> + if (ret)
> >> + return ret;
> >> +
> >
> > Right, so we've moved this to apply to USB only, thus assuming PCI will
> > call .reset for its reset (why the asymmetry?).
>
> Exact, there is no power_on/power_off when USB3 mode is used, and vendor
> always reset the PHY before switching to USB3, but for PCIe, it seems the
> reset and the power_on must be done separately with the PCIe controller init
> and reset in the middle.
>
> I would prefer symmetry aswell :-/
OK.
Thanks,
Andrew Murray
>
> Neil
>
> >
> > Thanks,
> >
> > Andrew Murray
> >
> >> /* Switch PHY to USB3 */
> >> /* TODO figure out how to handle when PCIe was set in the bootloader */
> >> regmap_update_bits(priv->regmap, PHY_R0,
> >> @@ -272,24 +278,64 @@ static int phy_g12a_usb3_init(struct phy *phy)
> >> return 0;
> >> }
> >>
> >> -static int phy_g12a_usb3_pcie_init(struct phy *phy)
> >> +static int phy_g12a_usb3_pcie_power_on(struct phy *phy)
> >> +{
> >> + struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
> >> +
> >> + if (priv->mode == PHY_TYPE_USB3)
> >> + return 0;
> >> +
> >> + regmap_update_bits(priv->regmap, PHY_R0,
> >> + PHY_R0_PCIE_POWER_STATE,
> >> + FIELD_PREP(PHY_R0_PCIE_POWER_STATE, 0x1c));
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +static int phy_g12a_usb3_pcie_power_off(struct phy *phy)
> >> +{
> >> + struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
> >> +
> >> + if (priv->mode == PHY_TYPE_USB3)
> >> + return 0;
> >> +
> >> + regmap_update_bits(priv->regmap, PHY_R0,
> >> + PHY_R0_PCIE_POWER_STATE,
> >> + FIELD_PREP(PHY_R0_PCIE_POWER_STATE, 0x1d));
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +static int phy_g12a_usb3_pcie_reset(struct phy *phy)
> >> {
> >> struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
> >> int ret;
> >>
> >> - ret = reset_control_reset(priv->reset);
> >> + if (priv->mode == PHY_TYPE_USB3)
> >> + return 0;
> >> +
> >> + ret = reset_control_assert(priv->reset);
> >> if (ret)
> >> return ret;
> >>
> >> + udelay(PCIE_RESET_DELAY);
> >> +
> >> + ret = reset_control_deassert(priv->reset);
> >> + if (ret)
> >> + return ret;
> >> +
> >> + udelay(PCIE_RESET_DELAY);
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +static int phy_g12a_usb3_pcie_init(struct phy *phy)
> >> +{
> >> + struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
> >> +
> >> if (priv->mode == PHY_TYPE_USB3)
> >> return phy_g12a_usb3_init(phy);
> >>
> >> - /* Power UP PCIE */
> >> - /* TODO figure out when the bootloader has set USB3 mode before */
> >> - regmap_update_bits(priv->regmap, PHY_R0,
> >> - PHY_R0_PCIE_POWER_STATE,
> >> - FIELD_PREP(PHY_R0_PCIE_POWER_STATE, 0x1c));
> >> -
> >> return 0;
> >> }
> >>
> >> @@ -297,7 +343,10 @@ static int phy_g12a_usb3_pcie_exit(struct phy *phy)
> >> {
> >> struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
> >>
> >> - return reset_control_reset(priv->reset);
> >> + if (priv->mode == PHY_TYPE_USB3)
> >> + return reset_control_reset(priv->reset);
> >> +
> >> + return 0;
> >> }
> >>
> >> static struct phy *phy_g12a_usb3_pcie_xlate(struct device *dev,
> >> @@ -326,6 +375,9 @@ static struct phy *phy_g12a_usb3_pcie_xlate(struct device *dev,
> >> static const struct phy_ops phy_g12a_usb3_pcie_ops = {
> >> .init = phy_g12a_usb3_pcie_init,
> >> .exit = phy_g12a_usb3_pcie_exit,
> >> + .power_on = phy_g12a_usb3_pcie_power_on,
> >> + .power_off = phy_g12a_usb3_pcie_power_off,
> >> + .reset = phy_g12a_usb3_pcie_reset,
> >> .owner = THIS_MODULE,
> >> };
> >>
> >> --
> >> 2.17.1
> >>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-09-11 13:00 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-08 13:42 [PATCH 0/6] arm64: dts: meson-g12: add support for PCIe Neil Armstrong
2019-09-08 13:42 ` [PATCH 1/6] dt-bindings: pci: amlogic,meson-pcie: Add G12A bindings Neil Armstrong
2019-09-11 12:22 ` Andrew Murray
2019-09-11 12:30 ` Neil Armstrong
2019-09-13 14:36 ` [PATCH 1/6] dt-bindings: pci: amlogic, meson-pcie: " Rob Herring
2019-09-08 13:42 ` [PATCH 2/6] PCI: amlogic: Fix probed clock names Neil Armstrong
2019-09-11 10:59 ` Andrew Murray
2019-09-08 13:42 ` [PATCH 3/6] PCI: amlogic: meson: Add support for G12A Neil Armstrong
2019-09-11 11:36 ` Andrew Murray
2019-09-11 12:39 ` Neil Armstrong
2019-09-11 12:58 ` Andrew Murray
2019-09-08 13:42 ` [PATCH 4/6] phy: meson-g12a-usb3-pcie: Add support for PCIe mode Neil Armstrong
2019-09-11 12:19 ` Andrew Murray
2019-09-11 12:45 ` Neil Armstrong
2019-09-11 12:59 ` Andrew Murray [this message]
2019-09-08 13:42 ` [PATCH 5/6] arm64: dts: meson-g12a: Add PCIe node Neil Armstrong
2019-09-08 13:42 ` [PATCH 6/6] arm64: dts: khadas-vim3: add commented support for PCIe Neil Armstrong
2019-09-09 16:37 ` Marc Zyngier
2019-09-09 17:50 ` Neil Armstrong
2019-09-10 9:12 ` Marc Zyngier
2019-09-10 9:14 ` Neil Armstrong
2019-09-11 12:50 ` Andrew Murray
2019-09-11 12:58 ` Neil Armstrong
2019-09-11 13:11 ` Andrew Murray
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190911125958.GW9720@e119886-lin.cambridge.arm.com \
--to=andrew.murray@arm.com \
--cc=bhelgaas@google.com \
--cc=khilman@baylibre.com \
--cc=kishon@ti.com \
--cc=linux-amlogic@lists.infradead.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=maz@kernel.org \
--cc=narmstrong@baylibre.com \
--cc=repk@triplefau.lt \
--cc=yue.wang@Amlogic.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).